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/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dtpc0_qm_masks.h23 #define TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define TPC0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define TPC0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define TPC0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define TPC0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define TPC0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define TPC0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define TPC0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define TPC0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
[all …]
H A Dnic0_qm0_masks.h23 #define NIC0_QM0_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define NIC0_QM0_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define NIC0_QM0_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define NIC0_QM0_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define NIC0_QM0_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define NIC0_QM0_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define NIC0_QM0_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define NIC0_QM0_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define NIC0_QM0_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
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H A Dmme0_qm_masks.h23 #define MME0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define MME0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define MME0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define MME0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define MME0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define MME0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define MME0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define MME0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define MME0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define MME0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
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H A Ddma0_qm_masks.h23 #define DMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
24 #define DMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
26 #define DMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
28 #define DMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
32 #define DMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
34 #define DMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
36 #define DMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
38 #define DMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
40 #define DMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000
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/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_edma0_qm_masks.h24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
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H A Dpdma0_qm_masks.h24 #define PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0
25 #define PDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF
27 #define PDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0
29 #define PDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00
31 #define PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000
34 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0
35 #define PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF
37 #define PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0
39 #define PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00
41 #define PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000
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H A Ddcore0_tpc0_eml_stm_regs.h23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
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H A Ddcore0_mme_ctrl_lo_masks.h24 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0
25 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F
27 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20
29 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40
31 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180
33 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00
35 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000
37 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000
39 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000
41 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000
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/openbmc/qemu/include/hw/timer/
H A Dhpet.h19 #define HPET_BASE 0xfed00000
20 #define HPET_LEN 0x400
29 #define HPET_LEGACY_PIT_INT 0
32 #define HPET_CFG_ENABLE 0x001
33 #define HPET_CFG_LEGACY 0x002
35 #define HPET_ID 0x000
36 #define HPET_PERIOD 0x004
37 #define HPET_CFG 0x010
38 #define HPET_STATUS 0x020
39 #define HPET_COUNTER 0x0f0
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/openbmc/linux/arch/mips/include/asm/
H A Dhpet.h9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
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/openbmc/linux/sound/pci/
H A Dad1889.h9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
11 #define AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */
12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
15 #define AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */
17 #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
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/openbmc/linux/arch/x86/include/asm/
H A Dhpet.h11 #define HPET_ID 0x000
12 #define HPET_PERIOD 0x004
13 #define HPET_CFG 0x010
14 #define HPET_STATUS 0x020
15 #define HPET_COUNTER 0x0f0
17 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
18 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
19 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
21 #define HPET_T0_CFG 0x100
22 #define HPET_T0_CMP 0x108
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/openbmc/linux/drivers/mfd/
H A Dwm97xx-core.c23 #define WM9705_VENDOR_ID 0x574d4c05
24 #define WM9712_VENDOR_ID 0x574d4c12
25 #define WM9713_VENDOR_ID 0x574d4c13
26 #define WM97xx_VENDOR_ID_MASK 0xffffffff
42 case AC97_GPIO_CFG ... 0x5c: in wm97xx_readable_reg()
44 case 0x74 ... AC97_VENDOR_ID2: in wm97xx_readable_reg()
63 { 0x02, 0x8000 },
64 { 0x04, 0x8000 },
65 { 0x06, 0x8000 },
66 { 0x0a, 0x8000 },
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/openbmc/linux/sound/soc/codecs/
H A Dtfa9879.h12 #define TFA9879_DEVICE_CONTROL 0x00
13 #define TFA9879_SERIAL_INTERFACE_1 0x01
14 #define TFA9879_PCM_IOM2_FORMAT_1 0x02
15 #define TFA9879_SERIAL_INTERFACE_2 0x03
16 #define TFA9879_PCM_IOM2_FORMAT_2 0x04
17 #define TFA9879_EQUALIZER_A1 0x05
18 #define TFA9879_EQUALIZER_A2 0x06
19 #define TFA9879_EQUALIZER_B1 0x07
20 #define TFA9879_EQUALIZER_B2 0x08
21 #define TFA9879_EQUALIZER_C1 0x09
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/openbmc/linux/drivers/media/tuners/
H A Dmc44s803_priv.h14 SPI or I2C Address : 0xc0-0xc6
28 0A | LNA AGC
29 0B | Data Register Address
30 0C | Regulator Test
31 0D | VCO Test
32 0E | LNA Gain/Input Power
33 0F | ID Bits
41 #define MC44S803_REG_POWER 0
51 #define MC44S803_REG_LNAAGC 0x0A
52 #define MC44S803_REG_DATAREG 0x0B
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/openbmc/linux/drivers/media/usb/go7007/
H A Dgo7007-fw.c40 #define SPECIAL_FRM_HEAD 0
58 #define CODE_GEN(name, dest) struct code_gen name = { dest, 0, 32, 0 }
70 } while (0)
169 { 0x01, 1 }, { 0x03, 3 }, { 0x02, 3 }, { 0x03, 4 },
170 { 0x02, 4 }, { 0x03, 5 }, { 0x02, 5 }, { 0x07, 7 },
171 { 0x06, 7 }, { 0x0b, 8 }, { 0x0a, 8 }, { 0x09, 8 },
172 { 0x08, 8 }, { 0x07, 8 }, { 0x06, 8 }, { 0x17, 10 },
173 { 0x16, 10 }, { 0x15, 10 }, { 0x14, 10 }, { 0x13, 10 },
174 { 0x12, 10 }, { 0x23, 11 }, { 0x22, 11 }, { 0x21, 11 },
175 { 0x20, 11 }, { 0x1f, 11 }, { 0x1e, 11 }, { 0x1d, 11 },
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/openbmc/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h14 #define PCI_DEVID_CN10K_RPM 0xA060
15 #define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00
16 #define PCI_DEVID_CN10KB_RPM 0xA09F
19 #define RPMX_CMRX_CFG 0x00
20 #define RPMX_CMR_GLOBAL_CFG 0x08
24 #define RPMX_CMRX_RX_ID_MAP 0x80
25 #define RPMX_CMRX_SW_INT 0x180
26 #define RPMX_CMRX_SW_INT_W1S 0x188
27 #define RPMX_CMRX_SW_INT_ENA_W1S 0x198
28 #define RPMX_CMRX_LINK_CFG 0x1070
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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/openbmc/u-boot/arch/arm/mach-at91/arm920t/
H A Dclock.c37 return 0; in at91_css_to_rate()
43 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc()
44 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; in at91_pll_calc()
72 if (diff1 < 0) in at91_pll_calc()
78 if (diff == 0) in at91_pll_calc()
86 return 0; in at91_pll_calc()
94 div = reg & 0xff; in at91_pll_rate()
95 mul = (reg >> 16) & 0x7ff; in at91_pll_rate()
100 freq = 0; in at91_pll_rate()
157 return 0; in at91_clock_init()
[all …]
/openbmc/linux/drivers/net/wireless/ti/wl18xx/
H A Dreg.h11 #define WL18XX_REGISTERS_BASE 0x00800000
12 #define WL18XX_CODE_BASE 0x00000000
13 #define WL18XX_DATA_BASE 0x00400000
14 #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000
15 #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000
16 #define WL18XX_PHY_BASE 0x00900000
17 #define WL18XX_TOP_OCP_BASE 0x00A00000
18 #define WL18XX_PACKET_RAM_BASE 0x00B00000
19 #define WL18XX_HOST_BASE 0x00C00000
21 #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000
[all …]
/openbmc/u-boot/include/configs/
H A Dlx2160a_common.h20 #define CONFIG_SYS_FLASH_BASE 0x20000000
29 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
30 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
31 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
33 #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39 #define SPD_EEPROM_ADDRESS1 0x51
40 #define SPD_EEPROM_ADDRESS2 0x52
41 #define SPD_EEPROM_ADDRESS3 0x53
42 #define SPD_EEPROM_ADDRESS4 0x54
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc885ads.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xff000100 0x40>;
48 0x0 0x0 0xfe000000 0x800000
49 0x1 0x0 0xff080000 0x8000
[all …]
/openbmc/linux/drivers/phy/marvell/
H A Dphy-mmp3-usb.c15 #define USB2_PLL_REG0 0x4
16 #define USB2_PLL_REG1 0x8
17 #define USB2_TX_REG0 0x10
18 #define USB2_TX_REG1 0x14
19 #define USB2_TX_REG2 0x18
20 #define USB2_RX_REG0 0x20
21 #define USB2_RX_REG1 0x24
22 #define USB2_RX_REG2 0x28
23 #define USB2_ANA_REG0 0x30
24 #define USB2_ANA_REG1 0x34
[all …]
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dclock.c37 return 0; in at91_css_to_rate()
43 unsigned i, div = 0, mul = 0, diff = 1 << 30; in at91_pll_calc()
44 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; in at91_pll_calc()
80 if (diff1 < 0) in at91_pll_calc()
86 if (diff == 0) in at91_pll_calc()
94 return 0; in at91_pll_calc()
102 div = reg & 0xff; in at91_pll_rate()
103 mul = (reg >> 16) & 0x7ff; in at91_pll_rate()
108 freq = 0; in at91_pll_rate()
180 * 0 <==> 1 in at91_clock_init()
[all …]
/openbmc/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_wqe.h12 #define HINIC_CMDQ_CTRL_PI_SHIFT 0
18 #define HINIC_CMDQ_CTRL_PI_MASK 0xFFFF
19 #define HINIC_CMDQ_CTRL_CMD_MASK 0xFF
20 #define HINIC_CMDQ_CTRL_MOD_MASK 0x1F
21 #define HINIC_CMDQ_CTRL_ACK_TYPE_MASK 0x3
22 #define HINIC_CMDQ_CTRL_HW_BUSY_BIT_MASK 0x1
32 #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_SHIFT 0
40 #define HINIC_CMDQ_WQE_HEADER_BUFDESC_LEN_MASK 0xFF
41 #define HINIC_CMDQ_WQE_HEADER_COMPLETE_FMT_MASK 0x1
42 #define HINIC_CMDQ_WQE_HEADER_DATA_FMT_MASK 0x1
[all …]

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