37 	return 0;  in at91_css_to_rate()
43 	unsigned i, div = 0, mul = 0, diff = 1 << 30;  in at91_pll_calc()
44 	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;  in at91_pll_calc()
80 		if (diff1 < 0)  in at91_pll_calc()
86 			if (diff == 0)  in at91_pll_calc()
94 	return 0;  in at91_pll_calc()
102 	div = reg & 0xff;  in at91_pll_rate()
103 	mul = (reg >> 16) & 0x7ff;  in at91_pll_rate()
108 		freq = 0;  in at91_pll_rate()
180 	 *  0   <==>   1  in at91_clock_init()
195 	return 0;  in at91_clock_init()
258 	start_time = get_timer(0);  in at91_pllb_clk_enable()
261 		tmp_time = get_timer(0);  in at91_pllb_clk_enable()
268 	return 0;  in at91_pllb_clk_enable()
276 	start_time = get_timer(0);  in at91_pllb_clk_disable()
277 	writel(0, &pmc->pllbr);  in at91_pllb_clk_disable()
278 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {  in at91_pllb_clk_disable()
279 		tmp_time = get_timer(0);  in at91_pllb_clk_disable()
286 	return 0;  in at91_pllb_clk_disable()