1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2e292ccdeSHuacai Chen #ifndef _ASM_HPET_H 3e292ccdeSHuacai Chen #define _ASM_HPET_H 4e292ccdeSHuacai Chen 5e292ccdeSHuacai Chen #ifdef CONFIG_RS780_HPET 6e292ccdeSHuacai Chen 7e292ccdeSHuacai Chen #define HPET_MMAP_SIZE 1024 8e292ccdeSHuacai Chen 9e292ccdeSHuacai Chen #define HPET_ID 0x000 10e292ccdeSHuacai Chen #define HPET_PERIOD 0x004 11e292ccdeSHuacai Chen #define HPET_CFG 0x010 12e292ccdeSHuacai Chen #define HPET_STATUS 0x020 13e292ccdeSHuacai Chen #define HPET_COUNTER 0x0f0 14e292ccdeSHuacai Chen 15e292ccdeSHuacai Chen #define HPET_Tn_CFG(n) (0x100 + 0x20 * n) 16e292ccdeSHuacai Chen #define HPET_Tn_CMP(n) (0x108 + 0x20 * n) 17e292ccdeSHuacai Chen #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n) 18e292ccdeSHuacai Chen 19e292ccdeSHuacai Chen #define HPET_T0_IRS 0x001 20e292ccdeSHuacai Chen #define HPET_T1_IRS 0x002 21e292ccdeSHuacai Chen #define HPET_T3_IRS 0x004 22e292ccdeSHuacai Chen 23e292ccdeSHuacai Chen #define HPET_T0_CFG 0x100 24e292ccdeSHuacai Chen #define HPET_T0_CMP 0x108 25e292ccdeSHuacai Chen #define HPET_T0_ROUTE 0x110 26e292ccdeSHuacai Chen #define HPET_T1_CFG 0x120 27e292ccdeSHuacai Chen #define HPET_T1_CMP 0x128 28e292ccdeSHuacai Chen #define HPET_T1_ROUTE 0x130 29e292ccdeSHuacai Chen #define HPET_T2_CFG 0x140 30e292ccdeSHuacai Chen #define HPET_T2_CMP 0x148 31e292ccdeSHuacai Chen #define HPET_T2_ROUTE 0x150 32e292ccdeSHuacai Chen 33e292ccdeSHuacai Chen #define HPET_ID_REV 0x000000ff 34e292ccdeSHuacai Chen #define HPET_ID_NUMBER 0x00001f00 35e292ccdeSHuacai Chen #define HPET_ID_64BIT 0x00002000 36e292ccdeSHuacai Chen #define HPET_ID_LEGSUP 0x00008000 37e292ccdeSHuacai Chen #define HPET_ID_VENDOR 0xffff0000 38e292ccdeSHuacai Chen #define HPET_ID_NUMBER_SHIFT 8 39e292ccdeSHuacai Chen #define HPET_ID_VENDOR_SHIFT 16 40e292ccdeSHuacai Chen 41e292ccdeSHuacai Chen #define HPET_CFG_ENABLE 0x001 42e292ccdeSHuacai Chen #define HPET_CFG_LEGACY 0x002 43e292ccdeSHuacai Chen #define HPET_LEGACY_8254 2 44e292ccdeSHuacai Chen #define HPET_LEGACY_RTC 8 45e292ccdeSHuacai Chen 46e292ccdeSHuacai Chen #define HPET_TN_LEVEL 0x0002 47e292ccdeSHuacai Chen #define HPET_TN_ENABLE 0x0004 48e292ccdeSHuacai Chen #define HPET_TN_PERIODIC 0x0008 49e292ccdeSHuacai Chen #define HPET_TN_PERIODIC_CAP 0x0010 50e292ccdeSHuacai Chen #define HPET_TN_64BIT_CAP 0x0020 51e292ccdeSHuacai Chen #define HPET_TN_SETVAL 0x0040 52e292ccdeSHuacai Chen #define HPET_TN_32BIT 0x0100 53e292ccdeSHuacai Chen #define HPET_TN_ROUTE 0x3e00 54e292ccdeSHuacai Chen #define HPET_TN_FSB 0x4000 55e292ccdeSHuacai Chen #define HPET_TN_FSB_CAP 0x8000 56e292ccdeSHuacai Chen #define HPET_TN_ROUTE_SHIFT 9 57e292ccdeSHuacai Chen 58e292ccdeSHuacai Chen /* Max HPET Period is 10^8 femto sec as in HPET spec */ 59e292ccdeSHuacai Chen #define HPET_MAX_PERIOD 100000000UL 60e292ccdeSHuacai Chen /* 61e292ccdeSHuacai Chen * Min HPET period is 10^5 femto sec just for safety. If it is less than this, 62e292ccdeSHuacai Chen * then 32 bit HPET counter wrapsaround in less than 0.5 sec. 63e292ccdeSHuacai Chen */ 64e292ccdeSHuacai Chen #define HPET_MIN_PERIOD 100000UL 65e292ccdeSHuacai Chen 66e292ccdeSHuacai Chen #define HPET_ADDR 0x20000 67e292ccdeSHuacai Chen #define HPET_MMIO_ADDR 0x90000e0000020000 68e292ccdeSHuacai Chen #define HPET_FREQ 14318780 69e292ccdeSHuacai Chen #define HPET_COMPARE_VAL ((HPET_FREQ + HZ / 2) / HZ) 70e292ccdeSHuacai Chen #define HPET_T0_IRQ 0 71e292ccdeSHuacai Chen 72e292ccdeSHuacai Chen extern void __init setup_hpet_timer(void); 73e292ccdeSHuacai Chen #endif /* CONFIG_RS780_HPET */ 74e292ccdeSHuacai Chen #endif /* _ASM_HPET_H */ 75