Lines Matching +full:0 +full:x3e00
20 #define CONFIG_SYS_FLASH_BASE 0x20000000
29 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
30 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
31 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
33 #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL
38 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
39 #define SPD_EEPROM_ADDRESS1 0x51
40 #define SPD_EEPROM_ADDRESS2 0x52
41 #define SPD_EEPROM_ADDRESS3 0x53
42 #define SPD_EEPROM_ADDRESS4 0x54
43 #define SPD_EEPROM_ADDRESS5 0x55
44 #define SPD_EEPROM_ADDRESS6 0x56
46 #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
53 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
61 * will be udpated later when get_bus_freq(0) is available.
71 #define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4)
72 #define CONFIG_SYS_SERIAL0 0x21c0000
73 #define CONFIG_SYS_SERIAL1 0x21d0000
74 #define CONFIG_SYS_SERIAL2 0x21e0000
75 #define CONFIG_SYS_SERIAL3 0x21f0000
85 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
86 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
87 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
88 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
107 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
108 #define I2C_MUX_CH_DEFAULT 0x8
112 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
117 #define CONFIG_SYS_EEPROM_BUS_NUM 0
118 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
126 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
175 #define CONFIG_SYS_MMC_ENV_DEV 0
176 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
177 #define CONFIG_ENV_SECT_SIZE 0x20000
178 #define CONFIG_ENV_OFFSET 0x500000
198 "esbc_validate 0x20700000 && " \
199 "esbc_validate 0x20740000 ;" \
200 "fsl_mc start mc 0x20a00000 0x20e00000\0"
203 "mmc read 0x80000000 0x5000 0x800;" \
204 "mmc read 0x80100000 0x7000 0x800;" \
206 "mmc read 0x80700000 0x3800 0x10 && " \
207 "mmc read 0x80740000 0x3A00 0x10 && " \
208 "esbc_validate 0x80700000 && " \
209 "esbc_validate 0x80740000 ;" \
210 "fsl_mc start mc 0x80000000 0x80100000\0"
213 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
214 "ramdisk_addr=0x800000\0" \
215 "ramdisk_size=0x2000000\0" \
216 "fdt_high=0xa0000000\0" \
217 "initrd_high=0xffffffffffffffff\0" \
218 "fdt_addr=0x64f00000\0" \
219 "kernel_start=0x1000000\0" \
220 "kernelheader_start=0x7C0000\0" \
221 "scriptaddr=0x80000000\0" \
222 "scripthdraddr=0x80080000\0" \
223 "fdtheader_addr_r=0x80100000\0" \
224 "kernelheader_addr_r=0x80200000\0" \
225 "kernel_addr_r=0x81000000\0" \
226 "kernelheader_size=0x40000\0" \
227 "fdt_addr_r=0x90000000\0" \
228 "load_addr=0xa0000000\0" \
229 "kernel_size=0x2800000\0" \
230 "kernel_addr_sd=0x8000\0" \
231 "kernelhdr_addr_sd=0x3E00\0" \
232 "kernel_size_sd=0x1d000\0" \
233 "kernelhdr_size_sd=0x10\0" \
234 "console=ttyAMA0,38400n8\0" \
236 "mcmemsize=0x70000000\0" \
238 "boot_scripts=lx2160ardb_boot.scr\0" \
239 "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
249 "done\0" \
255 "done;\0" \
263 "source ${scriptaddr}\0"
267 "&& esbc_validate 0x20780000; " \
269 "fsl_mc lazyapply dpl 0x20d00000; " \
275 "mmc read 0x80001000 0x6800 0x800; " \
277 " && mmc read 0x80780000 0x3C00 0x10 " \
278 "&& esbc_validate 0x80780000;env exists mcinitcmd " \
279 "&& fsl_mc lazyapply dpl 0x80001000;" \
284 func(USB, usb, 0) \
285 func(MMC, mmc, 0) \
286 func(SCSI, scsi, 0)