/openbmc/linux/arch/arm/mm/ |
H A D | cache-fa.S | 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 65 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 67 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 68 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 90 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 91 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 96 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 126 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 127 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 132 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB [all …]
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H A D | cache-v6.S | 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 66 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 145 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 150 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB [all …]
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H A D | proc-arm926.S | 69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 72 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 109 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 134 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test,clean,invalidate 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 163 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
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H A D | proc-arm925.S | 109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 112 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 143 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 170 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 197 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
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H A D | proc-mohawk.S | 62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 92 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 116 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 138 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 139 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 141 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 178 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
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H A D | proc-arm920.S | 77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 80 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 213 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 218 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
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H A D | proc-arm922.S | 79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 82 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 110 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 196 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 215 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 220 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
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H A D | cache-v4wt.S | 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 70 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 71 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 89 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 91 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 122 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 140 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 157 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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H A D | proc-fa526.S | 58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 61 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 104 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 106 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 108 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 109 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 113 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB 137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 140 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 142 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM [all …]
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H A D | proc-arm1022.S | 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 267 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
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H A D | proc-arm1026.S | 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 141 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 @ test, clean, invalidate 146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 175 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 232 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 261 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
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H A D | proc-arm946.S | 83 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 140 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 144 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 147 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 184 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
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H A D | proc-arm1020e.S | 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 181 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 267 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
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H A D | tlb-v7.S | 49 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 51 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 53 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA 78 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 80 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 82 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
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H A D | tlb-v6.S | 48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
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H A D | proc-arm1020.S | 85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 88 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 118 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 144 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 153 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 176 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 222 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 244 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 278 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
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H A D | proc-feroceon.S | 95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 98 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 127 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 181 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 182 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 184 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 185 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
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H A D | proc-xsc3.S | 68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 149 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 202 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 245 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line [all …]
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H A D | cache-v4wb.S | 58 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 77 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 111 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 117 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 164 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 169 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 191 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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H A D | cache-v7.S | 85 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 86 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 165 mcr p15, 0, r5, c7, c14, 2 @ clean & invalidate by set/way 200 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 201 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 216 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 217 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 302 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line 307 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 308 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB [all …]
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H A D | tlb-v4wb.S | 38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB 41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB 62 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | tlb-v4wbi.S | 40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 52 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 53 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | proc-sa1100.S | 73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 187 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 204 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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/openbmc/qemu/hw/display/ |
H A D | next-fb.c | 44 int invalidate; member 82 if (s->invalidate) { in nextfb_update() 85 s->invalidate = 0; in nextfb_update() 98 s->invalidate = 1; in nextfb_invalidate() 102 .invalidate = nextfb_invalidate, 114 s->invalidate = 1; in nextfb_realize()
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H A D | bcm2835_fb.c | 52 s->invalidate = true; in fb_invalidate_display() 196 if (s->invalidate) { in fb_update_display() 205 src_width, dest_width, 0, s->invalidate, in fb_update_display() 213 s->invalidate = false; in fb_update_display() 261 s->invalidate = true; in bcm2835_fb_reconfigure() 360 VMSTATE_BOOL(invalidate, BCM2835FBState), 378 .invalidate = fb_invalidate_display, 400 s->invalidate = true; in bcm2835_fb_reset()
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