1*d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 21da177e4SLinus Torvalds/* 31da177e4SLinus Torvalds * linux/arch/arm/mm/tlbv4wbi.S 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Copyright (C) 1997-2002 Russell King 61da177e4SLinus Torvalds * 71da177e4SLinus Torvalds * ARM architecture version 4 and version 5 TLB handling functions. 81da177e4SLinus Torvalds * These assume a split I/D TLBs, with a write buffer. 91da177e4SLinus Torvalds * 101da177e4SLinus Torvalds * Processors: ARM920 ARM922 ARM925 ARM926 XScale 111da177e4SLinus Torvalds */ 121da177e4SLinus Torvalds#include <linux/linkage.h> 131da177e4SLinus Torvalds#include <linux/init.h> 146ebbf2ceSRussell King#include <asm/assembler.h> 15e6ae744dSSam Ravnborg#include <asm/asm-offsets.h> 161da177e4SLinus Torvalds#include <asm/tlbflush.h> 171da177e4SLinus Torvalds#include "proc-macros.S" 181da177e4SLinus Torvalds 191da177e4SLinus Torvalds/* 201da177e4SLinus Torvalds * v4wb_flush_user_tlb_range(start, end, mm) 211da177e4SLinus Torvalds * 221da177e4SLinus Torvalds * Invalidate a range of TLB entries in the specified address space. 231da177e4SLinus Torvalds * 241da177e4SLinus Torvalds * - start - range start address 251da177e4SLinus Torvalds * - end - range end address 261da177e4SLinus Torvalds * - mm - mm_struct describing address space 271da177e4SLinus Torvalds */ 281da177e4SLinus Torvalds .align 5 291da177e4SLinus TorvaldsENTRY(v4wbi_flush_user_tlb_range) 301da177e4SLinus Torvalds vma_vm_mm ip, r2 311da177e4SLinus Torvalds act_mm r3 @ get current->active_mm 321da177e4SLinus Torvalds eors r3, ip, r3 @ == mm ? 336ebbf2ceSRussell King retne lr @ no, we dont do anything 341da177e4SLinus Torvalds mov r3, #0 351da177e4SLinus Torvalds mcr p15, 0, r3, c7, c10, 4 @ drain WB 361da177e4SLinus Torvalds vma_vm_flags r2, r2 371da177e4SLinus Torvalds bic r0, r0, #0x0ff 381da177e4SLinus Torvalds bic r0, r0, #0xf00 391da177e4SLinus Torvalds1: tst r2, #VM_EXEC 401da177e4SLinus Torvalds mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 411da177e4SLinus Torvalds mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 421da177e4SLinus Torvalds add r0, r0, #PAGE_SZ 431da177e4SLinus Torvalds cmp r0, r1 441da177e4SLinus Torvalds blo 1b 456ebbf2ceSRussell King ret lr 461da177e4SLinus Torvalds 471da177e4SLinus TorvaldsENTRY(v4wbi_flush_kern_tlb_range) 481da177e4SLinus Torvalds mov r3, #0 491da177e4SLinus Torvalds mcr p15, 0, r3, c7, c10, 4 @ drain WB 501da177e4SLinus Torvalds bic r0, r0, #0x0ff 511da177e4SLinus Torvalds bic r0, r0, #0xf00 521da177e4SLinus Torvalds1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 531da177e4SLinus Torvalds mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 541da177e4SLinus Torvalds add r0, r0, #PAGE_SZ 551da177e4SLinus Torvalds cmp r0, r1 561da177e4SLinus Torvalds blo 1b 576ebbf2ceSRussell King ret lr 581da177e4SLinus Torvalds 591da177e4SLinus Torvalds __INITDATA 601da177e4SLinus Torvalds 61ca560963SDave Martin /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */ 62ca560963SDave Martin define_tlb_functions v4wbi, v4wbi_tlb_flags 63