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/openbmc/linux/drivers/gpu/drm/i915/
H A DKconfig.profile2 int "Default timeout for requests (ms)"
5 Configures the default timeout after which any user submissions will
13 May be 0 to disable the timeout.
16 int "Timeout for unsignaled foreign fences (ms, jiffy granularity)"
21 make forward progress. This value specifies the timeout used for an
24 May be 0 to disable the timeout, and rely on the foreign fence being
28 int "Runtime autosuspend delay for userspace GGTT mmaps (ms)"
35 that complements the runtime-pm autosuspend and provides a lower
42 int "Interval between heartbeat pulses (ms)"
46 check the health of the GPU and undertake regular house-keeping of
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/openbmc/linux/kernel/time/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0
7 * 1997-01-28 Modified by Finn Arne Gangstad to make timers scale better.
9 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
11 * 1998-12-24 Fixed a xtime SMP race (we need the xtime_lock rw spinlock to
14 * 1999-03-10 Improved NTP compatibility by Ulrich Windl
15 * 2002-05-31 Move sys_sysinfo here and make its locking sane, Robert Love
16 * 2000-10-05 Implemented scalable SMP per-CPU timer handling.
33 #include <linux/posix-timers.h>
55 #include "tick-internal.h"
85 * timeout timers (networking, disk I/O ...) are canceled before expiry. If
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Drohm,bd9576-pmic.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 powering the R-Car series processors.
21 - rohm,bd9576
22 - rohm,bd9573
32 rohm,vout1-en-low:
35 controlled by a GPIO. This is dictated by state of vout1-en pin during
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/openbmc/openbmc/meta-ufispace/meta-ncplite/recipes-phosphor/state/phosphor-state-manager/
H A Dchassis-control9 timeout=30
11 echo "Wait for host shutdown in ${timeout}s"
12 while [ "${timeout}" -gt 0 ]; do
13 host_state=$(gpioget --numeric host0-ready)
14 timeout=$((timeout-1))
15 if [ "${host_state}" -eq 0 ]; then
21 echo "Host still on, but reach timeout"
26 gpioset --hold-period 50ms -t0 power-chassis-control0=1
27 gpioset --hold-period 50ms -t0 power-chassis-control1=1
32 val=$(gpioget --numeric host0-ready)
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/openbmc/linux/Documentation/devicetree/bindings/power/reset/
H A Dgpio-poweroff.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-poweroff.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
15 from inactive to active. After a delay (active-delay-ms) it
17 delay (inactive-delay-ms) it is configured as active again.
19 the system is still running after waiting some time (timeout-ms).
23 const: gpio-poweroff
32 it to an output when the power-off sequence is initiated. If this optional
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/openbmc/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
100 * @timeout: Timeout to wait for clock synchronization in seconds
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/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/
H A Ddevlink_linecard.sh2 # SPDX-License-Identifier: GPL-2.0
5 # LC_SLOT - If not set, all probed line cards are going to be tested,
41 devlink lc show $DEVLINK_DEV lc $lc -j | jq -e -r ".[][][].state"
48 local timeout=$3 # ms
50 busywait "$timeout" until_lc_state_is_not "$state" lc_state_get "$lc"
57 local timeout=$3 # ms
59 busywait "$timeout" until_lc_state_is "$state" lc_state_get "$lc"
75 devlink port -j | jq -e -r ".[][] | select(.lc==$lc) | .port" | wc -l
82 local timeout=$3 # ms
84 busywait "$timeout" until_lc_port_count_is "$port_count" lc_port_count_get "$lc"
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/openbmc/linux/Documentation/devicetree/bindings/input/
H A Diqs626a.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS626A is a 14-channel capacitive touch controller that features
14 additional Hall-effect and inductive sensing capabilities.
19 - $ref: touchscreen/touchscreen.yaml#
31 "#address-cells":
34 "#size-cells":
37 azoteq,suspend-mode:
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/openbmc/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dazoteq,iqs7211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS7210A, IQS7211A and IQS7211E trackpad and touchscreen control-
14 lers employ projected-capacitance sensing and can track two contacts.
21 - azoteq,iqs7210a
22 - azoteq,iqs7211a
23 - azoteq,iqs7211e
28 irq-gpios:
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H A Dcypress,cy8ctma340.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Javier Martinez Canillas <javier@dowhile0.org>
15 - Linus Walleij <linus.walleij@linaro.org>
18 - $ref: touchscreen.yaml#
26 - const: cypress,cy8ctma340
27 - const: cypress,cy8ctst341
28 - const: cypress,cyttsp-spi
31 - const: cypress,cyttsp-i2c
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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dpl011.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: /schemas/arm/primecell.yaml#
14 - $ref: serial.yaml#
22 - arm,pl011
24 - compatible
29 - const: arm,pl011
30 - const: arm,primecell
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/openbmc/u-boot/include/configs/
H A Despt.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the ESPT-GIGA board
39 /* U-Boot setting */
49 /* Timeout for Flash erase operations (in ms) */
51 /* Timeout for Flash write operations (in ms) */
53 /* Timeout for Flash set sector lock bit operations (in ms) */
55 /* Timeout for Flash clear lock bit operations (in ms) */
57 /* Use hardware flash sectors protection instead of U-Boot software protection */
63 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
H A Dsh7763rdp.h1 /* SPDX-License-Identifier: GPL-2.0+ */
39 /* U-Boot setting */
49 /* Timeout for Flash erase operations (in ms) */
51 /* Timeout for Flash write operations (in ms) */
53 /* Timeout for Flash set sector lock bit operations (in ms) */
55 /* Timeout for Flash clear lock bit operations (in ms) */
57 /* Use hardware flash sectors protection instead of U-Boot software protection */
63 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
H A Dr0p7734.h1 /* SPDX-License-Identifier: GPL-2.0+ */
56 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
60 /* Timeout for Flash erase operations (in ms) */
62 /* Timeout for Flash write operations (in ms) */
64 /* Timeout for Flash set sector lock bit operations (in ms) */
66 /* Timeout for Flash clear lock bit operations (in ms) */
71 * of U-Boot software protection
75 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
89 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
H A Dkzm9g.h1 /* SPDX-License-Identifier: GPL-2.0+ */
50 #define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
52 CONFIG_SYS_INIT_RAM_SIZE - \
56 #define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
73 /* Timeout for Flash erase operations (in ms) */
75 /* Timeout for Flash write operations (in ms) */
77 /* Timeout for Flash set sector lock bit operations (in ms) */
79 /* Timeout for Flash clear lock bit operations (in ms) */
H A Dap_sh4a_4a.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Alpha Project AP-SH4A-4A board
58 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
62 /* Timeout for Flash erase operations (in ms) */
64 /* Timeout for Flash write operations (in ms) */
66 /* Timeout for Flash set sector lock bit operations (in ms) */
68 /* Timeout for Flash clear lock bit operations (in ms) */
73 * of U-Boot software protection
77 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
91 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
H A DMigoR.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Renesas Solutions Migo-R board
42 /* maybe more, but if so u-boot doesn't know about it... */
47 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
64 /* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
68 /* Timeout for Flash erase operations (in ms) */
70 /* Timeout for Flash write operations (in ms) */
72 /* Timeout for Flash set sector lock bit operations (in ms) */
74 /* Timeout for Flash clear lock bit operations (in ms) */
77 /* Use hardware flash sectors protection instead of U-Boot software protection */
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H A Dms7722se.h1 /* SPDX-License-Identifier: GPL-2.0+ */
39 #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about…
43 #define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
58 /* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
64 #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */
65 #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */
66 #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (…
67 #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in
75 #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector …
H A Dap325rxa.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Configuation settings for the Renesas Solutions AP-325RXA board
46 /* maybe more, but if so u-boot doesn't know about it... */
51 /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
82 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
86 /* Timeout for Flash erase operations (in ms) */
88 /* Timeout for Flash write operations (in ms) */
90 /* Timeout for Flash set sector lock bit operations (in ms) */
92 /* Timeout for Flash clear lock bit operations (in ms) */
97 * of U-Boot software protection
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H A Decovec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
15 *-----------------------------------------
16 * 0x0000_0000 U-Boot 16bit
93 /* if you use all NOR Flash , you change dip-switch. Please see Manual. */
97 /* Timeout for Flash erase operations (in ms) */
99 /* Timeout for Flash write operations (in ms) */
101 /* Timeout for Flash set sector lock bit operations (in ms) */
103 /* Timeout for Flash clear lock bit operations (in ms) */
108 * of U-Boot software protection
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/openbmc/linux/Documentation/devicetree/bindings/peci/
H A Dpeci-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/peci/peci-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Iwona Winiarska <iwona.winiarska@intel.com>
19 pattern: "^peci-controller(@.*)?$"
21 cmd-timeout-ms:
23 Command timeout in units of ms.
28 - |
29 peci-controller@1e78b000 {
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/openbmc/u-boot/arch/arm/mach-at91/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
25 unsigned long const timeout = 1000; /* 1000ms */ in at91_phy_reset() local
28 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; in at91_phy_reset()
31 * Need to reset PHY -> 500ms reset in at91_phy_reset()
32 * Reset PHY by pulling the NRST line for 500ms to low. To do so in at91_phy_reset()
37 AT91_RSTC_MR_URSTEN, &rstc->mr); in at91_phy_reset()
39 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); in at91_phy_reset()
42 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { in at91_phy_reset()
47 /* timeout for not getting stuck in an endless loop */ in at91_phy_reset()
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/openbmc/linux/net/netfilter/ipvs/
H A Dip_vs_sync.c1 // SPDX-License-Identifier: GPL-2.0
6 * high-performance and highly available server based on a
13 * time-outs, and firewall marks.
15 * Ver. 0 can be turned on by sysctl -w net.ipv4.vs.sync_version=0
32 * Persistence support, fwmark and time-out.
61 #define IP_VS_SYNC_GROUP 0xe0000051 /* multicast addr - 224.0.0.81 */
100 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
102 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
104 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
106 +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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/openbmc/sdbusplus/test/event/
H A Devent.cpp17 static constexpr auto timeout = 250ms; in TEST_F() local
20 ev.run_one(timeout); in TEST_F()
23 EXPECT_TRUE(stop - start > timeout); in TEST_F()
24 EXPECT_TRUE(stop - start < timeout * 3); in TEST_F()
29 static constexpr auto timeout = 10s; in TEST_F() local
34 ev.run_one(timeout); in TEST_F()
37 EXPECT_TRUE(stop - start < timeout); in TEST_F()
62 static constexpr auto timeout = 50ms; in TEST_F() local
75 auto c = ev.add_oneshot_timer(handler::_, &ran, timeout); in TEST_F()
80 EXPECT_TRUE(stop - start > timeout); in TEST_F()
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dziirave-wdt.txt4 - compatible: must be "zii,rave-wdt"
5 - reg: i2c slave address of device, usually 0x38
8 - timeout-sec: Watchdog timeout value in seconds.
9 - reset-duration-ms: Duration of the pulse generated when the watchdog times
15 compatible = "zii,rave-wdt";
17 timeout-sec = <30>;
18 reset-duration-ms = <30>;

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