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/openbmc/linux/drivers/media/platform/via/
H A Dvia-camera.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define VCR_IC_ACTBUF 0x0018 /* Active video buffer */
13 #define VCR_IC_INTEN 0x0100 /* End of active video int. enable */
14 #define VCR_IC_VBIINT 0x0200 /* End of VBI int enable */
15 #define VCR_IC_VBIBUF 0x0400 /* Current VBI buffer */
18 #define VCR_TSC_ENABLE 0x000001 /* Transport stream input enable */
20 #define VCR_TSC_METHOD 0x00000c /* DMA method (non-functional) */
22 #define VCR_TSC_CBMODE 0x080000 /* Change buffer by byte count */
28 #define VCR_CI_ENABLE 0x00000001 /* Capture enable */
31 #define VCR_CI_VIPEN 0x00000008 /* VIP enable */
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/openbmc/linux/include/linux/usb/
H A Dr8a66597.h1 // SPDX-License-Identifier: GPL-2.0
124 #define XTAL 0xC000 /* b15-14: Crystal selection */
128 #define XCKE 0x2000 /* b13: External clock enable */
130 #define SCKE 0x0400 /* b10: USB clock enable */
133 #define HSE 0x0080 /* b7: Hi-speed enable */
135 #define DRPD 0x0020 /* b5: D+/- pull down control */
137 #define USBE 0x0001 /* b0: USB module operation enable */
140 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
141 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
143 #define IDMON 0x0004 /* b3: ID-pin monitor */
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/openbmc/u-boot/include/
H A Dmisc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
10 * misc_read() - Read the device to buffer, optional.
13 * @buf: pointer to data buffer
16 * Return: number of bytes read if OK (may be 0 if EOF), -ve on error
21 * misc_write() - Write buffer to the device, optional.
24 * @buf: pointer to data buffer
27 * Return: number of bytes written if OK (may be < @size), -ve on error
32 * misc_ioctl() - Assert command to the device, optional.
35 * @buf: pointer to buffer related to the request
37 * Return: 0 if OK, -ve on error
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/openbmc/linux/drivers/media/platform/st/sti/delta/
H A Ddelta-mjpeg-fw.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 * @display_luma_p: address of the luma buffer
17 * @display_chroma_p: address of the chroma buffer
31 * @display_luma_p: address of the luma buffer
32 * @display_chroma_p: address of the chroma buffer
33 * @display_decimated_luma_p: address of the decimated luma buffer
34 * @display_decimated_chroma_p: address of the decimated chroma buffer
49 /* enable decimated (for display) reconstruction */
51 /* enable main (for display) reconstruction */
53 /* enable both main & decimated (for display) reconstruction */
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/openbmc/linux/drivers/media/rc/
H A Dene_ir.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS 0 /* hardware status - unused */
18 #define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
24 #define ENE_FW1_ENABLE 0x01 /* enable fw processing */
26 #define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
27 #define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
30 #define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
31 #define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
32 #define ENE_FW1_IRQ 0x80 /* enable interrupt */
36 #define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
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/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_mitigations.c1 // SPDX-License-Identifier: MIT
41 return -ENOMEM; in mitigations_set()
44 bool enable = true; in mitigations_set() local
62 enable = !enable; in mitigations_set()
67 enable = !enable; in mitigations_set()
76 if (enable) in mitigations_set()
86 err = -EINVAL; in mitigations_set()
98 static int mitigations_get(char *buffer, const struct kernel_param *kp) in mitigations_get() argument
102 bool enable; in mitigations_get() local
105 return scnprintf(buffer, PAGE_SIZE, "%s\n", "off"); in mitigations_get()
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/openbmc/linux/drivers/usb/renesas_usbhs/
H A Dcommon.h1 /* SPDX-License-Identifier: GPL-1.0+ */
100 #define D2FIFOSEL 0x00F0 /* for R-Car Gen2 */
101 #define D2FIFOCTR 0x00F2 /* for R-Car Gen2 */
102 #define D3FIFOSEL 0x00F4 /* for R-Car Gen2 */
103 #define D3FIFOCTR 0x00F6 /* for R-Car Gen2 */
107 #define SCKE (1 << 10) /* USB Module Clock Enable */
108 #define CNEN (1 << 8) /* Single-ended receiver operation Enable */
109 #define HSE (1 << 7) /* High-Speed Operation Enable */
111 #define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
113 #define USBE (1 << 0) /* USB Module Operation Enable */
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/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
119 /* set interrupt mapping enable rx */
123 /* set interrupt mapping enable tx */
157 void hw_atl_itr_rsc_en_set(struct aq_hw_s *aq_hw, u32 enable);
167 /* set rx dca enable */
173 /* set rx descriptor data buffer size */
178 /* set rx descriptor dca enable */
182 /* set rx descriptor enable */
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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvega10_ih.c41 * vega10_ih_init_register_offset - Initialize register offset for ih rings
51 if (adev->irq.ih.ring_size) { in vega10_ih_init_register_offset()
52 ih_regs = &adev->irq.ih.ih_regs; in vega10_ih_init_register_offset()
53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega10_ih_init_register_offset()
55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset()
56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega10_ih_init_register_offset()
59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega10_ih_init_register_offset()
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H A Dih_v6_1.c40 * ih_v6_1_init_register_offset - Initialize register offset for ih rings
52 if (adev->irq.ih.ring_size) { in ih_v6_1_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_1_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_1_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_1_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_1_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_1_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_1_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_1_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); in ih_v6_1_init_register_offset()
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H A Dnavi10_ih.c43 * navi10_ih_init_register_offset - Initialize register offset for ih rings
53 if (adev->irq.ih.ring_size) { in navi10_ih_init_register_offset()
54 ih_regs = &adev->irq.ih.ih_regs; in navi10_ih_init_register_offset()
55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in navi10_ih_init_register_offset()
57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset()
58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
60 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in navi10_ih_init_register_offset()
61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in navi10_ih_init_register_offset()
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H A Dvega20_ih.c49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
59 if (adev->irq.ih.ring_size) { in vega20_ih_init_register_offset()
60 ih_regs = &adev->irq.ih.ih_regs; in vega20_ih_init_register_offset()
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega20_ih_init_register_offset()
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset()
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega20_ih_init_register_offset()
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega20_ih_init_register_offset()
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H A Dih_v6_0.c40 * ih_v6_0_init_register_offset - Initialize register offset for ih rings
52 if (adev->irq.ih.ring_size) { in ih_v6_0_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE); in ih_v6_0_init_register_offset()
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI); in ih_v6_0_init_register_offset()
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL); in ih_v6_0_init_register_offset()
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR); in ih_v6_0_init_register_offset()
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR); in ih_v6_0_init_register_offset()
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR); in ih_v6_0_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO); in ih_v6_0_init_register_offset()
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H A Dtonga_ih.c38 * Starting with r6xx, interrupts are handled via a ring buffer.
45 * writes vectors to the ring buffer, it increments the
54 * tonga_ih_enable_interrupts - Enable the interrupt ring buffer
58 * Enable the interrupt ring buffer (VI).
67 adev->irq.ih.enabled = true; in tonga_ih_enable_interrupts()
71 * tonga_ih_disable_interrupts - Disable the interrupt ring buffer
75 * Disable the interrupt ring buffer (VI).
87 adev->irq.ih.enabled = false; in tonga_ih_disable_interrupts()
88 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
92 * tonga_ih_irq_init - init and enable the interrupt ring
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/openbmc/linux/drivers/net/wan/
H A Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
32 #define IER0 0x14 /* Interrupt Enable 0 */
33 #define IER1 0x15 /* Interrupt Enable 1 */
34 #define IER2 0x16 /* Interrupt Enable 2 */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
48 #define TRBL 0x00 /* TX/RX buffer L */
49 #define TRBH 0x01 /* TX/RX buffer H */
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/openbmc/linux/drivers/pci/
H A Dvc.c1 // SPDX-License-Identifier: GPL-2.0
19 * pci_vc_save_restore_dwords - Save or restore a series of dwords
22 * @buf: buffer to save to or restore from
40 * pci_vc_load_arb_table - load and wait for VC arbitration table
63 * pci_vc_load_port_arb_table - Load and wait for VC port arbitration table
66 * @res: VC resource number, ie. VCn (0-7)
91 * pci_vc_enable - Enable virtual channel
94 * @res: VC res number, ie. VCn (0-7)
96 * A VC is enabled by setting the enable bit in matching resource control
98 * end of the link. To keep this simple we enable from the downstream device.
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/openbmc/qemu/include/hw/net/
H A Dnpcm_gmac.h40 /* RDES2 and RDES3 are buffer addresses */
88 /* Receive Buffer 2 Size */
92 /* Receive Buffer 1 Size */
104 /* TDES2 and TDES3 are buffer addresses */
152 /* Transmit Buffer 2 Size */
154 /* Transmit Buffer 1 Size */
170 #define TYPE_NPCM_GMAC "npcm-gmac"
220 /* Receive Buffer Unavailable */
230 /* Transmit Buffer Unavailable */
257 /* Early Receive Interrupt Enable */
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/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_dcb_82598.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10 #define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
15 #define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
18 #define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
20 #define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet buffers enable */
21 #define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores (RSS) enable */
33 #define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
35 #define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
37 #define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */
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/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
25 /* set new RPF enable */
26 void hw_atl2_rpf_new_enable_set(struct aq_hw_s *aq_hw, u32 enable);
41 /* set tx random TC-queue mapping enable bit */
45 /* set tx buffer clock gate enable */
69 /* set enable action resolver section */
72 /* get data from firmware shared input buffer */
76 /* set data into firmware shared input buffer */
80 /* get data from firmware shared output buffer */
84 /* set host finished write shared buffer indication */
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/openbmc/u-boot/drivers/fastboot/
H A DKconfig9 bool "Enable USB fastboot gadget"
20 bool "Enable fastboot protocol over UDP"
27 hex "Define FASTBOOT buffer address"
40 The fastboot protocol requires a large memory buffer for
45 hex "Define FASTBOOT buffer size"
52 The fastboot protocol requires a large memory buffer for
53 downloads. This buffer should be as large as possible for a
66 bool "Enable FASTBOOT FLASH command"
72 the downloaded image to a non-volatile storage device. Define
73 this to enable the "fastboot flash" command.
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/openbmc/linux/drivers/net/wireless/marvell/mwifiex/
H A D11h.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2011-2020 NXP
14 priv->state_11h.is_11h_enabled = true; in mwifiex_init_11h_params()
15 priv->state_11h.is_11h_active = false; in mwifiex_init_11h_params()
20 return priv->state_11h.is_11h_active; in mwifiex_is_11h_active()
22 /* This function appends 11h info to a buffer while joining an
26 mwifiex_11h_process_infra_join(struct mwifiex_private *priv, u8 **buffer, in mwifiex_11h_process_infra_join() argument
36 if (!buffer || !(*buffer)) in mwifiex_11h_process_infra_join()
39 radio_type = mwifiex_band_to_radio_type((u8) bss_desc->bss_band); in mwifiex_11h_process_infra_join()
40 sband = priv->wdev.wiphy->bands[radio_type]; in mwifiex_11h_process_infra_join()
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/openbmc/linux/sound/soc/intel/skylake/
H A Dskl-sst-cldma.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #define SKL_CL_DMA_SD_INT_COMPLETE 0x04 /* Buffer completion interrupt */
60 /* Interrupt On Completion Enable */
66 /* FIFO Error Interrupt Enable */
72 /* Descriptor Error Interrupt Enable */
110 /* Buffer Completion Interrupt Status */
134 /* CL: Stream Descriptor x Buffer Descriptor List Pointer Lower Base Address */
142 /* Buffer Descriptor List Lower Base Address */
148 /* Buffer Descriptor List Upper Base Address */
155 * Code Loader - Software Position Based FIFO
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/openbmc/u-boot/common/
H A DKconfig6 Enable recording of boot time while booting. To use it, insert
25 Enable recording of boot time in SPL. To make this visible to U-Boot
26 proper, enable BOOTSTAGE_STASH as well. This will stash the timing
27 information when SPL finishes and load it when U-Boot proper starts
34 Enable recording of boot time in SPL. To make this visible to U-Boot
35 proper, enable BOOTSTAGE_STASH as well. This will stash the timing
36 information when TPL finishes and load it when U-Boot proper starts
43 Enable output of a boot time report just before the OS is booted.
44 This shows how long it took U-Boot to go through each stage of the
129 Enabling this will make a U-Boot binary that is capable of being
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/openbmc/linux/drivers/media/platform/ti/omap3isp/
H A Dispstat.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Statistics core
15 #include <linux/dma-mapping.h>
22 #define ISP_STAT_USES_DMAENGINE(stat) ((stat)->dma_ch != NULL)
36 * the next buffer to start to be written in the same point where the overflow
38 * go back to a valid state is having a valid buffer processing. Of course it
39 * requires at least a doubled buffer size to avoid an access to invalid memory
43 * configuration was created. It produces the minimum buffer size for each H3A
45 * will be enabled every time a SBL overflow occur. As the output buffer size
56 #define IS_H3A_AF(stat) ((stat) == &(stat)->isp->isp_af)
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/openbmc/linux/arch/mips/include/asm/dec/
H A Dioasic_addrs.h53 #define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */
67 #define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */
69 #define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */
72 #define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */
73 #define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */
74 #define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */
75 #define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */
100 #define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */
103 #define IO_REG_FCTR 0x1e0 /* Free-Running Counter */
115 #define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */
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