Lines Matching +full:buffer +full:- +full:enable
41 * vega10_ih_init_register_offset - Initialize register offset for ih rings
51 if (adev->irq.ih.ring_size) { in vega10_ih_init_register_offset()
52 ih_regs = &adev->irq.ih.ih_regs; in vega10_ih_init_register_offset()
53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega10_ih_init_register_offset()
55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset()
56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
58 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR); in vega10_ih_init_register_offset()
59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO); in vega10_ih_init_register_offset()
60 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI); in vega10_ih_init_register_offset()
61 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL; in vega10_ih_init_register_offset()
64 if (adev->irq.ih1.ring_size) { in vega10_ih_init_register_offset()
65 ih_regs = &adev->irq.ih1.ih_regs; in vega10_ih_init_register_offset()
66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega10_ih_init_register_offset()
67 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1); in vega10_ih_init_register_offset()
68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_init_register_offset()
69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in vega10_ih_init_register_offset()
70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in vega10_ih_init_register_offset()
71 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1); in vega10_ih_init_register_offset()
72 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1; in vega10_ih_init_register_offset()
75 if (adev->irq.ih2.ring_size) { in vega10_ih_init_register_offset()
76 ih_regs = &adev->irq.ih2.ih_regs; in vega10_ih_init_register_offset()
77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in vega10_ih_init_register_offset()
78 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2); in vega10_ih_init_register_offset()
79 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2); in vega10_ih_init_register_offset()
80 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2); in vega10_ih_init_register_offset()
81 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2); in vega10_ih_init_register_offset()
82 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2); in vega10_ih_init_register_offset()
83 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2; in vega10_ih_init_register_offset()
88 * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
92 * @enable: true - enable the interrupts, false - disable the interrupts
94 * Toggle the interrupt ring buffer (VEGA10)
98 bool enable) in vega10_ih_toggle_ring_interrupts() argument
103 ih_regs = &ih->ih_regs; in vega10_ih_toggle_ring_interrupts()
105 tmp = RREG32(ih_regs->ih_rb_cntl); in vega10_ih_toggle_ring_interrupts()
106 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0)); in vega10_ih_toggle_ring_interrupts()
109 if (ih == &adev->irq.ih) in vega10_ih_toggle_ring_interrupts()
110 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0)); in vega10_ih_toggle_ring_interrupts()
112 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { in vega10_ih_toggle_ring_interrupts()
113 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); in vega10_ih_toggle_ring_interrupts()
114 return -ETIMEDOUT; in vega10_ih_toggle_ring_interrupts()
117 WREG32(ih_regs->ih_rb_cntl, tmp); in vega10_ih_toggle_ring_interrupts()
120 if (enable) { in vega10_ih_toggle_ring_interrupts()
121 ih->enabled = true; in vega10_ih_toggle_ring_interrupts()
124 WREG32(ih_regs->ih_rb_rptr, 0); in vega10_ih_toggle_ring_interrupts()
125 WREG32(ih_regs->ih_rb_wptr, 0); in vega10_ih_toggle_ring_interrupts()
126 ih->enabled = false; in vega10_ih_toggle_ring_interrupts()
127 ih->rptr = 0; in vega10_ih_toggle_ring_interrupts()
134 * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
137 * @enable: enable or disable interrupt ring buffers
141 static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable) in vega10_ih_toggle_interrupts() argument
143 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in vega10_ih_toggle_interrupts()
148 if (ih[i]->ring_size) { in vega10_ih_toggle_interrupts()
149 r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable); in vega10_ih_toggle_interrupts()
160 int rb_bufsz = order_base_2(ih->ring_size / 4); in vega10_ih_rb_cntl()
163 MC_SPACE, ih->use_bus_addr ? 1 : 4); in vega10_ih_rb_cntl()
169 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register in vega10_ih_rb_cntl()
185 if (ih->use_doorbell) { in vega10_ih_doorbell_rptr()
188 ih->doorbell_index); in vega10_ih_doorbell_rptr()
191 ENABLE, 1); in vega10_ih_doorbell_rptr()
195 ENABLE, 0); in vega10_ih_doorbell_rptr()
201 * vega10_ih_enable_ring - enable an ih ring buffer
206 * Enable an ih ring buffer (VEGA10)
214 ih_regs = &ih->ih_regs; in vega10_ih_enable_ring()
216 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ in vega10_ih_enable_ring()
217 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in vega10_ih_enable_ring()
218 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); in vega10_ih_enable_ring()
220 tmp = RREG32(ih_regs->ih_rb_cntl); in vega10_ih_enable_ring()
222 if (ih == &adev->irq.ih) in vega10_ih_enable_ring()
223 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled); in vega10_ih_enable_ring()
224 if (ih == &adev->irq.ih1) in vega10_ih_enable_ring()
227 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) { in vega10_ih_enable_ring()
228 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n"); in vega10_ih_enable_ring()
229 return -ETIMEDOUT; in vega10_ih_enable_ring()
232 WREG32(ih_regs->ih_rb_cntl, tmp); in vega10_ih_enable_ring()
235 if (ih == &adev->irq.ih) { in vega10_ih_enable_ring()
237 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in vega10_ih_enable_ring()
238 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in vega10_ih_enable_ring()
242 WREG32(ih_regs->ih_rb_wptr, 0); in vega10_ih_enable_ring()
243 WREG32(ih_regs->ih_rb_rptr, 0); in vega10_ih_enable_ring()
245 WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih)); in vega10_ih_enable_ring()
251 * vega10_ih_irq_init - init and enable the interrupt ring
255 * Allocate a ring buffer for the interrupt controller,
256 * enable the RLC, disable interrupts, enable the IH
257 * ring buffer and enable it (VI).
263 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2}; in vega10_ih_irq_init()
273 adev->nbio.funcs->ih_control(adev); in vega10_ih_irq_init()
275 if (adev->asic_type == CHIP_RENOIR) { in vega10_ih_irq_init()
277 if (adev->irq.ih.use_bus_addr) { in vega10_ih_irq_init()
285 if (ih[i]->ring_size) { in vega10_ih_irq_init()
293 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in vega10_ih_irq_init()
294 adev->irq.ih.doorbell_index); in vega10_ih_irq_init()
296 pci_set_master(adev->pdev); in vega10_ih_irq_init()
298 /* enable interrupts */ in vega10_ih_irq_init()
303 if (adev->irq.ih_soft.ring_size) in vega10_ih_irq_init()
304 adev->irq.ih_soft.enabled = true; in vega10_ih_irq_init()
310 * vega10_ih_irq_disable - disable interrupts
325 * vega10_ih_get_wptr - get the IH ring buffer wptr
328 * @ih: IH ring buffer to fetch wptr
330 * Get the IH ring buffer wptr from either the register
331 * or the writeback memory buffer (VEGA10). Also check for
332 * ring buffer overflow and deal with it.
341 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) { in vega10_ih_get_wptr()
343 * to register-based code with overflow checking below. in vega10_ih_get_wptr()
347 wptr = le32_to_cpu(*ih->wptr_cpu); in vega10_ih_get_wptr()
353 ih_regs = &ih->ih_regs; in vega10_ih_get_wptr()
356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
362 /* When a ring buffer overflow happen start parsing interrupt in vega10_ih_get_wptr()
366 tmp = (wptr + 32) & ih->ptr_mask; in vega10_ih_get_wptr()
367 dev_warn(adev->dev, "IH ring buffer overflow " in vega10_ih_get_wptr()
369 wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
370 ih->rptr = tmp; in vega10_ih_get_wptr()
372 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl); in vega10_ih_get_wptr()
374 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega10_ih_get_wptr()
380 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp); in vega10_ih_get_wptr()
383 return (wptr & ih->ptr_mask); in vega10_ih_get_wptr()
387 * vega10_ih_irq_rearm - rearm IRQ if lost
400 ih_regs = &ih->ih_regs; in vega10_ih_irq_rearm()
401 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */ in vega10_ih_irq_rearm()
403 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr); in vega10_ih_irq_rearm()
404 if ((v < ih->ring_size) && (v != ih->rptr)) in vega10_ih_irq_rearm()
405 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_irq_rearm()
412 * vega10_ih_set_rptr - set the IH ring buffer rptr
415 * @ih: IH ring buffer to set rptr
417 * Set the IH ring buffer rptr.
424 if (ih == &adev->irq.ih_soft) in vega10_ih_set_rptr()
427 if (ih->use_doorbell) { in vega10_ih_set_rptr()
429 *ih->rptr_cpu = ih->rptr; in vega10_ih_set_rptr()
430 WDOORBELL32(ih->doorbell_index, ih->rptr); in vega10_ih_set_rptr()
435 ih_regs = &ih->ih_regs; in vega10_ih_set_rptr()
436 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in vega10_ih_set_rptr()
441 * vega10_ih_self_irq - dispatch work for ring 1 and 2
453 switch (entry->ring_id) { in vega10_ih_self_irq()
455 schedule_work(&adev->irq.ih1_work); in vega10_ih_self_irq()
458 schedule_work(&adev->irq.ih2_work); in vega10_ih_self_irq()
471 adev->irq.self_irq.num_types = 0; in vega10_ih_set_self_irq_funcs()
472 adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; in vega10_ih_set_self_irq_funcs()
490 &adev->irq.self_irq); in vega10_ih_sw_init()
494 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, true); in vega10_ih_sw_init()
498 adev->irq.ih.use_doorbell = true; in vega10_ih_sw_init()
499 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; in vega10_ih_sw_init()
501 if (!(adev->flags & AMD_IS_APU)) { in vega10_ih_sw_init()
502 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true); in vega10_ih_sw_init()
506 adev->irq.ih1.use_doorbell = true; in vega10_ih_sw_init()
507 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in vega10_ih_sw_init()
509 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true); in vega10_ih_sw_init()
513 adev->irq.ih2.use_doorbell = true; in vega10_ih_sw_init()
514 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1; in vega10_ih_sw_init()
519 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true); in vega10_ih_sw_init()
576 return -ETIMEDOUT; in vega10_ih_wait_for_idle()
587 bool enable) in vega10_ih_update_clockgating_state() argument
591 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) { in vega10_ih_update_clockgating_state()
593 field_val = enable ? 0 : 1; in vega10_ih_update_clockgating_state()
597 if (adev->asic_type == CHIP_RENOIR) in vega10_ih_update_clockgating_state()
659 adev->irq.ih_funcs = &vega10_ih_funcs; in vega10_ih_set_interrupt_funcs()