1282aae55SKen Wang /*
2282aae55SKen Wang * Copyright 2016 Advanced Micro Devices, Inc.
3282aae55SKen Wang *
4282aae55SKen Wang * Permission is hereby granted, free of charge, to any person obtaining a
5282aae55SKen Wang * copy of this software and associated documentation files (the "Software"),
6282aae55SKen Wang * to deal in the Software without restriction, including without limitation
7282aae55SKen Wang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8282aae55SKen Wang * and/or sell copies of the Software, and to permit persons to whom the
9282aae55SKen Wang * Software is furnished to do so, subject to the following conditions:
10282aae55SKen Wang *
11282aae55SKen Wang * The above copyright notice and this permission notice shall be included in
12282aae55SKen Wang * all copies or substantial portions of the Software.
13282aae55SKen Wang *
14282aae55SKen Wang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15282aae55SKen Wang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16282aae55SKen Wang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17282aae55SKen Wang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18282aae55SKen Wang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19282aae55SKen Wang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20282aae55SKen Wang * OTHER DEALINGS IN THE SOFTWARE.
21282aae55SKen Wang *
22282aae55SKen Wang */
2347b757fbSSam Ravnborg
2447b757fbSSam Ravnborg #include <linux/pci.h>
2547b757fbSSam Ravnborg
26282aae55SKen Wang #include "amdgpu.h"
27282aae55SKen Wang #include "amdgpu_ih.h"
28282aae55SKen Wang #include "soc15.h"
29282aae55SKen Wang
308af7454eSFeifei Xu #include "oss/osssys_4_0_offset.h"
318af7454eSFeifei Xu #include "oss/osssys_4_0_sh_mask.h"
32282aae55SKen Wang
33282aae55SKen Wang #include "soc15_common.h"
34282aae55SKen Wang #include "vega10_ih.h"
35282aae55SKen Wang
3674dcfe74STrigger Huang #define MAX_REARM_RETRY 10
37282aae55SKen Wang
38282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev);
39282aae55SKen Wang
40282aae55SKen Wang /**
411ebb4841SHawking Zhang * vega10_ih_init_register_offset - Initialize register offset for ih rings
421ebb4841SHawking Zhang *
431ebb4841SHawking Zhang * @adev: amdgpu_device pointer
441ebb4841SHawking Zhang *
451ebb4841SHawking Zhang * Initialize register offset ih rings (VEGA10).
461ebb4841SHawking Zhang */
vega10_ih_init_register_offset(struct amdgpu_device * adev)471ebb4841SHawking Zhang static void vega10_ih_init_register_offset(struct amdgpu_device *adev)
481ebb4841SHawking Zhang {
491ebb4841SHawking Zhang struct amdgpu_ih_regs *ih_regs;
501ebb4841SHawking Zhang
511ebb4841SHawking Zhang if (adev->irq.ih.ring_size) {
521ebb4841SHawking Zhang ih_regs = &adev->irq.ih.ih_regs;
531ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
541ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
551ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
561ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
571ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
581ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
591ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
601ebb4841SHawking Zhang ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
611ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
621ebb4841SHawking Zhang }
631ebb4841SHawking Zhang
641ebb4841SHawking Zhang if (adev->irq.ih1.ring_size) {
651ebb4841SHawking Zhang ih_regs = &adev->irq.ih1.ih_regs;
661ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
671ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
681ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
691ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
701ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
711ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
721ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
731ebb4841SHawking Zhang }
741ebb4841SHawking Zhang
751ebb4841SHawking Zhang if (adev->irq.ih2.ring_size) {
761ebb4841SHawking Zhang ih_regs = &adev->irq.ih2.ih_regs;
771ebb4841SHawking Zhang ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
781ebb4841SHawking Zhang ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
791ebb4841SHawking Zhang ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
801ebb4841SHawking Zhang ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
811ebb4841SHawking Zhang ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
821ebb4841SHawking Zhang ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
831ebb4841SHawking Zhang ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
841ebb4841SHawking Zhang }
851ebb4841SHawking Zhang }
861ebb4841SHawking Zhang
871ebb4841SHawking Zhang /**
88c7375032SHawking Zhang * vega10_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
89c7375032SHawking Zhang *
90c7375032SHawking Zhang * @adev: amdgpu_device pointer
91c7375032SHawking Zhang * @ih: amdgpu_ih_ring pointet
92c7375032SHawking Zhang * @enable: true - enable the interrupts, false - disable the interrupts
93c7375032SHawking Zhang *
94c7375032SHawking Zhang * Toggle the interrupt ring buffer (VEGA10)
95c7375032SHawking Zhang */
vega10_ih_toggle_ring_interrupts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,bool enable)96c7375032SHawking Zhang static int vega10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
97c7375032SHawking Zhang struct amdgpu_ih_ring *ih,
98c7375032SHawking Zhang bool enable)
99c7375032SHawking Zhang {
100c7375032SHawking Zhang struct amdgpu_ih_regs *ih_regs;
101c7375032SHawking Zhang uint32_t tmp;
102c7375032SHawking Zhang
103c7375032SHawking Zhang ih_regs = &ih->ih_regs;
104c7375032SHawking Zhang
105c7375032SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl);
106c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
1079dd9cc2fSAlex Sierra tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
108c7375032SHawking Zhang /* enable_intr field is only valid in ring0 */
109c7375032SHawking Zhang if (ih == &adev->irq.ih)
110c7375032SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
111c7375032SHawking Zhang if (amdgpu_sriov_vf(adev)) {
112c7375032SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
113c7375032SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
114c7375032SHawking Zhang return -ETIMEDOUT;
115c7375032SHawking Zhang }
116c7375032SHawking Zhang } else {
117c7375032SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp);
118c7375032SHawking Zhang }
119c7375032SHawking Zhang
120c7375032SHawking Zhang if (enable) {
121c7375032SHawking Zhang ih->enabled = true;
122c7375032SHawking Zhang } else {
123c7375032SHawking Zhang /* set rptr, wptr to 0 */
124c7375032SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0);
125c7375032SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0);
126c7375032SHawking Zhang ih->enabled = false;
127c7375032SHawking Zhang ih->rptr = 0;
128c7375032SHawking Zhang }
129c7375032SHawking Zhang
130c7375032SHawking Zhang return 0;
131c7375032SHawking Zhang }
132c7375032SHawking Zhang
133fd95e1b1SHawking Zhang /**
134fd95e1b1SHawking Zhang * vega10_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
135fd95e1b1SHawking Zhang *
136fd95e1b1SHawking Zhang * @adev: amdgpu_device pointer
137fd95e1b1SHawking Zhang * @enable: enable or disable interrupt ring buffers
138fd95e1b1SHawking Zhang *
139fd95e1b1SHawking Zhang * Toggle all the available interrupt ring buffers (VEGA10).
140fd95e1b1SHawking Zhang */
vega10_ih_toggle_interrupts(struct amdgpu_device * adev,bool enable)141fd95e1b1SHawking Zhang static int vega10_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
142fd95e1b1SHawking Zhang {
143fd95e1b1SHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
144fd95e1b1SHawking Zhang int i;
145fd95e1b1SHawking Zhang int r;
146fd95e1b1SHawking Zhang
147fd95e1b1SHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) {
148fd95e1b1SHawking Zhang if (ih[i]->ring_size) {
149fd95e1b1SHawking Zhang r = vega10_ih_toggle_ring_interrupts(adev, ih[i], enable);
150fd95e1b1SHawking Zhang if (r)
151fd95e1b1SHawking Zhang return r;
152fd95e1b1SHawking Zhang }
153fd95e1b1SHawking Zhang }
154fd95e1b1SHawking Zhang
155fd95e1b1SHawking Zhang return 0;
156fd95e1b1SHawking Zhang }
157fd95e1b1SHawking Zhang
vega10_ih_rb_cntl(struct amdgpu_ih_ring * ih,uint32_t ih_rb_cntl)158ad710812SChristian König static uint32_t vega10_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
159ad710812SChristian König {
160ad710812SChristian König int rb_bufsz = order_base_2(ih->ring_size / 4);
161ad710812SChristian König
162ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
163ad710812SChristian König MC_SPACE, ih->use_bus_addr ? 1 : 4);
164ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
165ad710812SChristian König WPTR_OVERFLOW_CLEAR, 1);
166ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
167ad710812SChristian König WPTR_OVERFLOW_ENABLE, 1);
168ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
169ad710812SChristian König /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
170ad710812SChristian König * value is written to memory
171ad710812SChristian König */
172ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
173ad710812SChristian König WPTR_WRITEBACK_ENABLE, 1);
174ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
175ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
176ad710812SChristian König ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
177ad710812SChristian König
178ad710812SChristian König return ih_rb_cntl;
179282aae55SKen Wang }
180282aae55SKen Wang
vega10_ih_doorbell_rptr(struct amdgpu_ih_ring * ih)1811ae64cecSChristian König static uint32_t vega10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
1821ae64cecSChristian König {
1831ae64cecSChristian König u32 ih_doorbell_rtpr = 0;
1841ae64cecSChristian König
1851ae64cecSChristian König if (ih->use_doorbell) {
1861ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
1871ae64cecSChristian König IH_DOORBELL_RPTR, OFFSET,
1881ae64cecSChristian König ih->doorbell_index);
1891ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
1901ae64cecSChristian König IH_DOORBELL_RPTR,
1911ae64cecSChristian König ENABLE, 1);
1921ae64cecSChristian König } else {
1931ae64cecSChristian König ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
1941ae64cecSChristian König IH_DOORBELL_RPTR,
1951ae64cecSChristian König ENABLE, 0);
1961ae64cecSChristian König }
1971ae64cecSChristian König return ih_doorbell_rtpr;
1981ae64cecSChristian König }
1991ae64cecSChristian König
200282aae55SKen Wang /**
201ffa02126SHawking Zhang * vega10_ih_enable_ring - enable an ih ring buffer
202ffa02126SHawking Zhang *
203ffa02126SHawking Zhang * @adev: amdgpu_device pointer
204ffa02126SHawking Zhang * @ih: amdgpu_ih_ring pointer
205ffa02126SHawking Zhang *
206ffa02126SHawking Zhang * Enable an ih ring buffer (VEGA10)
207ffa02126SHawking Zhang */
vega10_ih_enable_ring(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)208ffa02126SHawking Zhang static int vega10_ih_enable_ring(struct amdgpu_device *adev,
209ffa02126SHawking Zhang struct amdgpu_ih_ring *ih)
210ffa02126SHawking Zhang {
211ffa02126SHawking Zhang struct amdgpu_ih_regs *ih_regs;
212ffa02126SHawking Zhang uint32_t tmp;
213ffa02126SHawking Zhang
214ffa02126SHawking Zhang ih_regs = &ih->ih_regs;
215ffa02126SHawking Zhang
216ffa02126SHawking Zhang /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
217ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
218ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
219ffa02126SHawking Zhang
220ffa02126SHawking Zhang tmp = RREG32(ih_regs->ih_rb_cntl);
221ffa02126SHawking Zhang tmp = vega10_ih_rb_cntl(ih, tmp);
222ffa02126SHawking Zhang if (ih == &adev->irq.ih)
223ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
224b672cb1eSPhilip Yang if (ih == &adev->irq.ih1)
225ffa02126SHawking Zhang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
226ffa02126SHawking Zhang if (amdgpu_sriov_vf(adev)) {
227ffa02126SHawking Zhang if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
228ffa02126SHawking Zhang dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
229ffa02126SHawking Zhang return -ETIMEDOUT;
230ffa02126SHawking Zhang }
231ffa02126SHawking Zhang } else {
232ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_cntl, tmp);
233ffa02126SHawking Zhang }
234ffa02126SHawking Zhang
235ffa02126SHawking Zhang if (ih == &adev->irq.ih) {
236ffa02126SHawking Zhang /* set the ih ring 0 writeback address whether it's enabled or not */
237ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
238ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
239ffa02126SHawking Zhang }
240ffa02126SHawking Zhang
241ffa02126SHawking Zhang /* set rptr, wptr to 0 */
242ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_wptr, 0);
243ffa02126SHawking Zhang WREG32(ih_regs->ih_rb_rptr, 0);
244ffa02126SHawking Zhang
245ffa02126SHawking Zhang WREG32(ih_regs->ih_doorbell_rptr, vega10_ih_doorbell_rptr(ih));
246ffa02126SHawking Zhang
247ffa02126SHawking Zhang return 0;
248ffa02126SHawking Zhang }
249ffa02126SHawking Zhang
250ffa02126SHawking Zhang /**
251282aae55SKen Wang * vega10_ih_irq_init - init and enable the interrupt ring
252282aae55SKen Wang *
253282aae55SKen Wang * @adev: amdgpu_device pointer
254282aae55SKen Wang *
255282aae55SKen Wang * Allocate a ring buffer for the interrupt controller,
256282aae55SKen Wang * enable the RLC, disable interrupts, enable the IH
257282aae55SKen Wang * ring buffer and enable it (VI).
258282aae55SKen Wang * Called at device load and reume.
259282aae55SKen Wang * Returns 0 for success, errors for failure.
260282aae55SKen Wang */
vega10_ih_irq_init(struct amdgpu_device * adev)261282aae55SKen Wang static int vega10_ih_irq_init(struct amdgpu_device *adev)
262282aae55SKen Wang {
26321822b6aSHawking Zhang struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
26421822b6aSHawking Zhang u32 ih_chicken;
265fd95e1b1SHawking Zhang int ret;
26621822b6aSHawking Zhang int i;
267282aae55SKen Wang
268282aae55SKen Wang /* disable irqs */
269fd95e1b1SHawking Zhang ret = vega10_ih_toggle_interrupts(adev, false);
270fd95e1b1SHawking Zhang if (ret)
271fd95e1b1SHawking Zhang return ret;
272282aae55SKen Wang
273bebc0762SHawking Zhang adev->nbio.funcs->ih_control(adev);
274282aae55SKen Wang
27595c0c257SHawking Zhang if (adev->asic_type == CHIP_RENOIR) {
27625344d7eSZhigang Luo ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
27725344d7eSZhigang Luo if (adev->irq.ih.use_bus_addr) {
27825344d7eSZhigang Luo ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
27925344d7eSZhigang Luo MC_SPACE_GPA_ENABLE, 1);
28025344d7eSZhigang Luo }
281f9c84ae5SLe Ma WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
28225344d7eSZhigang Luo }
283f9c84ae5SLe Ma
28421822b6aSHawking Zhang for (i = 0; i < ARRAY_SIZE(ih); i++) {
28521822b6aSHawking Zhang if (ih[i]->ring_size) {
28621822b6aSHawking Zhang ret = vega10_ih_enable_ring(adev, ih[i]);
28721822b6aSHawking Zhang if (ret)
28821822b6aSHawking Zhang return ret;
289470b4250STrigger Huang }
290ad710812SChristian König }
291ad710812SChristian König
292dc1d85cbSAlex Deucher if (!amdgpu_sriov_vf(adev))
293dc1d85cbSAlex Deucher adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
294dc1d85cbSAlex Deucher adev->irq.ih.doorbell_index);
295dc1d85cbSAlex Deucher
296282aae55SKen Wang pci_set_master(adev->pdev);
297282aae55SKen Wang
298282aae55SKen Wang /* enable interrupts */
299fd95e1b1SHawking Zhang ret = vega10_ih_toggle_interrupts(adev, true);
300fd95e1b1SHawking Zhang if (ret)
301282aae55SKen Wang return ret;
302fd95e1b1SHawking Zhang
3037f03b148SHawking Zhang if (adev->irq.ih_soft.ring_size)
3047f03b148SHawking Zhang adev->irq.ih_soft.enabled = true;
3057f03b148SHawking Zhang
306fd95e1b1SHawking Zhang return 0;
307282aae55SKen Wang }
308282aae55SKen Wang
309282aae55SKen Wang /**
310282aae55SKen Wang * vega10_ih_irq_disable - disable interrupts
311282aae55SKen Wang *
312282aae55SKen Wang * @adev: amdgpu_device pointer
313282aae55SKen Wang *
314282aae55SKen Wang * Disable interrupts on the hw (VEGA10).
315282aae55SKen Wang */
vega10_ih_irq_disable(struct amdgpu_device * adev)316282aae55SKen Wang static void vega10_ih_irq_disable(struct amdgpu_device *adev)
317282aae55SKen Wang {
318fd95e1b1SHawking Zhang vega10_ih_toggle_interrupts(adev, false);
319282aae55SKen Wang
320282aae55SKen Wang /* Wait and acknowledge irq */
321282aae55SKen Wang mdelay(1);
322282aae55SKen Wang }
323282aae55SKen Wang
324282aae55SKen Wang /**
325282aae55SKen Wang * vega10_ih_get_wptr - get the IH ring buffer wptr
326282aae55SKen Wang *
327282aae55SKen Wang * @adev: amdgpu_device pointer
3285162e40eSLee Jones * @ih: IH ring buffer to fetch wptr
329282aae55SKen Wang *
330282aae55SKen Wang * Get the IH ring buffer wptr from either the register
331282aae55SKen Wang * or the writeback memory buffer (VEGA10). Also check for
332282aae55SKen Wang * ring buffer overflow and deal with it.
333282aae55SKen Wang * Returns the value of the wptr.
334282aae55SKen Wang */
vega10_ih_get_wptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)3358bb9eb48SChristian König static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
3368bb9eb48SChristian König struct amdgpu_ih_ring *ih)
337282aae55SKen Wang {
338554bdbf6SHawking Zhang u32 wptr, tmp;
339554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs;
340282aae55SKen Wang
341de8341eeSMukul Joshi if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
342b672cb1eSPhilip Yang /* Only ring0 supports writeback. On other rings fall back
343b672cb1eSPhilip Yang * to register-based code with overflow checking below.
344de8341eeSMukul Joshi * ih_soft ring doesn't have any backing hardware registers,
345de8341eeSMukul Joshi * update wptr and return.
346b672cb1eSPhilip Yang */
347d81f78b4SChristian König wptr = le32_to_cpu(*ih->wptr_cpu);
348282aae55SKen Wang
349b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
350b8217575SChristian König goto out;
351b672cb1eSPhilip Yang }
352b672cb1eSPhilip Yang
353b672cb1eSPhilip Yang ih_regs = &ih->ih_regs;
354b8217575SChristian König
355b8217575SChristian König /* Double check that the overflow wasn't already cleared. */
356554bdbf6SHawking Zhang wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
357b8217575SChristian König if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
358b8217575SChristian König goto out;
359b8217575SChristian König
360282aae55SKen Wang wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
361282aae55SKen Wang
362282aae55SKen Wang /* When a ring buffer overflow happen start parsing interrupt
363282aae55SKen Wang * from the last not overwritten vector (wptr + 32). Hopefully
364282aae55SKen Wang * this should allow us to catchup.
365282aae55SKen Wang */
3668bb9eb48SChristian König tmp = (wptr + 32) & ih->ptr_mask;
367b8217575SChristian König dev_warn(adev->dev, "IH ring buffer overflow "
368b8217575SChristian König "(0x%08X, 0x%08X, 0x%08X)\n",
3698bb9eb48SChristian König wptr, ih->rptr, tmp);
3708bb9eb48SChristian König ih->rptr = tmp;
371282aae55SKen Wang
372554bdbf6SHawking Zhang tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
373282aae55SKen Wang tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
374554bdbf6SHawking Zhang WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
375b8217575SChristian König
376*89833979SFriedrich Vock /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
377*89833979SFriedrich Vock * can be detected.
378*89833979SFriedrich Vock */
379*89833979SFriedrich Vock tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
380*89833979SFriedrich Vock WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
381*89833979SFriedrich Vock
382b8217575SChristian König out:
3838bb9eb48SChristian König return (wptr & ih->ptr_mask);
384282aae55SKen Wang }
385282aae55SKen Wang
386282aae55SKen Wang /**
38774dcfe74STrigger Huang * vega10_ih_irq_rearm - rearm IRQ if lost
38874dcfe74STrigger Huang *
38974dcfe74STrigger Huang * @adev: amdgpu_device pointer
3905162e40eSLee Jones * @ih: IH ring to match
39174dcfe74STrigger Huang *
39274dcfe74STrigger Huang */
vega10_ih_irq_rearm(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)39374dcfe74STrigger Huang static void vega10_ih_irq_rearm(struct amdgpu_device *adev,
39474dcfe74STrigger Huang struct amdgpu_ih_ring *ih)
39574dcfe74STrigger Huang {
39674dcfe74STrigger Huang uint32_t v = 0;
39774dcfe74STrigger Huang uint32_t i = 0;
398554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs;
39974dcfe74STrigger Huang
400554bdbf6SHawking Zhang ih_regs = &ih->ih_regs;
40174dcfe74STrigger Huang /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
40274dcfe74STrigger Huang for (i = 0; i < MAX_REARM_RETRY; i++) {
403554bdbf6SHawking Zhang v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
40474dcfe74STrigger Huang if ((v < ih->ring_size) && (v != ih->rptr))
40574dcfe74STrigger Huang WDOORBELL32(ih->doorbell_index, ih->rptr);
40674dcfe74STrigger Huang else
40774dcfe74STrigger Huang break;
40874dcfe74STrigger Huang }
40974dcfe74STrigger Huang }
41074dcfe74STrigger Huang
41174dcfe74STrigger Huang /**
412282aae55SKen Wang * vega10_ih_set_rptr - set the IH ring buffer rptr
413282aae55SKen Wang *
414282aae55SKen Wang * @adev: amdgpu_device pointer
4155162e40eSLee Jones * @ih: IH ring buffer to set rptr
416282aae55SKen Wang *
417282aae55SKen Wang * Set the IH ring buffer rptr.
418282aae55SKen Wang */
vega10_ih_set_rptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)4198bb9eb48SChristian König static void vega10_ih_set_rptr(struct amdgpu_device *adev,
4208bb9eb48SChristian König struct amdgpu_ih_ring *ih)
421282aae55SKen Wang {
422554bdbf6SHawking Zhang struct amdgpu_ih_regs *ih_regs;
423554bdbf6SHawking Zhang
424de8341eeSMukul Joshi if (ih == &adev->irq.ih_soft)
425de8341eeSMukul Joshi return;
426de8341eeSMukul Joshi
4278bb9eb48SChristian König if (ih->use_doorbell) {
428282aae55SKen Wang /* XXX check if swapping is necessary on BE */
429d81f78b4SChristian König *ih->rptr_cpu = ih->rptr;
4308bb9eb48SChristian König WDOORBELL32(ih->doorbell_index, ih->rptr);
43174dcfe74STrigger Huang
43274dcfe74STrigger Huang if (amdgpu_sriov_vf(adev))
43374dcfe74STrigger Huang vega10_ih_irq_rearm(adev, ih);
434554bdbf6SHawking Zhang } else {
435554bdbf6SHawking Zhang ih_regs = &ih->ih_regs;
436554bdbf6SHawking Zhang WREG32(ih_regs->ih_rb_rptr, ih->rptr);
437282aae55SKen Wang }
438282aae55SKen Wang }
439282aae55SKen Wang
440cf67950eSChristian König /**
441cf67950eSChristian König * vega10_ih_self_irq - dispatch work for ring 1 and 2
442cf67950eSChristian König *
443cf67950eSChristian König * @adev: amdgpu_device pointer
444cf67950eSChristian König * @source: irq source
445cf67950eSChristian König * @entry: IV with WPTR update
446cf67950eSChristian König *
447cf67950eSChristian König * Update the WPTR from the IV and schedule work to handle the entries.
448cf67950eSChristian König */
vega10_ih_self_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)449cf67950eSChristian König static int vega10_ih_self_irq(struct amdgpu_device *adev,
450cf67950eSChristian König struct amdgpu_irq_src *source,
451cf67950eSChristian König struct amdgpu_iv_entry *entry)
452cf67950eSChristian König {
453cf67950eSChristian König switch (entry->ring_id) {
454cf67950eSChristian König case 1:
455cf67950eSChristian König schedule_work(&adev->irq.ih1_work);
456cf67950eSChristian König break;
457cf67950eSChristian König case 2:
458cf67950eSChristian König schedule_work(&adev->irq.ih2_work);
459cf67950eSChristian König break;
460cf67950eSChristian König default: break;
461cf67950eSChristian König }
462cf67950eSChristian König return 0;
463cf67950eSChristian König }
464cf67950eSChristian König
465cf67950eSChristian König static const struct amdgpu_irq_src_funcs vega10_ih_self_irq_funcs = {
466cf67950eSChristian König .process = vega10_ih_self_irq,
467cf67950eSChristian König };
468cf67950eSChristian König
vega10_ih_set_self_irq_funcs(struct amdgpu_device * adev)469cf67950eSChristian König static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev)
470cf67950eSChristian König {
471cf67950eSChristian König adev->irq.self_irq.num_types = 0;
472cf67950eSChristian König adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs;
473cf67950eSChristian König }
474cf67950eSChristian König
vega10_ih_early_init(void * handle)475282aae55SKen Wang static int vega10_ih_early_init(void *handle)
476282aae55SKen Wang {
477282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
478282aae55SKen Wang
479282aae55SKen Wang vega10_ih_set_interrupt_funcs(adev);
480cf67950eSChristian König vega10_ih_set_self_irq_funcs(adev);
481282aae55SKen Wang return 0;
482282aae55SKen Wang }
483282aae55SKen Wang
vega10_ih_sw_init(void * handle)484282aae55SKen Wang static int vega10_ih_sw_init(void *handle)
485282aae55SKen Wang {
486282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
487cf67950eSChristian König int r;
488cf67950eSChristian König
489cf67950eSChristian König r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
490cf67950eSChristian König &adev->irq.self_irq);
491cf67950eSChristian König if (r)
492cf67950eSChristian König return r;
493282aae55SKen Wang
494bf80d34bSPhilip Yang r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, true);
495282aae55SKen Wang if (r)
496282aae55SKen Wang return r;
497282aae55SKen Wang
4981ae64cecSChristian König adev->irq.ih.use_doorbell = true;
4991ae64cecSChristian König adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
5001ae64cecSChristian König
5019f18985dSHawking Zhang if (!(adev->flags & AMD_IS_APU)) {
502ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, true);
503ad710812SChristian König if (r)
504ad710812SChristian König return r;
505ad710812SChristian König
5061ae64cecSChristian König adev->irq.ih1.use_doorbell = true;
507b51cd19eSChristian König adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
5081ae64cecSChristian König
509ad710812SChristian König r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
510ad710812SChristian König if (r)
511ad710812SChristian König return r;
512ad710812SChristian König
5131ae64cecSChristian König adev->irq.ih2.use_doorbell = true;
514b51cd19eSChristian König adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
5159f18985dSHawking Zhang }
516f0594717SHawking Zhang /* initialize ih control registers offset */
517f0594717SHawking Zhang vega10_ih_init_register_offset(adev);
518f0594717SHawking Zhang
519bf80d34bSPhilip Yang r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
52047509189SChristian König if (r)
52147509189SChristian König return r;
52247509189SChristian König
523282aae55SKen Wang r = amdgpu_irq_init(adev);
524282aae55SKen Wang
525282aae55SKen Wang return r;
526282aae55SKen Wang }
527282aae55SKen Wang
vega10_ih_sw_fini(void * handle)528282aae55SKen Wang static int vega10_ih_sw_fini(void *handle)
529282aae55SKen Wang {
530282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
531282aae55SKen Wang
53272c8c97bSAndrey Grodzovsky amdgpu_irq_fini_sw(adev);
533282aae55SKen Wang
534282aae55SKen Wang return 0;
535282aae55SKen Wang }
536282aae55SKen Wang
vega10_ih_hw_init(void * handle)537282aae55SKen Wang static int vega10_ih_hw_init(void *handle)
538282aae55SKen Wang {
539282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
540282aae55SKen Wang
54138c1c736SMinghao Chi return vega10_ih_irq_init(adev);
542282aae55SKen Wang }
543282aae55SKen Wang
vega10_ih_hw_fini(void * handle)544282aae55SKen Wang static int vega10_ih_hw_fini(void *handle)
545282aae55SKen Wang {
546282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
547282aae55SKen Wang
548282aae55SKen Wang vega10_ih_irq_disable(adev);
549282aae55SKen Wang
550282aae55SKen Wang return 0;
551282aae55SKen Wang }
552282aae55SKen Wang
vega10_ih_suspend(void * handle)553282aae55SKen Wang static int vega10_ih_suspend(void *handle)
554282aae55SKen Wang {
555282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
556282aae55SKen Wang
557282aae55SKen Wang return vega10_ih_hw_fini(adev);
558282aae55SKen Wang }
559282aae55SKen Wang
vega10_ih_resume(void * handle)560282aae55SKen Wang static int vega10_ih_resume(void *handle)
561282aae55SKen Wang {
562282aae55SKen Wang struct amdgpu_device *adev = (struct amdgpu_device *)handle;
563282aae55SKen Wang
564282aae55SKen Wang return vega10_ih_hw_init(adev);
565282aae55SKen Wang }
566282aae55SKen Wang
vega10_ih_is_idle(void * handle)567282aae55SKen Wang static bool vega10_ih_is_idle(void *handle)
568282aae55SKen Wang {
569282aae55SKen Wang /* todo */
570282aae55SKen Wang return true;
571282aae55SKen Wang }
572282aae55SKen Wang
vega10_ih_wait_for_idle(void * handle)573282aae55SKen Wang static int vega10_ih_wait_for_idle(void *handle)
574282aae55SKen Wang {
575282aae55SKen Wang /* todo */
576282aae55SKen Wang return -ETIMEDOUT;
577282aae55SKen Wang }
578282aae55SKen Wang
vega10_ih_soft_reset(void * handle)579282aae55SKen Wang static int vega10_ih_soft_reset(void *handle)
580282aae55SKen Wang {
581282aae55SKen Wang /* todo */
582282aae55SKen Wang
583282aae55SKen Wang return 0;
584282aae55SKen Wang }
585282aae55SKen Wang
vega10_ih_update_clockgating_state(struct amdgpu_device * adev,bool enable)586227f7d58SKenneth Feng static void vega10_ih_update_clockgating_state(struct amdgpu_device *adev,
587227f7d58SKenneth Feng bool enable)
588227f7d58SKenneth Feng {
589227f7d58SKenneth Feng uint32_t data, def, field_val;
590227f7d58SKenneth Feng
591227f7d58SKenneth Feng if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
592227f7d58SKenneth Feng def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
593227f7d58SKenneth Feng field_val = enable ? 0 : 1;
594227f7d58SKenneth Feng /**
5952601fa64SHawking Zhang * Vega10/12 and RAVEN don't have IH_BUFFER_MEM_CLK_SOFT_OVERRIDE field.
596227f7d58SKenneth Feng */
5972601fa64SHawking Zhang if (adev->asic_type == CHIP_RENOIR)
598227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL,
599227f7d58SKenneth Feng IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
600227f7d58SKenneth Feng
601227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL,
602227f7d58SKenneth Feng DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
603227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL,
604227f7d58SKenneth Feng OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
605227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL,
606227f7d58SKenneth Feng LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
607227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL,
608227f7d58SKenneth Feng DYN_CLK_SOFT_OVERRIDE, field_val);
609227f7d58SKenneth Feng data = REG_SET_FIELD(data, IH_CLK_CTRL,
610227f7d58SKenneth Feng REG_CLK_SOFT_OVERRIDE, field_val);
611227f7d58SKenneth Feng if (def != data)
612227f7d58SKenneth Feng WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
613227f7d58SKenneth Feng }
614227f7d58SKenneth Feng }
615227f7d58SKenneth Feng
vega10_ih_set_clockgating_state(void * handle,enum amd_clockgating_state state)616282aae55SKen Wang static int vega10_ih_set_clockgating_state(void *handle,
617282aae55SKen Wang enum amd_clockgating_state state)
618282aae55SKen Wang {
619227f7d58SKenneth Feng struct amdgpu_device *adev = (struct amdgpu_device *)handle;
620227f7d58SKenneth Feng
621227f7d58SKenneth Feng vega10_ih_update_clockgating_state(adev,
622a9d4fe2fSNirmoy Das state == AMD_CG_STATE_GATE);
623282aae55SKen Wang return 0;
624227f7d58SKenneth Feng
625282aae55SKen Wang }
626282aae55SKen Wang
vega10_ih_set_powergating_state(void * handle,enum amd_powergating_state state)627282aae55SKen Wang static int vega10_ih_set_powergating_state(void *handle,
628282aae55SKen Wang enum amd_powergating_state state)
629282aae55SKen Wang {
630282aae55SKen Wang return 0;
631282aae55SKen Wang }
632282aae55SKen Wang
633282aae55SKen Wang const struct amd_ip_funcs vega10_ih_ip_funcs = {
634282aae55SKen Wang .name = "vega10_ih",
635282aae55SKen Wang .early_init = vega10_ih_early_init,
636282aae55SKen Wang .late_init = NULL,
637282aae55SKen Wang .sw_init = vega10_ih_sw_init,
638282aae55SKen Wang .sw_fini = vega10_ih_sw_fini,
639282aae55SKen Wang .hw_init = vega10_ih_hw_init,
640282aae55SKen Wang .hw_fini = vega10_ih_hw_fini,
641282aae55SKen Wang .suspend = vega10_ih_suspend,
642282aae55SKen Wang .resume = vega10_ih_resume,
643282aae55SKen Wang .is_idle = vega10_ih_is_idle,
644282aae55SKen Wang .wait_for_idle = vega10_ih_wait_for_idle,
645282aae55SKen Wang .soft_reset = vega10_ih_soft_reset,
646282aae55SKen Wang .set_clockgating_state = vega10_ih_set_clockgating_state,
647282aae55SKen Wang .set_powergating_state = vega10_ih_set_powergating_state,
648282aae55SKen Wang };
649282aae55SKen Wang
650282aae55SKen Wang static const struct amdgpu_ih_funcs vega10_ih_funcs = {
651282aae55SKen Wang .get_wptr = vega10_ih_get_wptr,
65240838281SHawking Zhang .decode_iv = amdgpu_ih_decode_iv_helper,
6533c2d6ea2SPhilip Yang .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
654282aae55SKen Wang .set_rptr = vega10_ih_set_rptr
655282aae55SKen Wang };
656282aae55SKen Wang
vega10_ih_set_interrupt_funcs(struct amdgpu_device * adev)657282aae55SKen Wang static void vega10_ih_set_interrupt_funcs(struct amdgpu_device *adev)
658282aae55SKen Wang {
659282aae55SKen Wang adev->irq.ih_funcs = &vega10_ih_funcs;
660282aae55SKen Wang }
661282aae55SKen Wang
662282aae55SKen Wang const struct amdgpu_ip_block_version vega10_ih_ip_block =
663282aae55SKen Wang {
664282aae55SKen Wang .type = AMD_IP_BLOCK_TYPE_IH,
665282aae55SKen Wang .major = 4,
666282aae55SKen Wang .minor = 0,
667282aae55SKen Wang .rev = 0,
668282aae55SKen Wang .funcs = &vega10_ih_ip_funcs,
669282aae55SKen Wang };
670