Lines Matching +full:buffer +full:- +full:enable

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #define ENE_STATUS		0	/* hardware status - unused */
18 #define ENE_FW_SAMPLE_BUFFER	0xF8F0	/* sample buffer */
24 #define	ENE_FW1_ENABLE		0x01	/* enable fw processing */
26 #define ENE_FW1_HAS_EXTRA_BUF	0x04	/* fw uses extra buffer*/
27 #define ENE_FW1_EXTRA_BUF_HND	0x08	/* extra buffer handshake bit*/
30 #define ENE_FW1_WPATTERN	0x20	/* enable wake pattern */
31 #define ENE_FW1_WAKE		0x40	/* enable wake from S3 */
32 #define ENE_FW1_IRQ		0x80	/* enable interrupt */
36 #define ENE_FW2_BUF_WPTR	0x01	/* which half of the buffer to read */
45 /* firmware RX pointer for new style buffer */
56 #define ENE_GPIOFS1_GPIO0D	0x20	/* enable tx output on GPIO0D */
58 #define ENE_GPIOFS8_GPIO41	0x02	/* enable tx output on GPIO40 */
80 #define ENE_CIRCFG_RX_EN	0x01	/* RX enable */
81 #define ENE_CIRCFG_RX_IRQ	0x02	/* Enable hardware interrupt */
83 #define ENE_CIRCFG_CARR_DEMOD	0x08	/* Enable carrier demodulator */
85 #define ENE_CIRCFG_TX_EN	0x10	/* TX enable */
96 #define ENE_CIRCFG2_CARR_DETECT	0x10	/* Enable carrier detection */
101 /* Knobs for protocol decoding - will document when/if will use them */
108 /* Actual register which contains RLC RX data - read by firmware */
112 /* RLC configuration - sample period (1us resolution) + idle mode */
117 /* Two byte RLC TX buffer */
125  * Low nibble  - number of carrier pulses to average
126  * High nibble - number of initial carrier pulses to discard
193 	bool hw_extra_buffer;			/* hardware has 'extra buffer' */
199 	/* Extra RX buffer location */
214 	/* TX buffer */
215 	unsigned *tx_buffer;			/* input samples buffer*/
216 	int tx_pos;				/* position in that buffer */
217 	int tx_len;				/* current len of tx buffer */