Lines Matching +full:buffer +full:- +full:enable
53 #define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */
67 #define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */
69 #define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */
72 #define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */
73 #define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */
74 #define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */
75 #define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */
100 #define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */
103 #define IO_REG_FCTR 0x1e0 /* Free-Running Counter */
115 #define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */
116 #define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */
123 #define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */
124 #define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */
127 #define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */
128 #define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */
135 #define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */
136 #define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */
138 #define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */
139 #define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */
140 #define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */
143 * The lower 16 bits are system-specific. Bits 15,11:8 are common and
144 * defined here. The rest is defined in system-specific headers.