usb/renesas_usbhs/common.h

1 /* SPDX-License-Identifier: GPL-1.0+ */
100 #define D2FIFOSEL	0x00F0	/* for R-Car Gen2 */
101 #define D2FIFOCTR	0x00F2	/* for R-Car Gen2 */
102 #define D3FIFOSEL	0x00F4	/* for R-Car Gen2 */
103 #define D3FIFOCTR	0x00F6	/* for R-Car Gen2 */
107 #define SCKE	(1 << 10)	/* USB Module Clock Enable */
108 #define CNEN	(1 << 8)	/* Single-ended receiver operation Enable */
109 #define HSE	(1 << 7)	/* High-Speed Operation Enable */
111 #define DRPD	(1 << 5)	/* D+ Line/D- Line Resistance Control */
113 #define USBE	(1 << 0)	/* USB Module Operation Enable */
115 #define UPLLE	(1 << 1)	/* USB PLL Enable for RZ/A1 */
121 #define UACT	(1 << 4)	/* USB Bus Enable */
123 #define  RHST_LOW_SPEED  1	/* Low-speed connection */
124 #define  RHST_FULL_SPEED 2	/* Full-speed connection */
125 #define  RHST_HIGH_SPEED 3	/* High-speed connection */
128 #define DREQE	(1 << 12)	/* DMA Transfer Request Enable */
132 #define BVAL	(1 << 15)	/* Buffer Memory Enable Flag */
133 #define BCLR	(1 << 14)	/* CPU buffer clear */
138 #define VBSE	(1 << 15)	/* Enable IRQ VBUS_0 and VBUSIN_0 */
139 #define RSME	(1 << 14)	/* Enable IRQ Resume */
140 #define SOFE	(1 << 13)	/* Enable IRQ Frame Number Update */
141 #define DVSE	(1 << 12)	/* Enable IRQ Device State Transition */
142 #define CTRE	(1 << 11)	/* Enable IRQ Control Stage Transition */
143 #define BEMPE	(1 << 10)	/* Enable IRQ Buffer Empty */
144 #define NRDYE	(1 << 9)	/* Enable IRQ Buffer Not Ready Response */
145 #define BRDYE	(1 << 8)	/* Enable IRQ Buffer Ready */
148 #define BCHGE	(1 << 14)	/* USB Bus Change Interrupt Enable */
149 #define DTCHE	(1 << 12)	/* Disconnection Detect Interrupt Enable */
150 #define ATTCHE	(1 << 11)	/* Connection Detect Interrupt Enable */
151 #define EOFERRE	(1 << 6)	/* EOF Error Detect Interrupt Enable */
152 #define SIGNE	(1 << 5)	/* Setup Transaction Error Interrupt Enable */
153 #define SACKE	(1 << 4)	/* Setup Transaction ACK Interrupt Enable */
159 #define BEMP	(1 << 10)	/* Buffer Empty Interrupt Status */
160 #define BRDY	(1 << 8)	/* Buffer Ready Interrupt Status */
196 #define DBLB		(1 << 9)	/* Double Buffer Mode */
213 #define BSTS		(1 << 15)	/* Buffer Status */
215 #define INBUFM		(1 << 14)	/* (PIPEnCTR) Transfer Buffer Monitor */
217 #define	ACLRM		(1 << 9)	/* Buffer Auto-Clear Mode */
228 #define CCPL		(1 << 2)	/* Control Transfer End Enable */
231 #define TRENB		(1 << 9)	/* Transaction Counter Enable */
301 void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
302 void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
303 void usbhs_sys_function_pullup(struct usbhs_priv *priv, int enable);
318 int usbhs_vbus_ctrl(struct usbhs_priv *priv, int enable);
341 #define usbhs_get_dparam(priv, param)	(priv->dparam.param)
342 #define usbhs_priv_to_pdev(priv)	(priv->pdev)
343 #define usbhs_priv_to_dev(priv)		(&priv->pdev->dev)
344 #define usbhs_priv_to_lock(priv)	(&priv->lock)