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/openbmc/linux/drivers/mtd/spi-nor/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o
4 spi-nor-objs += atmel.o
5 spi-nor-objs += catalyst.o
6 spi-nor-objs += eon.o
7 spi-nor-objs += esmt.o
8 spi-nor-objs += everspin.o
9 spi-nor-objs += fujitsu.o
10 spi-nor-objs += gigadevice.o
11 spi-nor-objs += intel.o
[all …]
H A Dsysfs.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/mtd/spi-nor.h>
4 #include <linux/spi/spi.h>
5 #include <linux/spi/spi-mem.h>
13 struct spi_device *spi = to_spi_device(dev); in manufacturer_show() local
14 struct spi_mem *spimem = spi_get_drvdata(spi); in manufacturer_show()
15 struct spi_nor *nor = spi_mem_get_drvdata(spimem); in manufacturer_show() local
17 return sysfs_emit(buf, "%s\n", nor->manufacturer->name); in manufacturer_show()
24 struct spi_device *spi = to_spi_device(dev); in partname_show() local
25 struct spi_mem *spimem = spi_get_drvdata(spi); in partname_show()
[all …]
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 /* Standard SPI NOR flash operations. */
155 /* Dual SPI */
161 /* Quad SPI */
167 /* Octal SPI */
180 /* Quad SPI */
185 /* Octal SPI */
195 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
201 * @opcode: the SPI command op code to erase the sector/block.
216 * struct spi_nor_erase_command - Used for non-uniform erases
[all …]
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mtd/spi-nor.h>
23 #include <linux/spi/flash.h>
30 * For everything but full-chip erase; probably could be much smaller, but kept
36 * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
47 * spi_nor_get_cmd_ext() - Ge
57 spi_nor_get_cmd_ext(const struct spi_nor * nor,const struct spi_mem_op * op) spi_nor_get_cmd_ext() argument
80 spi_nor_spimem_setup_op(const struct spi_nor * nor,struct spi_mem_op * op,const enum spi_nor_protocol proto) spi_nor_spimem_setup_op() argument
128 spi_nor_spimem_bounce(struct spi_nor * nor,struct spi_mem_op * op) spi_nor_spimem_bounce() argument
149 spi_nor_spimem_exec_op(struct spi_nor * nor,struct spi_mem_op * op) spi_nor_spimem_exec_op() argument
160 spi_nor_controller_ops_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,size_t len) spi_nor_controller_ops_read_reg() argument
169 spi_nor_controller_ops_write_reg(struct spi_nor * nor,u8 opcode,const u8 * buf,size_t len) spi_nor_controller_ops_write_reg() argument
178 spi_nor_controller_ops_erase(struct spi_nor * nor,loff_t offs) spi_nor_controller_ops_erase() argument
196 spi_nor_spimem_read_data(struct spi_nor * nor,loff_t from,size_t len,u8 * buf) spi_nor_spimem_read_data() argument
242 spi_nor_read_data(struct spi_nor * nor,loff_t from,size_t len,u8 * buf) spi_nor_read_data() argument
260 spi_nor_spimem_write_data(struct spi_nor * nor,loff_t to,size_t len,const u8 * buf) spi_nor_spimem_write_data() argument
301 spi_nor_write_data(struct spi_nor * nor,loff_t to,size_t len,const u8 * buf) spi_nor_write_data() argument
319 spi_nor_read_any_reg(struct spi_nor * nor,struct spi_mem_op * op,enum spi_nor_protocol proto) spi_nor_read_any_reg() argument
341 spi_nor_write_any_volatile_reg(struct spi_nor * nor,struct spi_mem_op * op,enum spi_nor_protocol proto) spi_nor_write_any_volatile_reg() argument
362 spi_nor_write_enable(struct spi_nor * nor) spi_nor_write_enable() argument
389 spi_nor_write_disable(struct spi_nor * nor) spi_nor_write_disable() argument
423 spi_nor_read_id(struct spi_nor * nor,u8 naddr,u8 ndummy,u8 * id,enum spi_nor_protocol proto) spi_nor_read_id() argument
449 spi_nor_read_sr(struct spi_nor * nor,u8 * sr) spi_nor_read_sr() argument
489 spi_nor_read_cr(struct spi_nor * nor,u8 * cr) spi_nor_read_cr() argument
520 spi_nor_set_4byte_addr_mode_en4b_ex4b(struct spi_nor * nor,bool enable) spi_nor_set_4byte_addr_mode_en4b_ex4b() argument
553 spi_nor_set_4byte_addr_mode_wren_en4b_ex4b(struct spi_nor * nor,bool enable) spi_nor_set_4byte_addr_mode_wren_en4b_ex4b() argument
582 spi_nor_set_4byte_addr_mode_brwr(struct spi_nor * nor,bool enable) spi_nor_set_4byte_addr_mode_brwr() argument
612 spi_nor_sr_ready(struct spi_nor * nor) spi_nor_sr_ready() argument
629 spi_nor_use_parallel_locking(struct spi_nor * nor) spi_nor_use_parallel_locking() argument
635 spi_nor_rww_start_rdst(struct spi_nor * nor) spi_nor_rww_start_rdst() argument
654 spi_nor_rww_end_rdst(struct spi_nor * nor) spi_nor_rww_end_rdst() argument
666 spi_nor_lock_rdst(struct spi_nor * nor) spi_nor_lock_rdst() argument
674 spi_nor_unlock_rdst(struct spi_nor * nor) spi_nor_unlock_rdst() argument
688 spi_nor_ready(struct spi_nor * nor) spi_nor_ready() argument
715 spi_nor_wait_till_ready_with_timeout(struct spi_nor * nor,unsigned long timeout_jiffies) spi_nor_wait_till_ready_with_timeout() argument
748 spi_nor_wait_till_ready(struct spi_nor * nor) spi_nor_wait_till_ready() argument
760 spi_nor_global_block_unlock(struct spi_nor * nor) spi_nor_global_block_unlock() argument
795 spi_nor_write_sr(struct spi_nor * nor,const u8 * sr,size_t len) spi_nor_write_sr() argument
830 spi_nor_write_sr1_and_check(struct spi_nor * nor,u8 sr1) spi_nor_write_sr1_and_check() argument
862 spi_nor_write_16bit_sr_and_check(struct spi_nor * nor,u8 sr1) spi_nor_write_16bit_sr_and_check() argument
937 spi_nor_write_16bit_cr_and_check(struct spi_nor * nor,u8 cr) spi_nor_write_16bit_cr_and_check() argument
989 spi_nor_write_sr_and_check(struct spi_nor * nor,u8 sr1) spi_nor_write_sr_and_check() argument
1005 spi_nor_write_sr2(struct spi_nor * nor,const u8 * sr2) spi_nor_write_sr2() argument
1041 spi_nor_read_sr2(struct spi_nor * nor,u8 * sr2) spi_nor_read_sr2() argument
1068 spi_nor_erase_chip(struct spi_nor * nor) spi_nor_erase_chip() argument
1151 spi_nor_has_uniform_erase(const struct spi_nor * nor) spi_nor_has_uniform_erase() argument
1156 spi_nor_set_4byte_opcodes(struct spi_nor * nor) spi_nor_set_4byte_opcodes() argument
1175 spi_nor_prep(struct spi_nor * nor) spi_nor_prep() argument
1185 spi_nor_unprep(struct spi_nor * nor) spi_nor_unprep() argument
1200 spi_nor_rww_start_io(struct spi_nor * nor) spi_nor_rww_start_io() argument
1218 spi_nor_rww_end_io(struct spi_nor * nor) spi_nor_rww_end_io() argument
1225 spi_nor_lock_device(struct spi_nor * nor) spi_nor_lock_device() argument
1233 spi_nor_unlock_device(struct spi_nor * nor) spi_nor_unlock_device() argument
1242 spi_nor_rww_start_exclusive(struct spi_nor * nor) spi_nor_rww_start_exclusive() argument
1262 spi_nor_rww_end_exclusive(struct spi_nor * nor) spi_nor_rww_end_exclusive() argument
1273 spi_nor_prep_and_lock(struct spi_nor * nor) spi_nor_prep_and_lock() argument
1290 spi_nor_unlock_and_unprep(struct spi_nor * nor) spi_nor_unlock_and_unprep() argument
1303 spi_nor_rww_start_pe(struct spi_nor * nor,loff_t start,size_t len) spi_nor_rww_start_pe() argument
1333 spi_nor_rww_end_pe(struct spi_nor * nor,loff_t start,size_t len) spi_nor_rww_end_pe() argument
1350 spi_nor_prep_and_lock_pe(struct spi_nor * nor,loff_t start,size_t len) spi_nor_prep_and_lock_pe() argument
1367 spi_nor_unlock_and_unprep_pe(struct spi_nor * nor,loff_t start,size_t len) spi_nor_unlock_and_unprep_pe() argument
1380 spi_nor_rww_start_rd(struct spi_nor * nor,loff_t start,size_t len) spi_nor_rww_start_rd() argument
1411 spi_nor_rww_end_rd(struct spi_nor * nor,loff_t start,size_t len) spi_nor_rww_end_rd() argument
1429 spi_nor_prep_and_lock_rd(struct spi_nor * nor,loff_t start,size_t len) spi_nor_prep_and_lock_rd() argument
1446 spi_nor_unlock_and_unprep_rd(struct spi_nor * nor,loff_t start,size_t len) spi_nor_unlock_and_unprep_rd() argument
1458 spi_nor_convert_addr(struct spi_nor * nor,loff_t addr) spi_nor_convert_addr() argument
1469 spi_nor_erase_sector(struct spi_nor * nor,u32 addr) spi_nor_erase_sector() argument
1679 spi_nor_init_erase_cmd_list(struct spi_nor * nor,struct list_head * erase_list,u64 addr,u32 len) spi_nor_init_erase_cmd_list() argument
1746 spi_nor_erase_multi_sectors(struct spi_nor * nor,u64 addr,u32 len) spi_nor_erase_multi_sectors() argument
1801 struct spi_nor *nor = mtd_to_spi_nor(mtd); spi_nor_erase() local
1909 spi_nor_sr1_bit6_quad_enable(struct spi_nor * nor) spi_nor_sr1_bit6_quad_enable() argument
1934 spi_nor_sr2_bit1_quad_enable(struct spi_nor * nor) spi_nor_sr2_bit1_quad_enable() argument
1965 spi_nor_sr2_bit7_quad_enable(struct spi_nor * nor) spi_nor_sr2_bit7_quad_enable() argument
2031 spi_nor_match_id(struct spi_nor * nor,const u8 * id) spi_nor_match_id() argument
2051 spi_nor_detect(struct spi_nor * nor) spi_nor_detect() argument
2088 struct spi_nor *nor = mtd_to_spi_nor(mtd); spi_nor_read() local
2135 struct spi_nor *nor = mtd_to_spi_nor(mtd); spi_nor_write() local
2196 spi_nor_check(struct spi_nor * nor) spi_nor_check() argument
2298 spi_nor_spimem_check_op(struct spi_nor * nor,struct spi_mem_op * op) spi_nor_spimem_check_op() argument
2329 spi_nor_spimem_check_readop(struct spi_nor * nor,const struct spi_nor_read_command * read) spi_nor_spimem_check_readop() argument
2353 spi_nor_spimem_check_pp(struct spi_nor * nor,const struct spi_nor_pp_command * pp) spi_nor_spimem_check_pp() argument
2371 spi_nor_spimem_adjust_hwcaps(struct spi_nor * nor,u32 * hwcaps) spi_nor_spimem_adjust_hwcaps() argument
2450 spi_nor_post_bfpt_fixups(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt) spi_nor_post_bfpt_fixups() argument
2470 spi_nor_select_read(struct spi_nor * nor,u32 shared_hwcaps) spi_nor_select_read() argument
2501 spi_nor_select_pp(struct spi_nor * nor,u32 shared_hwcaps) spi_nor_select_pp() argument
2581 spi_nor_select_erase(struct spi_nor * nor) spi_nor_select_erase() argument
2629 spi_nor_default_setup(struct spi_nor * nor,const struct spi_nor_hwcaps * hwcaps) spi_nor_default_setup() argument
2690 spi_nor_set_addr_nbytes(struct spi_nor * nor) spi_nor_set_addr_nbytes() argument
2733 spi_nor_setup(struct spi_nor * nor,const struct spi_nor_hwcaps * hwcaps) spi_nor_setup() argument
2753 spi_nor_manufacturer_init_params(struct spi_nor * nor) spi_nor_manufacturer_init_params() argument
2772 spi_nor_no_sfdp_init_params(struct spi_nor * nor) spi_nor_no_sfdp_init_params() argument
2840 spi_nor_init_flags(struct spi_nor * nor) spi_nor_init_flags() argument
2885 spi_nor_init_fixup_flags(struct spi_nor * nor) spi_nor_init_fixup_flags() argument
2904 spi_nor_late_init_params(struct spi_nor * nor) spi_nor_late_init_params() argument
2950 spi_nor_sfdp_init_params_deprecated(struct spi_nor * nor) spi_nor_sfdp_init_params_deprecated() argument
2971 spi_nor_init_params_deprecated(struct spi_nor * nor) spi_nor_init_params_deprecated() argument
2990 spi_nor_init_default_params(struct spi_nor * nor) spi_nor_init_default_params() argument
3076 spi_nor_init_params(struct spi_nor * nor) spi_nor_init_params() argument
3107 spi_nor_set_octal_dtr(struct spi_nor * nor,bool enable) spi_nor_set_octal_dtr() argument
3139 spi_nor_quad_enable(struct spi_nor * nor) spi_nor_quad_enable() argument
3158 spi_nor_set_4byte_addr_mode(struct spi_nor * nor,bool enable) spi_nor_set_4byte_addr_mode() argument
3178 spi_nor_init(struct spi_nor * nor) spi_nor_init() argument
3244 spi_nor_soft_reset(struct spi_nor * nor) spi_nor_soft_reset() argument
3280 struct spi_nor *nor = mtd_to_spi_nor(mtd); spi_nor_suspend() local
3294 struct spi_nor *nor = mtd_to_spi_nor(mtd); spi_nor_resume() local
3307 struct spi_nor *nor = mtd_to_spi_nor(master); spi_nor_get_device() local
3324 struct spi_nor *nor = mtd_to_spi_nor(master); spi_nor_put_device() local
3335 spi_nor_restore(struct spi_nor * nor) spi_nor_restore() argument
3356 spi_nor_match_name(struct spi_nor * nor,const char * name) spi_nor_match_name() argument
3373 spi_nor_get_flash_info(struct spi_nor * nor,const char * name) spi_nor_get_flash_info() argument
3411 spi_nor_set_mtd_info(struct spi_nor * nor) spi_nor_set_mtd_info() argument
3444 spi_nor_hw_reset(struct spi_nor * nor) spi_nor_hw_reset() argument
3465 spi_nor_scan(struct spi_nor * nor,const char * name,const struct spi_nor_hwcaps * hwcaps) spi_nor_scan() argument
3559 spi_nor_create_read_dirmap(struct spi_nor * nor) spi_nor_create_read_dirmap() argument
3590 spi_nor_create_write_dirmap(struct spi_nor * nor) spi_nor_create_write_dirmap() argument
3621 struct spi_device *spi = spimem->spi; spi_nor_probe() local
3623 struct spi_nor *nor; spi_nor_probe() local
3696 struct spi_nor *nor = spi_mem_get_drvdata(spimem); spi_nor_remove() local
3706 struct spi_nor *nor = spi_mem_get_drvdata(spimem); spi_nor_shutdown() local
[all...]
/openbmc/u-boot/drivers/spi/
H A DKconfig1 menuconfig SPI config
2 bool "SPI Support"
4 if SPI
7 bool "Enable Driver Model for SPI drivers"
10 Enable driver model for SPI. The SPI slave interface
12 the SPI uclass. Drivers provide methods to access the SPI
14 include/spi.h. The existing spi_slave structure is attached
16 typically use driver-private data instead of extending the
20 bool "SPI memory extension"
22 Enable this option if you want to enable the SPI memory extension.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mtk-nor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Serial NOR flash controller for MediaTek ARM SoCs
10 - Bayi Cheng <bayi.cheng@mediatek.com>
11 - Chuanhong Guo <gch981213@gmail.com>
14 This spi controller support single, dual, or quad mode transfer for
15 SPI NOR flash. There should be only one spi slave device following
16 generic spi bindings. It's not recommended to use this controller
[all …]
H A Dcdns,xspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2020-21 Cadence
4 ---
5 $id: http://devicetree.org/schemas/spi/cdns,xspi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Parshuram Thombare <pthombar@cadence.com>
14 The XSPI controller allows SPI protocol communication in
16 read/write access to slaves such as SPI-NOR flash.
19 - $ref: spi-controller.yaml#
23 const: cdns,xspi-nor
[all …]
/openbmc/linux/Documentation/driver-api/mtd/
H A Dspi-nor.rst2 SPI NOR framework
5 Part I - Why do we need this framework?
6 ---------------------------------------
8 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
11 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
13 In particular, Freescale's QuadSPI controller must know the NOR commands to
14 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
15 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
18 details of the SPI NOR protocol.
20 Part II - How does the framework work?
[all …]
/openbmc/u-boot/drivers/mtd/spi/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0+
6 obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o
7 spi-nor-y := sf_probe.o spi-nor-ids.o
10 obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
12 spi-nor-y += spi-nor-tiny.o
14 spi-nor-y += spi-nor-core.o
17 spi-nor-y += spi-nor-core.o
20 obj-$(CONFIG_SPI_FLASH) += spi-nor.o
21 obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o sf.o
22 obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
[all …]
H A Dspi-nor-tiny.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/mtd/spi-nor.h>
21 #include <spi-mem.h>
22 #include <spi.h>
29 * For everything but full-chip erase; probably could be much smaller, but kept
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op in spi_nor_read_write_reg() argument
40 if (op->data.dir == SPI_MEM_DATA_IN) in spi_nor_read_write_reg()
41 op->data.buf.in = buf; in spi_nor_read_write_reg()
43 op->data.buf.out = buf; in spi_nor_read_write_reg()
44 return spi_mem_exec_op(nor->spi, op); in spi_nor_read_write_reg()
[all …]
H A Dspi-nor-core.c1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/mtd/spi-nor.h>
21 #include <spi-mem.h>
22 #include <spi.h>
29 * For everything but full-chip erase; probably could be much smaller, but kept
38 * spi_nor_setup_op() - Set up common properties of a spi-mem op.
39 * @nor: pointer to a 'struct spi_nor'
44 void spi_nor_setup_op(const struct spi_nor *nor, in spi_nor_setup_op() argument
48 op->cmd.buswidth = spi_nor_get_protocol_inst_nbits(proto); in spi_nor_setup_op()
50 if (op->addr.nbytes) in spi_nor_setup_op()
[all …]
/openbmc/linux/Documentation/ABI/testing/
H A Dsysfs-bus-spi-devices-spi-nor1 What: /sys/bus/spi/devices/.../spi-nor/jedec_id
4 Contact: linux-mtd@lists.infradead.org
5 Description: (RO) The JEDEC ID of the SPI NOR flash as reported by the
10 non-JEDEC compliant flashes.
12 What: /sys/bus/spi/devices/.../spi-nor/manufacturer
15 Contact: linux-mtd@lists.infradead.org
16 Description: (RO) Manufacturer of the SPI NOR flash.
22 What: /sys/bus/spi/devices/.../spi-nor/partname
25 Contact: linux-mtd@lists.infradead.org
26 Description: (RO) Part name of the SPI NOR flash.
[all …]
/openbmc/openbmc/meta-ampere/meta-jefferson/recipes-ampere/platform/ampere-utils/
H A Dampere_flash_bios.sh8 # $device_sellect : 1 - Host Main SPI Nor
9 # 2 - Host Second SPI Nor
14 # BMC_GPIOW6_SPI0_PROGRAM_SEL (GPIO 182): 1 => BMC owns SPI bus for upgrading
15 # 0 => HOST owns SPI bus for upgrading
17 # BMC_GPIOW7_SPI0_BACKUP_SEL (GPIO 183) : 0 => to switch SPI0_CS0_FL1_L to secondary SPI Nor d…
18 # 1 => to switch SPI0_CS0_FL0_L to primary SPI Nor dev…
25 HOST_MTD=$(< /proc/mtd grep "pnor" | sed -n 's/^\(.*\):.*/\1/p')
26 if [ -n "$HOST_MTD" ];
28 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/unbind
31 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/bind
[all …]
/openbmc/u-boot/include/linux/mtd/
H A Dspi-nor.h1 // SPDX-License-Identifier: GPL-2.0
23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro <--> Micron */
24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* ST Micro <--> Micron */
37 * requires a 4-byte (32-bit) address.
48 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
49 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
50 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
51 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
68 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
71 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
[all …]
/openbmc/openbmc/meta-ampere/meta-mitchell/recipes-ampere/platform/ampere-utils/
H A Dampere_flash_bios.sh8 # $device_sellect : 1 - Host Main SPI Nor
9 # 2 - Host Second SPI Nor
14 # BMC_GPIOW6_SPI0_PROGRAM_SEL (GPIO 182): 1 => BMC owns SPI bus for upgrading
15 # 0 => HOST owns SPI bus for upgrading
17 # BMC_GPIOW7_SPI0_BACKUP_SEL (GPIO 183) : 1 => to switch SPI_CS0_L to primary SPI Nor device
18 # 0 => to switch SPI_CS0_L to second SPI Nor device
26 HOST_MTD=$(< /proc/mtd grep "pnor" | sed -n 's/^\(.*\):.*/\1/p')
27 if [ -n "$HOST_MTD" ];
29 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/unbind
32 echo 1e630000.spi > /sys/bus/platform/drivers/spi-aspeed-smc/bind
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dhisilicon,fmc-spi-nor.txt1 HiSilicon SPI-NOR Flash Controller
4 - compatible : Should be "hisilicon,fmc-spi-nor" and one of the following strings:
5 "hisilicon,hi3519-spi-nor"
6 - address-cells : Should be 1.
7 - size-cells : Should be 0.
8 - reg : Offset and length of the register set for the controller device.
9 - reg-names : Must include the following two entries: "control", "memory".
10 - clocks : handle to spi-nor flash controller clock.
13 spi-nor-controller@10000000 {
14 compatible = "hisilicon,hi3519-spi-nor", "hisilicon,fmc-spi-nor";
[all …]
H A Djedec,spi-nor.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
10 - Rob Herring <robh@kernel.org>
13 - $ref: mtd.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
19 - items:
20 - pattern: "^((((micron|spansion|st),)?\
[all …]
/openbmc/linux/include/linux/mtd/
H A Dspi-nor.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <linux/spi/spi-mem.h>
18 * requires a 4-byte (32-bit) address.
30 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
31 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
32 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
33 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
34 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
35 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
53 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
[all …]
/openbmc/linux/drivers/mtd/spi-nor/controllers/
H A Dnxp-spifi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI NOR driver for NXP SPI Flash Interface (SPIFI)
18 #include <linux/mtd/spi-nor.h>
21 #include <linux/spi/spi.h>
58 struct spi_nor nor; member
68 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_wait_for_cmd()
71 dev_warn(spifi->dev, "command timed out\n"); in nxp_spifi_wait_for_cmd()
81 writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT); in nxp_spifi_reset()
82 ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat, in nxp_spifi_reset()
85 dev_warn(spifi->dev, "state reset timed out\n"); in nxp_spifi_reset()
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1088a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
21 bus-num = <0>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 compatible = "jedec,spi-nor";
29 spi-max-frequency = <1000000>;
33 #address-cells = <1>;
[all …]
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
/openbmc/u-boot/board/boundary/nitrogen6x/
H A DREADME.mx6qsabrelite1 U-Boot for the Freescale i.MX6q SabreLite board
4 This file contains information for the port of U-Boot to the Freescale
9 --------
11 To build U-Boot for the SabreLite board:
18 --------------------
20 The SabreLite boards boot from the SPI NOR flash. These boards need their SPI
22 board will still boot from SPI NOR, but the loader will in turn request the
23 BootROM to load the U-Boot from SD card.
29 This is provided under a open-source 3-clause BSD license.
31 To following procedure can be used to update the SPI-NOR on the SabreLite
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds.dtsi2 * MPC8536DS Device Tree Source stub (no addresses or top-level ranges)
13 * * Neither the name of Freescale Semiconductor nor the
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
41 bank-width = <2>;
42 device-width = <1>;
46 label = "ramdisk-nor";
51 label = "diagnostic-nor";
[all …]
/openbmc/u-boot/board/freescale/c29xpcie/
H A DREADME3 C29XPCIE board is a series of Freescale PCIe add-in cards to perform
6 The Freescale C29x family is a high performance crypto co-processor.
12 - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
13 - 64 Mbyte NOR flash single-chip memory
14 - 4 Gbyte NAND flash memory
15 - 1 Mbit AT24C1024 I2C EEPROM
16 - 16 Mbyte SPI memory
19 - 10/100/1000 BaseT Ethernet ports:
20 - eTSEC1, RGMII: one 10/100/1000 port
21 - eTSEC2, RGMII: one 10/100/1000 port
[all …]
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PA5 The P1010 is a cost-effective, low-power, highly integrated host processor
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
[all …]

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