1a0900d01SBoris Brezillon // SPDX-License-Identifier: GPL-2.0-only
2a0900d01SBoris Brezillon /*
31ac71ec0STudor Ambarus * SPI NOR driver for NXP SPI Flash Interface (SPIFI)
4a0900d01SBoris Brezillon *
5a0900d01SBoris Brezillon * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
6a0900d01SBoris Brezillon *
7a0900d01SBoris Brezillon * Based on Freescale QuadSPI driver:
8a0900d01SBoris Brezillon * Copyright (C) 2013 Freescale Semiconductor, Inc.
9a0900d01SBoris Brezillon */
10a0900d01SBoris Brezillon
11a0900d01SBoris Brezillon #include <linux/clk.h>
12a0900d01SBoris Brezillon #include <linux/err.h>
13a0900d01SBoris Brezillon #include <linux/io.h>
14a0900d01SBoris Brezillon #include <linux/iopoll.h>
15a0900d01SBoris Brezillon #include <linux/module.h>
16a0900d01SBoris Brezillon #include <linux/mtd/mtd.h>
17a0900d01SBoris Brezillon #include <linux/mtd/partitions.h>
18a0900d01SBoris Brezillon #include <linux/mtd/spi-nor.h>
19a0900d01SBoris Brezillon #include <linux/of.h>
20a0900d01SBoris Brezillon #include <linux/platform_device.h>
21a0900d01SBoris Brezillon #include <linux/spi/spi.h>
22a0900d01SBoris Brezillon
23a0900d01SBoris Brezillon /* NXP SPIFI registers, bits and macros */
24a0900d01SBoris Brezillon #define SPIFI_CTRL 0x000
25a0900d01SBoris Brezillon #define SPIFI_CTRL_TIMEOUT(timeout) (timeout)
26a0900d01SBoris Brezillon #define SPIFI_CTRL_CSHIGH(cshigh) ((cshigh) << 16)
27a0900d01SBoris Brezillon #define SPIFI_CTRL_MODE3 BIT(23)
28a0900d01SBoris Brezillon #define SPIFI_CTRL_DUAL BIT(28)
29a0900d01SBoris Brezillon #define SPIFI_CTRL_FBCLK BIT(30)
30a0900d01SBoris Brezillon #define SPIFI_CMD 0x004
31a0900d01SBoris Brezillon #define SPIFI_CMD_DATALEN(dlen) ((dlen) & 0x3fff)
32a0900d01SBoris Brezillon #define SPIFI_CMD_DOUT BIT(15)
33a0900d01SBoris Brezillon #define SPIFI_CMD_INTLEN(ilen) ((ilen) << 16)
34a0900d01SBoris Brezillon #define SPIFI_CMD_FIELDFORM(field) ((field) << 19)
35a0900d01SBoris Brezillon #define SPIFI_CMD_FIELDFORM_ALL_SERIAL SPIFI_CMD_FIELDFORM(0x0)
36a0900d01SBoris Brezillon #define SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA SPIFI_CMD_FIELDFORM(0x1)
37a0900d01SBoris Brezillon #define SPIFI_CMD_FRAMEFORM(frame) ((frame) << 21)
38a0900d01SBoris Brezillon #define SPIFI_CMD_FRAMEFORM_OPCODE_ONLY SPIFI_CMD_FRAMEFORM(0x1)
39a0900d01SBoris Brezillon #define SPIFI_CMD_OPCODE(op) ((op) << 24)
40a0900d01SBoris Brezillon #define SPIFI_ADDR 0x008
41a0900d01SBoris Brezillon #define SPIFI_IDATA 0x00c
42a0900d01SBoris Brezillon #define SPIFI_CLIMIT 0x010
43a0900d01SBoris Brezillon #define SPIFI_DATA 0x014
44a0900d01SBoris Brezillon #define SPIFI_MCMD 0x018
45a0900d01SBoris Brezillon #define SPIFI_STAT 0x01c
46a0900d01SBoris Brezillon #define SPIFI_STAT_MCINIT BIT(0)
47a0900d01SBoris Brezillon #define SPIFI_STAT_CMD BIT(1)
48a0900d01SBoris Brezillon #define SPIFI_STAT_RESET BIT(4)
49a0900d01SBoris Brezillon
50a0900d01SBoris Brezillon #define SPI_NOR_MAX_ID_LEN 6
51a0900d01SBoris Brezillon
52a0900d01SBoris Brezillon struct nxp_spifi {
53a0900d01SBoris Brezillon struct device *dev;
54a0900d01SBoris Brezillon struct clk *clk_spifi;
55a0900d01SBoris Brezillon struct clk *clk_reg;
56a0900d01SBoris Brezillon void __iomem *io_base;
57a0900d01SBoris Brezillon void __iomem *flash_base;
58a0900d01SBoris Brezillon struct spi_nor nor;
59a0900d01SBoris Brezillon bool memory_mode;
60a0900d01SBoris Brezillon u32 mcmd;
61a0900d01SBoris Brezillon };
62a0900d01SBoris Brezillon
nxp_spifi_wait_for_cmd(struct nxp_spifi * spifi)63a0900d01SBoris Brezillon static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi)
64a0900d01SBoris Brezillon {
65a0900d01SBoris Brezillon u8 stat;
66a0900d01SBoris Brezillon int ret;
67a0900d01SBoris Brezillon
68a0900d01SBoris Brezillon ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
69a0900d01SBoris Brezillon !(stat & SPIFI_STAT_CMD), 10, 30);
70a0900d01SBoris Brezillon if (ret)
71a0900d01SBoris Brezillon dev_warn(spifi->dev, "command timed out\n");
72a0900d01SBoris Brezillon
73a0900d01SBoris Brezillon return ret;
74a0900d01SBoris Brezillon }
75a0900d01SBoris Brezillon
nxp_spifi_reset(struct nxp_spifi * spifi)76a0900d01SBoris Brezillon static int nxp_spifi_reset(struct nxp_spifi *spifi)
77a0900d01SBoris Brezillon {
78a0900d01SBoris Brezillon u8 stat;
79a0900d01SBoris Brezillon int ret;
80a0900d01SBoris Brezillon
81a0900d01SBoris Brezillon writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
82a0900d01SBoris Brezillon ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
83a0900d01SBoris Brezillon !(stat & SPIFI_STAT_RESET), 10, 30);
84a0900d01SBoris Brezillon if (ret)
85a0900d01SBoris Brezillon dev_warn(spifi->dev, "state reset timed out\n");
86a0900d01SBoris Brezillon
87a0900d01SBoris Brezillon return ret;
88a0900d01SBoris Brezillon }
89a0900d01SBoris Brezillon
nxp_spifi_set_memory_mode_off(struct nxp_spifi * spifi)90a0900d01SBoris Brezillon static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi)
91a0900d01SBoris Brezillon {
92a0900d01SBoris Brezillon int ret;
93a0900d01SBoris Brezillon
94a0900d01SBoris Brezillon if (!spifi->memory_mode)
95a0900d01SBoris Brezillon return 0;
96a0900d01SBoris Brezillon
97a0900d01SBoris Brezillon ret = nxp_spifi_reset(spifi);
98a0900d01SBoris Brezillon if (ret)
99a0900d01SBoris Brezillon dev_err(spifi->dev, "unable to enter command mode\n");
100a0900d01SBoris Brezillon else
101a0900d01SBoris Brezillon spifi->memory_mode = false;
102a0900d01SBoris Brezillon
103a0900d01SBoris Brezillon return ret;
104a0900d01SBoris Brezillon }
105a0900d01SBoris Brezillon
nxp_spifi_set_memory_mode_on(struct nxp_spifi * spifi)106a0900d01SBoris Brezillon static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
107a0900d01SBoris Brezillon {
108a0900d01SBoris Brezillon u8 stat;
109a0900d01SBoris Brezillon int ret;
110a0900d01SBoris Brezillon
111a0900d01SBoris Brezillon if (spifi->memory_mode)
112a0900d01SBoris Brezillon return 0;
113a0900d01SBoris Brezillon
114a0900d01SBoris Brezillon writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
115a0900d01SBoris Brezillon ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
116a0900d01SBoris Brezillon stat & SPIFI_STAT_MCINIT, 10, 30);
117a0900d01SBoris Brezillon if (ret)
118a0900d01SBoris Brezillon dev_err(spifi->dev, "unable to enter memory mode\n");
119a0900d01SBoris Brezillon else
120a0900d01SBoris Brezillon spifi->memory_mode = true;
121a0900d01SBoris Brezillon
122a0900d01SBoris Brezillon return ret;
123a0900d01SBoris Brezillon }
124a0900d01SBoris Brezillon
nxp_spifi_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,size_t len)125a0900d01SBoris Brezillon static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
126a0900d01SBoris Brezillon size_t len)
127a0900d01SBoris Brezillon {
128a0900d01SBoris Brezillon struct nxp_spifi *spifi = nor->priv;
129a0900d01SBoris Brezillon u32 cmd;
130a0900d01SBoris Brezillon int ret;
131a0900d01SBoris Brezillon
132a0900d01SBoris Brezillon ret = nxp_spifi_set_memory_mode_off(spifi);
133a0900d01SBoris Brezillon if (ret)
134a0900d01SBoris Brezillon return ret;
135a0900d01SBoris Brezillon
136a0900d01SBoris Brezillon cmd = SPIFI_CMD_DATALEN(len) |
137a0900d01SBoris Brezillon SPIFI_CMD_OPCODE(opcode) |
138a0900d01SBoris Brezillon SPIFI_CMD_FIELDFORM_ALL_SERIAL |
139a0900d01SBoris Brezillon SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
140a0900d01SBoris Brezillon writel(cmd, spifi->io_base + SPIFI_CMD);
141a0900d01SBoris Brezillon
142a0900d01SBoris Brezillon while (len--)
143a0900d01SBoris Brezillon *buf++ = readb(spifi->io_base + SPIFI_DATA);
144a0900d01SBoris Brezillon
145a0900d01SBoris Brezillon return nxp_spifi_wait_for_cmd(spifi);
146a0900d01SBoris Brezillon }
147a0900d01SBoris Brezillon
nxp_spifi_write_reg(struct spi_nor * nor,u8 opcode,const u8 * buf,size_t len)148a0900d01SBoris Brezillon static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf,
149a0900d01SBoris Brezillon size_t len)
150a0900d01SBoris Brezillon {
151a0900d01SBoris Brezillon struct nxp_spifi *spifi = nor->priv;
152a0900d01SBoris Brezillon u32 cmd;
153a0900d01SBoris Brezillon int ret;
154a0900d01SBoris Brezillon
155a0900d01SBoris Brezillon ret = nxp_spifi_set_memory_mode_off(spifi);
156a0900d01SBoris Brezillon if (ret)
157a0900d01SBoris Brezillon return ret;
158a0900d01SBoris Brezillon
159a0900d01SBoris Brezillon cmd = SPIFI_CMD_DOUT |
160a0900d01SBoris Brezillon SPIFI_CMD_DATALEN(len) |
161a0900d01SBoris Brezillon SPIFI_CMD_OPCODE(opcode) |
162a0900d01SBoris Brezillon SPIFI_CMD_FIELDFORM_ALL_SERIAL |
163a0900d01SBoris Brezillon SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
164a0900d01SBoris Brezillon writel(cmd, spifi->io_base + SPIFI_CMD);
165a0900d01SBoris Brezillon
166a0900d01SBoris Brezillon while (len--)
167a0900d01SBoris Brezillon writeb(*buf++, spifi->io_base + SPIFI_DATA);
168a0900d01SBoris Brezillon
169a0900d01SBoris Brezillon return nxp_spifi_wait_for_cmd(spifi);
170a0900d01SBoris Brezillon }
171a0900d01SBoris Brezillon
nxp_spifi_read(struct spi_nor * nor,loff_t from,size_t len,u_char * buf)172a0900d01SBoris Brezillon static ssize_t nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len,
173a0900d01SBoris Brezillon u_char *buf)
174a0900d01SBoris Brezillon {
175a0900d01SBoris Brezillon struct nxp_spifi *spifi = nor->priv;
176a0900d01SBoris Brezillon int ret;
177a0900d01SBoris Brezillon
178a0900d01SBoris Brezillon ret = nxp_spifi_set_memory_mode_on(spifi);
179a0900d01SBoris Brezillon if (ret)
180a0900d01SBoris Brezillon return ret;
181a0900d01SBoris Brezillon
182a0900d01SBoris Brezillon memcpy_fromio(buf, spifi->flash_base + from, len);
183a0900d01SBoris Brezillon
184a0900d01SBoris Brezillon return len;
185a0900d01SBoris Brezillon }
186a0900d01SBoris Brezillon
nxp_spifi_write(struct spi_nor * nor,loff_t to,size_t len,const u_char * buf)187a0900d01SBoris Brezillon static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
188a0900d01SBoris Brezillon const u_char *buf)
189a0900d01SBoris Brezillon {
190a0900d01SBoris Brezillon struct nxp_spifi *spifi = nor->priv;
191a0900d01SBoris Brezillon u32 cmd;
192a0900d01SBoris Brezillon int ret;
193a0900d01SBoris Brezillon size_t i;
194a0900d01SBoris Brezillon
195a0900d01SBoris Brezillon ret = nxp_spifi_set_memory_mode_off(spifi);
196a0900d01SBoris Brezillon if (ret)
197a0900d01SBoris Brezillon return ret;
198a0900d01SBoris Brezillon
199a0900d01SBoris Brezillon writel(to, spifi->io_base + SPIFI_ADDR);
200a0900d01SBoris Brezillon
201a0900d01SBoris Brezillon cmd = SPIFI_CMD_DOUT |
202a0900d01SBoris Brezillon SPIFI_CMD_DATALEN(len) |
203a0900d01SBoris Brezillon SPIFI_CMD_FIELDFORM_ALL_SERIAL |
204a0900d01SBoris Brezillon SPIFI_CMD_OPCODE(nor->program_opcode) |
205a0900d01SBoris Brezillon SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
206c452d498STudor Ambarus writel(cmd, spifi->io_base + SPIFI_CMD);
207a0900d01SBoris Brezillon
208a0900d01SBoris Brezillon for (i = 0; i < len; i++)
209a0900d01SBoris Brezillon writeb(buf[i], spifi->io_base + SPIFI_DATA);
210a0900d01SBoris Brezillon
211a0900d01SBoris Brezillon ret = nxp_spifi_wait_for_cmd(spifi);
212a0900d01SBoris Brezillon if (ret)
213a0900d01SBoris Brezillon return ret;
214a0900d01SBoris Brezillon
215a0900d01SBoris Brezillon return len;
216a0900d01SBoris Brezillon }
217a0900d01SBoris Brezillon
nxp_spifi_erase(struct spi_nor * nor,loff_t offs)218a0900d01SBoris Brezillon static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
219a0900d01SBoris Brezillon {
220a0900d01SBoris Brezillon struct nxp_spifi *spifi = nor->priv;
221a0900d01SBoris Brezillon u32 cmd;
222a0900d01SBoris Brezillon int ret;
223a0900d01SBoris Brezillon
224a0900d01SBoris Brezillon ret = nxp_spifi_set_memory_mode_off(spifi);
225a0900d01SBoris Brezillon if (ret)
226a0900d01SBoris Brezillon return ret;
227a0900d01SBoris Brezillon
228a0900d01SBoris Brezillon writel(offs, spifi->io_base + SPIFI_ADDR);
229a0900d01SBoris Brezillon
230a0900d01SBoris Brezillon cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL |
231a0900d01SBoris Brezillon SPIFI_CMD_OPCODE(nor->erase_opcode) |
232a0900d01SBoris Brezillon SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
233c452d498STudor Ambarus writel(cmd, spifi->io_base + SPIFI_CMD);
234a0900d01SBoris Brezillon
235a0900d01SBoris Brezillon return nxp_spifi_wait_for_cmd(spifi);
236a0900d01SBoris Brezillon }
237a0900d01SBoris Brezillon
nxp_spifi_setup_memory_cmd(struct nxp_spifi * spifi)238a0900d01SBoris Brezillon static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
239a0900d01SBoris Brezillon {
240a0900d01SBoris Brezillon switch (spifi->nor.read_proto) {
241a0900d01SBoris Brezillon case SNOR_PROTO_1_1_1:
242a0900d01SBoris Brezillon spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
243a0900d01SBoris Brezillon break;
244a0900d01SBoris Brezillon case SNOR_PROTO_1_1_2:
245a0900d01SBoris Brezillon case SNOR_PROTO_1_1_4:
246a0900d01SBoris Brezillon spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
247a0900d01SBoris Brezillon break;
248a0900d01SBoris Brezillon default:
249a0900d01SBoris Brezillon dev_err(spifi->dev, "unsupported SPI read mode\n");
250a0900d01SBoris Brezillon return -EINVAL;
251a0900d01SBoris Brezillon }
252a0900d01SBoris Brezillon
253a0900d01SBoris Brezillon /* Memory mode supports address length between 1 and 4 */
254a0900d01SBoris Brezillon if (spifi->nor.addr_nbytes < 1 || spifi->nor.addr_nbytes > 4)
255c452d498STudor Ambarus return -EINVAL;
256a0900d01SBoris Brezillon
257a0900d01SBoris Brezillon spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |
258a0900d01SBoris Brezillon SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |
259a0900d01SBoris Brezillon SPIFI_CMD_FRAMEFORM(spifi->nor.addr_nbytes + 1);
260c452d498STudor Ambarus
261a0900d01SBoris Brezillon return 0;
262a0900d01SBoris Brezillon }
263a0900d01SBoris Brezillon
nxp_spifi_dummy_id_read(struct spi_nor * nor)264a0900d01SBoris Brezillon static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
265a0900d01SBoris Brezillon {
266a0900d01SBoris Brezillon u8 id[SPI_NOR_MAX_ID_LEN];
267a0900d01SBoris Brezillon nor->controller_ops->read_reg(nor, SPINOR_OP_RDID, id,
268a0900d01SBoris Brezillon SPI_NOR_MAX_ID_LEN);
269a0900d01SBoris Brezillon }
270a0900d01SBoris Brezillon
271a0900d01SBoris Brezillon static const struct spi_nor_controller_ops nxp_spifi_controller_ops = {
272a0900d01SBoris Brezillon .read_reg = nxp_spifi_read_reg,
273a0900d01SBoris Brezillon .write_reg = nxp_spifi_write_reg,
274a0900d01SBoris Brezillon .read = nxp_spifi_read,
275a0900d01SBoris Brezillon .write = nxp_spifi_write,
276a0900d01SBoris Brezillon .erase = nxp_spifi_erase,
277a0900d01SBoris Brezillon };
278a0900d01SBoris Brezillon
nxp_spifi_setup_flash(struct nxp_spifi * spifi,struct device_node * np)279a0900d01SBoris Brezillon static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
280a0900d01SBoris Brezillon struct device_node *np)
281a0900d01SBoris Brezillon {
282a0900d01SBoris Brezillon struct spi_nor_hwcaps hwcaps = {
283a0900d01SBoris Brezillon .mask = SNOR_HWCAPS_READ |
284a0900d01SBoris Brezillon SNOR_HWCAPS_READ_FAST |
285a0900d01SBoris Brezillon SNOR_HWCAPS_PP,
286a0900d01SBoris Brezillon };
287a0900d01SBoris Brezillon u32 ctrl, property;
288a0900d01SBoris Brezillon u16 mode = 0;
289a0900d01SBoris Brezillon int ret;
290a0900d01SBoris Brezillon
291a0900d01SBoris Brezillon if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {
292a0900d01SBoris Brezillon switch (property) {
293a0900d01SBoris Brezillon case 1:
294a0900d01SBoris Brezillon break;
295a0900d01SBoris Brezillon case 2:
296a0900d01SBoris Brezillon mode |= SPI_RX_DUAL;
297a0900d01SBoris Brezillon break;
298a0900d01SBoris Brezillon case 4:
299a0900d01SBoris Brezillon mode |= SPI_RX_QUAD;
300a0900d01SBoris Brezillon break;
301a0900d01SBoris Brezillon default:
302a0900d01SBoris Brezillon dev_err(spifi->dev, "unsupported rx-bus-width\n");
303a0900d01SBoris Brezillon return -EINVAL;
304a0900d01SBoris Brezillon }
305a0900d01SBoris Brezillon }
306a0900d01SBoris Brezillon
307a0900d01SBoris Brezillon if (of_property_read_bool(np, "spi-cpha"))
30857150c40SRob Herring mode |= SPI_CPHA;
309a0900d01SBoris Brezillon
310a0900d01SBoris Brezillon if (of_property_read_bool(np, "spi-cpol"))
31157150c40SRob Herring mode |= SPI_CPOL;
312a0900d01SBoris Brezillon
313a0900d01SBoris Brezillon /* Setup control register defaults */
314a0900d01SBoris Brezillon ctrl = SPIFI_CTRL_TIMEOUT(1000) |
315a0900d01SBoris Brezillon SPIFI_CTRL_CSHIGH(15) |
316a0900d01SBoris Brezillon SPIFI_CTRL_FBCLK;
317a0900d01SBoris Brezillon
318a0900d01SBoris Brezillon if (mode & SPI_RX_DUAL) {
319a0900d01SBoris Brezillon ctrl |= SPIFI_CTRL_DUAL;
320a0900d01SBoris Brezillon hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
321a0900d01SBoris Brezillon } else if (mode & SPI_RX_QUAD) {
322a0900d01SBoris Brezillon ctrl &= ~SPIFI_CTRL_DUAL;
323a0900d01SBoris Brezillon hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
324a0900d01SBoris Brezillon } else {
325a0900d01SBoris Brezillon ctrl |= SPIFI_CTRL_DUAL;
326a0900d01SBoris Brezillon }
327a0900d01SBoris Brezillon
328a0900d01SBoris Brezillon switch (mode & SPI_MODE_X_MASK) {
3295c26d52cSAndy Shevchenko case SPI_MODE_0:
330a0900d01SBoris Brezillon ctrl &= ~SPIFI_CTRL_MODE3;
331a0900d01SBoris Brezillon break;
332a0900d01SBoris Brezillon case SPI_MODE_3:
333a0900d01SBoris Brezillon ctrl |= SPIFI_CTRL_MODE3;
334a0900d01SBoris Brezillon break;
335a0900d01SBoris Brezillon default:
336a0900d01SBoris Brezillon dev_err(spifi->dev, "only mode 0 and 3 supported\n");
337a0900d01SBoris Brezillon return -EINVAL;
338a0900d01SBoris Brezillon }
339a0900d01SBoris Brezillon
340a0900d01SBoris Brezillon writel(ctrl, spifi->io_base + SPIFI_CTRL);
341a0900d01SBoris Brezillon
342a0900d01SBoris Brezillon spifi->nor.dev = spifi->dev;
343a0900d01SBoris Brezillon spi_nor_set_flash_node(&spifi->nor, np);
344a0900d01SBoris Brezillon spifi->nor.priv = spifi;
345a0900d01SBoris Brezillon spifi->nor.controller_ops = &nxp_spifi_controller_ops;
346a0900d01SBoris Brezillon
347a0900d01SBoris Brezillon /*
348a0900d01SBoris Brezillon * The first read on a hard reset isn't reliable so do a
349a0900d01SBoris Brezillon * dummy read of the id before calling spi_nor_scan().
350a0900d01SBoris Brezillon * The reason for this problem is unknown.
351a0900d01SBoris Brezillon *
352a0900d01SBoris Brezillon * The official NXP spifilib uses more or less the same
353a0900d01SBoris Brezillon * workaround that is applied here by reading the device
354a0900d01SBoris Brezillon * id multiple times.
355a0900d01SBoris Brezillon */
356a0900d01SBoris Brezillon nxp_spifi_dummy_id_read(&spifi->nor);
357a0900d01SBoris Brezillon
358a0900d01SBoris Brezillon ret = spi_nor_scan(&spifi->nor, NULL, &hwcaps);
359a0900d01SBoris Brezillon if (ret) {
360a0900d01SBoris Brezillon dev_err(spifi->dev, "device scan failed\n");
361a0900d01SBoris Brezillon return ret;
362a0900d01SBoris Brezillon }
363a0900d01SBoris Brezillon
364a0900d01SBoris Brezillon ret = nxp_spifi_setup_memory_cmd(spifi);
365a0900d01SBoris Brezillon if (ret) {
366a0900d01SBoris Brezillon dev_err(spifi->dev, "memory command setup failed\n");
367a0900d01SBoris Brezillon return ret;
368a0900d01SBoris Brezillon }
369a0900d01SBoris Brezillon
370a0900d01SBoris Brezillon ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
371a0900d01SBoris Brezillon if (ret) {
372a0900d01SBoris Brezillon dev_err(spifi->dev, "mtd device parse failed\n");
373a0900d01SBoris Brezillon return ret;
374a0900d01SBoris Brezillon }
375a0900d01SBoris Brezillon
376a0900d01SBoris Brezillon return 0;
377a0900d01SBoris Brezillon }
378a0900d01SBoris Brezillon
nxp_spifi_probe(struct platform_device * pdev)379a0900d01SBoris Brezillon static int nxp_spifi_probe(struct platform_device *pdev)
380a0900d01SBoris Brezillon {
381a0900d01SBoris Brezillon struct device_node *flash_np;
382a0900d01SBoris Brezillon struct nxp_spifi *spifi;
383a0900d01SBoris Brezillon int ret;
384a0900d01SBoris Brezillon
385a0900d01SBoris Brezillon spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);
386a0900d01SBoris Brezillon if (!spifi)
387a0900d01SBoris Brezillon return -ENOMEM;
388a0900d01SBoris Brezillon
389a0900d01SBoris Brezillon spifi->io_base = devm_platform_ioremap_resource_byname(pdev, "spifi");
390df872ab1SCai Huoqing if (IS_ERR(spifi->io_base))
391a0900d01SBoris Brezillon return PTR_ERR(spifi->io_base);
392a0900d01SBoris Brezillon
393a0900d01SBoris Brezillon spifi->flash_base = devm_platform_ioremap_resource_byname(pdev, "flash");
394df872ab1SCai Huoqing if (IS_ERR(spifi->flash_base))
395a0900d01SBoris Brezillon return PTR_ERR(spifi->flash_base);
396a0900d01SBoris Brezillon
397a0900d01SBoris Brezillon spifi->clk_spifi = devm_clk_get_enabled(&pdev->dev, "spifi");
398*69d50d04SLi Zetao if (IS_ERR(spifi->clk_spifi)) {
399a0900d01SBoris Brezillon dev_err(&pdev->dev, "spifi clock not found or unable to enable\n");
400*69d50d04SLi Zetao return PTR_ERR(spifi->clk_spifi);
401a0900d01SBoris Brezillon }
402a0900d01SBoris Brezillon
403a0900d01SBoris Brezillon spifi->clk_reg = devm_clk_get_enabled(&pdev->dev, "reg");
404*69d50d04SLi Zetao if (IS_ERR(spifi->clk_reg)) {
405a0900d01SBoris Brezillon dev_err(&pdev->dev, "reg clock not found or unable to enable\n");
406*69d50d04SLi Zetao return PTR_ERR(spifi->clk_reg);
407a0900d01SBoris Brezillon }
408a0900d01SBoris Brezillon
409a0900d01SBoris Brezillon spifi->dev = &pdev->dev;
410a0900d01SBoris Brezillon platform_set_drvdata(pdev, spifi);
411a0900d01SBoris Brezillon
412a0900d01SBoris Brezillon /* Initialize and reset device */
413a0900d01SBoris Brezillon nxp_spifi_reset(spifi);
414a0900d01SBoris Brezillon writel(0, spifi->io_base + SPIFI_IDATA);
415a0900d01SBoris Brezillon writel(0, spifi->io_base + SPIFI_MCMD);
416a0900d01SBoris Brezillon nxp_spifi_reset(spifi);
417a0900d01SBoris Brezillon
418a0900d01SBoris Brezillon flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
419a0900d01SBoris Brezillon if (!flash_np) {
420a0900d01SBoris Brezillon dev_err(&pdev->dev, "no SPI flash device to configure\n");
421a0900d01SBoris Brezillon return -ENODEV;
422*69d50d04SLi Zetao }
423a0900d01SBoris Brezillon
424a0900d01SBoris Brezillon ret = nxp_spifi_setup_flash(spifi, flash_np);
425a0900d01SBoris Brezillon of_node_put(flash_np);
426a0900d01SBoris Brezillon if (ret) {
427a0900d01SBoris Brezillon dev_err(&pdev->dev, "unable to setup flash chip\n");
428a0900d01SBoris Brezillon return ret;
429*69d50d04SLi Zetao }
430a0900d01SBoris Brezillon
431a0900d01SBoris Brezillon return 0;
432a0900d01SBoris Brezillon }
433a0900d01SBoris Brezillon
nxp_spifi_remove(struct platform_device * pdev)434a0900d01SBoris Brezillon static int nxp_spifi_remove(struct platform_device *pdev)
435a0900d01SBoris Brezillon {
436a0900d01SBoris Brezillon struct nxp_spifi *spifi = platform_get_drvdata(pdev);
437a0900d01SBoris Brezillon
438a0900d01SBoris Brezillon mtd_device_unregister(&spifi->nor.mtd);
439a0900d01SBoris Brezillon
440a0900d01SBoris Brezillon return 0;
441a0900d01SBoris Brezillon }
442a0900d01SBoris Brezillon
443a0900d01SBoris Brezillon static const struct of_device_id nxp_spifi_match[] = {
444a0900d01SBoris Brezillon {.compatible = "nxp,lpc1773-spifi"},
445a0900d01SBoris Brezillon { /* sentinel */ }
446a0900d01SBoris Brezillon };
447a0900d01SBoris Brezillon MODULE_DEVICE_TABLE(of, nxp_spifi_match);
448a0900d01SBoris Brezillon
449a0900d01SBoris Brezillon static struct platform_driver nxp_spifi_driver = {
450a0900d01SBoris Brezillon .probe = nxp_spifi_probe,
451a0900d01SBoris Brezillon .remove = nxp_spifi_remove,
452a0900d01SBoris Brezillon .driver = {
453a0900d01SBoris Brezillon .name = "nxp-spifi",
454a0900d01SBoris Brezillon .of_match_table = nxp_spifi_match,
455a0900d01SBoris Brezillon },
456a0900d01SBoris Brezillon };
457a0900d01SBoris Brezillon module_platform_driver(nxp_spifi_driver);
458a0900d01SBoris Brezillon
459a0900d01SBoris Brezillon MODULE_DESCRIPTION("NXP SPI Flash Interface driver");
460a0900d01SBoris Brezillon MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
461a0900d01SBoris Brezillon MODULE_LICENSE("GPL v2");
462a0900d01SBoris Brezillon