spi: Add usage example for write protect APIs

Implement the demostration scenario for command filter
and write address filter APIs.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Chang

spi: Add usage example for write protect APIs

Implement the demostration scenario for command filter
and write address filter APIs.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: Ia1e67aa222925a711e98148ccbf37741d7ae7812

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spi-nor: Disable hold/reset pin on MT25QL02G

Disable hold/reset pin function on MT25QL02G flash part.
If QSPI mode is used and the IO rising time is not good,
the flash will be in hold/reset status

spi-nor: Disable hold/reset pin on MT25QL02G

Disable hold/reset pin function on MT25QL02G flash part.
If QSPI mode is used and the IO rising time is not good,
the flash will be in hold/reset status when the next QSPI
command is sent.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I39a7b043b6c122b1bf40ce9a29e3202f3ce536ef

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spi-nor: Add fast read command for S25HL series flash support

Support fast read command, 0Ch, for S25HL series flash parts.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I1

spi-nor: Add fast read command for S25HL series flash support

Support fast read command, 0Ch, for S25HL series flash parts.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I1d99fe451f5d9c2a3545ffb0c52c003d1aeda746

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mtd: spi: Support Gigadevice device with 64KB sector size

When DWORD15[22:20] = 3b'111, QE bit is not supported.
Thus, no callback function should be added for quad_enable.

Signed-off-by: Chin-Ting

mtd: spi: Support Gigadevice device with 64KB sector size

When DWORD15[22:20] = 3b'111, QE bit is not supported.
Thus, no callback function should be added for quad_enable.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I0c9aa8df38ed2997fdb3f74275330969f277be9e

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spi_nor: Support s25hl without SFDP

Porting S25HL flash series when SFDP is disabled.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I59e3951cde913570e6e93ba8d9832a0bd10da462

spi-nor: Porting for S25HL series

Add Cypress S25HL series flash.
Sync code base from u-boot mainline.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I10a0d6d51f2500696b7c0a

spi-nor: Porting for S25HL series

Add Cypress S25HL series flash.
Sync code base from u-boot mainline.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I10a0d6d51f2500696b7c0abc41e935fda90321f0

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spi-nor: Add QE bit setting function for GD25Q256E

QE bit is located in status register 2 of GD25Q256E,
The setting method of status register 2 is different
from Winbond (using 01h command). Thus, a

spi-nor: Add QE bit setting function for GD25Q256E

QE bit is located in status register 2 of GD25Q256E,
The setting method of status register 2 is different
from Winbond (using 01h command). Thus, a new setting
function is needed.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I9a48a2be5eed505502296cbdc7bf0b5e56291614

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spi-nor: Porting MT25Q02G flash part

Due to bad raising timing, hold/reset pin feature should
be disabled if quad mode is enabled. Otherwise, flash will
be hold when command is send

spi-nor: Porting MT25Q02G flash part

Due to bad raising timing, hold/reset pin feature should
be disabled if quad mode is enabled. Otherwise, flash will
be hold when command is send to flash.

Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Change-Id: I82e91646097822793c53dcf896c43ce26756acbb

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Merge branch 'aspeed-master-v2019.04-github' into aspeed-master-v2019.04

spi-nor: Add support for Cypress s25hl-t/s25hs-t

Only support 1-1-1 SPI write format.

spi-nor: Porting 2Gb flashes

- Enable SFDP parser on AST2600 defconfig.
- Don't support 1-4-4, 1-2-2 SPI format.

spi-nor: ISSI flash model support

Support ISSI flash models, is25lp256 and is25lp512m.

Merge branch 'ryan_port' into aspeed-dev-v2019.04

spi-nor: GigaDevice flash support

- Add GigaDevice flash into flash ids.
- Send B7h command for entering 4-byte mode for
GigaDevice flash.

Merge branch 'ryan_port' into aspeed-dev-v2019.04

update for 4 byte opcodes transfer

fix spi issue

Merge branch 'master' of git://git.denx.de/u-boot-spi

- SPI-NOR support

mtd: spi: Add lightweight SPI flash stack for SPL

Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constrain

mtd: spi: Add lightweight SPI flash stack for SPL

Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.

Based on prior work of reducing spi flash id table by
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

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mtd: spi: Switch to new SPI NOR framework

Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to

mtd: spi: Switch to new SPI NOR framework

Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

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mtd: spi: spi-nor-core: Add back U-Boot specific features

For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framewor

mtd: spi: spi-nor-core: Add back U-Boot specific features

For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

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mtd: spi: spi-nor-core: Add SFDP support

Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.

mtd: spi: spi-nor-core: Add SFDP support

Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

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mtd: spi: spi-nor-core: Add 4 Byte addressing support

Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x

mtd: spi: spi-nor-core: Add 4 Byte addressing support

Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

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mtd: spi: spi-nor-core: Add SPI MEM support

Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to

mtd: spi: spi-nor-core: Add SPI MEM support

Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

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mtd: spi: Port SPI NOR framework from Linux

Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different

mtd: spi: Port SPI NOR framework from Linux

Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed

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