/openbmc/linux/drivers/net/phy/ |
H A D | mediatek-ge-soc.c | 351 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, in cal_cycle() 561 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, in tx_vcm_cal_sw() 568 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw() 571 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw() 579 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw() 582 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw() 590 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw() 593 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw() 601 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw() 604 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tx_vcm_cal_sw() [all …]
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H A D | adin1100.c | 105 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_B10L_PMA_CTRL, in adin_config_aneg() 114 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, ADIN_FORCED_MODE, ADIN_FORCED_MODE_EN); in adin_config_aneg() 129 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, in adin_config_aneg() 172 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_10T1L_CTRL, in adin_set_loopback()
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H A D | nxp-c45-tja11xx.c | 659 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S, in tja1120_get_hwtxts() 827 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling() 847 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling() 856 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling() 1225 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr() 1251 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr() 1356 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_get_status() 1358 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_get_status() 1385 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify() 1445 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE); in nxp_c45_disable_delays() [all …]
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H A D | mediatek-ge.c | 62 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300); in mt7531_phy_config_init()
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H A D | dp83822.c | 177 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, in dp83822_set_wol() 329 return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, in dp8382x_disable_wol() 415 err = phy_clear_bits_mmd(phydev, DP83822_DEVADDR, in dp83822_config_init()
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H A D | dp83tc811.c | 151 return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, in dp83811_set_wol() 350 return phy_clear_bits_mmd(phydev, DP83811_DEVADDR, MII_DP83811_WOL_CFG, in dp83811_config_init()
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H A D | phy-c45.c | 56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume() 325 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg() 1167 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain() 1262 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
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H A D | dp83td510.c | 78 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in dp83td510_config_intr()
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H A D | marvell10g.c | 328 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MV_V2_PORT_CTRL, in mv3310_power_up() 392 return phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_PCS_DSC1, in mv3310_set_downshift() 637 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, MV_AN_21X0_SERDES_CTRL2, in mv2110_set_mactype() 1336 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in mv3110_set_wol()
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H A D | marvell-88x2222.c | 65 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, in mv2222_tx_enable() 92 int ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PCS, MV_1GBX_CTRL, in mv2222_disable_aneg()
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H A D | adin.c | 260 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rgmii_mode() 306 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in adin_config_rmii_mode()
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H A D | micrel.c | 4255 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin)); in lan8841_ptp_perout_off() 4259 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin)); in lan8841_ptp_perout_off() 4263 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin)); in lan8841_ptp_perout_off() 4308 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp); in lan8841_ptp_remove_event() 4311 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp); in lan8841_ptp_remove_event() 4323 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp); in lan8841_ptp_remove_event() 4521 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin)); in lan8841_ptp_extts_on() 4546 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin)); in lan8841_ptp_extts_off() 4550 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin)); in lan8841_ptp_extts_off()
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H A D | dp83867.c | 486 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_port_mirroring() 760 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, in dp83867_config_init()
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H A D | dp83869.c | 504 return phy_clear_bits_mmd(phydev, DP83869_DEVADDR, in dp83869_config_port_mirroring()
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H A D | aquantia_main.c | 706 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, in aqr107_resume()
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H A D | mxl-gpy.c | 739 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in gpy_set_wol()
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/openbmc/linux/include/linux/ |
H A D | phy.h | 1494 static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad, in phy_clear_bits_mmd() function
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