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Searched refs:gmu (Results 1 – 25 of 35) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.c19 static void a6xx_gmu_fault(struct a6xx_gmu *gmu) in a6xx_gmu_fault() argument
21 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fault()
26 gmu->hung = true; in a6xx_gmu_fault()
37 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
40 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
41 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
44 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
46 a6xx_gmu_fault(gmu); in a6xx_gmu_irq()
50 dev_err_ratelimited(gmu in a6xx_gmu_irq()
61 struct a6xx_gmu *gmu = data; a6xx_hfi_irq() local
76 a6xx_gmu_sptprac_is_on(struct a6xx_gmu * gmu) a6xx_gmu_sptprac_is_on() argument
92 a6xx_gmu_gx_is_on(struct a6xx_gmu * gmu) a6xx_gmu_gx_is_on() argument
112 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_set_freq() local
172 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_get_freq() local
177 a6xx_gmu_check_idle_level(struct a6xx_gmu * gmu) a6xx_gmu_check_idle_level() argument
198 a6xx_gmu_wait_for_idle(struct a6xx_gmu * gmu) a6xx_gmu_wait_for_idle() argument
203 a6xx_gmu_start(struct a6xx_gmu * gmu) a6xx_gmu_start() argument
236 a6xx_gmu_hfi_start(struct a6xx_gmu * gmu) a6xx_gmu_hfi_start() argument
296 a6xx_gmu_set_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state) a6xx_gmu_set_oob() argument
341 a6xx_gmu_clear_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state) a6xx_gmu_clear_oob() argument
359 a6xx_sptprac_enable(struct a6xx_gmu * gmu) a6xx_sptprac_enable() argument
381 a6xx_sptprac_disable(struct a6xx_gmu * gmu) a6xx_sptprac_disable() argument
403 a6xx_gmu_gfx_rail_on(struct a6xx_gmu * gmu) a6xx_gmu_gfx_rail_on() argument
421 a6xx_gmu_notify_slumber(struct a6xx_gmu * gmu) a6xx_gmu_notify_slumber() argument
458 a6xx_rpmh_start(struct a6xx_gmu * gmu) a6xx_rpmh_start() argument
487 a6xx_rpmh_stop(struct a6xx_gmu * gmu) a6xx_rpmh_stop() argument
510 a6xx_gmu_rpmh_init(struct a6xx_gmu * gmu) a6xx_gmu_rpmh_init() argument
638 a6xx_gmu_power_config(struct a6xx_gmu * gmu) a6xx_gmu_power_config() argument
690 a6xx_gmu_fw_load(struct a6xx_gmu * gmu) a6xx_gmu_fw_load() argument
746 a6xx_gmu_fw_start(struct a6xx_gmu * gmu,unsigned int state) a6xx_gmu_fw_start() argument
849 a6xx_gmu_irq_disable(struct a6xx_gmu * gmu) a6xx_gmu_irq_disable() argument
858 a6xx_gmu_rpmh_off(struct a6xx_gmu * gmu) a6xx_gmu_rpmh_off() argument
874 a6xx_gmu_force_off(struct a6xx_gmu * gmu) a6xx_gmu_force_off() argument
914 a6xx_gmu_set_initial_freq(struct msm_gpu * gpu,struct a6xx_gmu * gmu) a6xx_gmu_set_initial_freq() argument
928 a6xx_gmu_set_initial_bw(struct msm_gpu * gpu,struct a6xx_gmu * gmu) a6xx_gmu_set_initial_bw() argument
945 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_resume() local
1024 a6xx_gmu_isidle(struct a6xx_gmu * gmu) a6xx_gmu_isidle() argument
1040 a6xx_gmu_shutdown(struct a6xx_gmu * gmu) a6xx_gmu_shutdown() argument
1102 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_stop() local
1135 a6xx_gmu_memory_free(struct a6xx_gmu * gmu) a6xx_gmu_memory_free() argument
1148 a6xx_gmu_memory_alloc(struct a6xx_gmu * gmu,struct a6xx_gmu_bo * bo,size_t size,u64 iova,const char * name) a6xx_gmu_memory_alloc() argument
1189 a6xx_gmu_memory_probe(struct a6xx_gmu * gmu) a6xx_gmu_memory_probe() argument
1305 a6xx_gmu_rpmh_votes_init(struct a6xx_gmu * gmu) a6xx_gmu_rpmh_votes_init() argument
1355 a6xx_gmu_pwrlevels_probe(struct a6xx_gmu * gmu) a6xx_gmu_pwrlevels_probe() argument
1389 a6xx_gmu_clocks_probe(struct a6xx_gmu * gmu) a6xx_gmu_clocks_probe() argument
1428 a6xx_gmu_get_irq(struct a6xx_gmu * gmu,struct platform_device * pdev,const char * name,irq_handler_t handler) a6xx_gmu_get_irq() argument
1448 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_remove() local
1494 struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb); cxpd_notifier_cb() local
1505 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_wrapper_init() local
1568 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; a6xx_gmu_init() local
[all...]
H A Da6xx_hfi.c26 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
57 if (!gmu->legacy) in a6xx_hfi_queue_read()
64 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
88 if (!gmu->legacy) { in a6xx_hfi_queue_write()
96 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
100 static int a6xx_hfi_wait_for_ack(struct a6xx_gmu *gmu, u32 id, u32 seqnum, in a6xx_hfi_wait_for_ack() argument
103 struct a6xx_hfi_queue *queue = &gmu->queues[HFI_RESPONSE_QUEUE]; in a6xx_hfi_wait_for_ack()
108 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_ack()
112 DRM_DEV_ERROR(gmu->dev, in a6xx_hfi_wait_for_ack()
119 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, in a6xx_hfi_wait_for_ack()
[all …]
H A Da6xx_gmu.h101 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset) in gmu_read() argument
103 return msm_readl(gmu->mmio + (offset << 2)); in gmu_read()
106 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value) in gmu_write() argument
108 msm_writel(value, gmu->mmio + (offset << 2)); in gmu_write()
112 gmu_write_bulk(struct a6xx_gmu *gmu, u32 offset, const u32 *data, u32 size) in gmu_write_bulk() argument
114 memcpy_toio(gmu->mmio + (offset << 2), data, size); in gmu_write_bulk()
118 static inline void gmu_rmw(struct a6xx_gmu *gmu, u32 reg, u32 mask, u32 or) in gmu_rmw() argument
120 u32 val = gmu_read(gmu, reg); in gmu_rmw()
124 gmu_write(gmu, reg, val | or); in gmu_rmw()
127 static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi) in gmu_read64() argument
[all …]
H A Da6xx_gpu.c24 if (!adreno_has_gmu_wrapper(adreno_gpu) && !a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a6xx_check_idle()
702 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_set_hwcg() local
725 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); in a6xx_set_hwcg()
732 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); in a6xx_set_hwcg()
1199 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
1204 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
1225 a6xx_sptprac_enable(gmu); in hw_init()
1359 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000); in hw_init()
1362 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, BIT(5)); in hw_init()
1363 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); in hw_init()
[all …]
H A Da6xx_gpu.h23 struct a6xx_gmu gmu; member
86 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
88 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
90 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
91 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
H A Da6xx_gpu_state.c144 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
784 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
804 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
806 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
833 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
871 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
874 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
876 for (i = 0; i < ARRAY_SIZE(gmu->queues); i++) { in a6xx_snapshot_gmu_hfi_history()
877 struct a6xx_hfi_queue *queue = &gmu->queues[i]; in a6xx_snapshot_gmu_hfi_history()
1047 a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log); in a6xx_gpu_state_get()
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992.dtsi31 gmu-sram@0 {
H A Dsm6350.dtsi1338 qcom,gmu = <&gmu>;
1421 gmu: gmu@3d6a000 { label
1422 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu";
1426 reg-names = "gmu",
1433 "gmu";
1441 "gmu",
H A Dsc8180x.dtsi2181 qcom,gmu = <&gmu>;
2224 gmu: gmu@2c6a000 { label
2225 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2230 reg-names = "gmu",
2236 interrupt-names = "hfi", "gmu";
2243 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsm8350.dtsi1852 qcom,gmu = <&gmu>;
1916 gmu: gmu@3d6a000 { label
1917 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
1922 reg-names = "gmu", "rscc", "gmu_pdc";
1926 interrupt-names = "hfi", "gmu";
1935 clock-names = "gmu",
H A Dsm8150.dtsi2221 qcom,gmu = <&gmu>;
2273 gmu: gmu@2c6a000 { label
2274 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
2279 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2283 interrupt-names = "hfi", "gmu";
2290 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsc7180.dtsi2094 qcom,gmu = <&gmu>;
2188 gmu: gmu@506a000 { label
2189 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2192 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2195 interrupt-names = "hfi", "gmu";
2200 clock-names = "gmu", "cxo", "axi", "memnoc";
H A Dsm8250-hdk.dts368 &gmu {
H A Dsm8150-hdk.dts362 &gmu {
H A Dsm8150-mtp.dts353 &gmu {
H A Dsm6115.dtsi1353 "gmu",
1361 qcom,gmu = <&gmu_wrapper>;
1426 gmu_wrapper: gmu@596a000 {
1427 compatible = "qcom,adreno-gmu-wrapper";
1429 reg-names = "gmu";
H A Dsdm845.dtsi4764 qcom,gmu = <&gmu>;
4840 gmu: gmu@506a000 { label
4841 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4846 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4850 interrupt-names = "hfi", "gmu";
4856 clock-names = "gmu", "cxo", "axi", "memnoc";
H A Dsc8280xp.dtsi2369 qcom,gmu = <&gmu>;
2429 gmu: gmu@3d6a000 { label
2430 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2434 reg-names = "gmu", "rscc", "gmu_pdc";
2437 interrupt-names = "hfi", "gmu";
2445 clock-names = "gmu",
H A Dsdm845-xiaomi-beryllium-common.dtsi242 &gmu {
H A Dsc7280.dtsi2574 qcom,gmu = <&gmu>;
2651 gmu: gmu@3d6a000 { label
2652 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2656 reg-names = "gmu", "rscc", "gmu_pdc";
2659 interrupt-names = "hfi", "gmu";
2667 clock-names = "gmu",
H A Dsm8250.dtsi2597 qcom,gmu = <&gmu>;
2655 gmu: gmu@3d6a000 { label
2656 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
2662 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
2666 interrupt-names = "hfi", "gmu";
2673 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsdm845-mtp.dts429 &gmu {
H A Dsdm845-xiaomi-polaris.dts384 &gmu {
H A Dsdm845-shift-axolotl.dts422 &gmu {
H A Dsdm850-lenovo-yoga-c630.dts358 &gmu {

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