1e13c6d14SVinod Koul// SPDX-License-Identifier: BSD-3-Clause 2e13c6d14SVinod Koul/* 3e13c6d14SVinod Koul * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4e13c6d14SVinod Koul * Copyright (c) 2019, Linaro Limited 5e13c6d14SVinod Koul */ 6e13c6d14SVinod Koul 705006290SFelipe Balbi#include <dt-bindings/dma/qcom-gpi.h> 8e13c6d14SVinod Koul#include <dt-bindings/interrupt-controller/arm-gic.h> 9017e7856SSibi Sankar#include <dt-bindings/power/qcom-rpmpd.h> 10e13c6d14SVinod Koul#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11e13c6d14SVinod Koul#include <dt-bindings/clock/qcom,rpmh.h> 1298874a46SKonrad Dybcio#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 13d6f55763SVinod Koul#include <dt-bindings/clock/qcom,gcc-sm8150.h> 14f1269916SJonathan Marek#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 15a6d435c1SSibi Sankar#include <dt-bindings/interconnect/qcom,osm-l3.h> 162b6187abSThara Gopinath#include <dt-bindings/interconnect/qcom,sm8150.h> 17d2fa630cSAmit Kucheria#include <dt-bindings/thermal/thermal.h> 18e13c6d14SVinod Koul 19e13c6d14SVinod Koul/ { 20e13c6d14SVinod Koul interrupt-parent = <&intc>; 21e13c6d14SVinod Koul 22e13c6d14SVinod Koul #address-cells = <2>; 23e13c6d14SVinod Koul #size-cells = <2>; 24e13c6d14SVinod Koul 25e13c6d14SVinod Koul chosen { }; 26e13c6d14SVinod Koul 27e13c6d14SVinod Koul clocks { 28e13c6d14SVinod Koul xo_board: xo-board { 29e13c6d14SVinod Koul compatible = "fixed-clock"; 30e13c6d14SVinod Koul #clock-cells = <0>; 31e13c6d14SVinod Koul clock-frequency = <38400000>; 32e13c6d14SVinod Koul clock-output-names = "xo_board"; 33e13c6d14SVinod Koul }; 34e13c6d14SVinod Koul 35e13c6d14SVinod Koul sleep_clk: sleep-clk { 36e13c6d14SVinod Koul compatible = "fixed-clock"; 37e13c6d14SVinod Koul #clock-cells = <0>; 38e13c6d14SVinod Koul clock-frequency = <32764>; 39e13c6d14SVinod Koul clock-output-names = "sleep_clk"; 40e13c6d14SVinod Koul }; 41e13c6d14SVinod Koul }; 42e13c6d14SVinod Koul 43e13c6d14SVinod Koul cpus { 44e13c6d14SVinod Koul #address-cells = <2>; 45e13c6d14SVinod Koul #size-cells = <0>; 46e13c6d14SVinod Koul 47e13c6d14SVinod Koul CPU0: cpu@0 { 48e13c6d14SVinod Koul device_type = "cpu"; 49e13c6d14SVinod Koul compatible = "qcom,kryo485"; 50e13c6d14SVinod Koul reg = <0x0 0x0>; 51fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 52e13c6d14SVinod Koul enable-method = "psci"; 535b2dae72SDanny Lin capacity-dmips-mhz = <488>; 545b2dae72SDanny Lin dynamic-power-coefficient = <232>; 55e13c6d14SVinod Koul next-level-cache = <&L2_0>; 56fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 572b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 5897c28902SAbel Vesa interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 598713c5e1SKrzysztof Kozlowski <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 60b2e3f897SDanny Lin power-domains = <&CPU_PD0>; 61b2e3f897SDanny Lin power-domain-names = "psci"; 62d2fa630cSAmit Kucheria #cooling-cells = <2>; 63e13c6d14SVinod Koul L2_0: l2-cache { 64e13c6d14SVinod Koul compatible = "cache"; 659435294cSPierre Gondois cache-level = <2>; 669c6e72fbSKrzysztof Kozlowski cache-unified; 67e13c6d14SVinod Koul next-level-cache = <&L3_0>; 68e13c6d14SVinod Koul L3_0: l3-cache { 69e13c6d14SVinod Koul compatible = "cache"; 709435294cSPierre Gondois cache-level = <3>; 719c6e72fbSKrzysztof Kozlowski cache-unified; 72e13c6d14SVinod Koul }; 73e13c6d14SVinod Koul }; 74e13c6d14SVinod Koul }; 75e13c6d14SVinod Koul 76e13c6d14SVinod Koul CPU1: cpu@100 { 77e13c6d14SVinod Koul device_type = "cpu"; 78e13c6d14SVinod Koul compatible = "qcom,kryo485"; 79e13c6d14SVinod Koul reg = <0x0 0x100>; 80fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 81e13c6d14SVinod Koul enable-method = "psci"; 825b2dae72SDanny Lin capacity-dmips-mhz = <488>; 835b2dae72SDanny Lin dynamic-power-coefficient = <232>; 84e13c6d14SVinod Koul next-level-cache = <&L2_100>; 85fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 862b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 8797c28902SAbel Vesa interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 888713c5e1SKrzysztof Kozlowski <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 89b2e3f897SDanny Lin power-domains = <&CPU_PD1>; 90b2e3f897SDanny Lin power-domain-names = "psci"; 91d2fa630cSAmit Kucheria #cooling-cells = <2>; 92e13c6d14SVinod Koul L2_100: l2-cache { 93e13c6d14SVinod Koul compatible = "cache"; 949435294cSPierre Gondois cache-level = <2>; 959c6e72fbSKrzysztof Kozlowski cache-unified; 96e13c6d14SVinod Koul next-level-cache = <&L3_0>; 97e13c6d14SVinod Koul }; 98e13c6d14SVinod Koul }; 99e13c6d14SVinod Koul 100e13c6d14SVinod Koul CPU2: cpu@200 { 101e13c6d14SVinod Koul device_type = "cpu"; 102e13c6d14SVinod Koul compatible = "qcom,kryo485"; 103e13c6d14SVinod Koul reg = <0x0 0x200>; 104fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 105e13c6d14SVinod Koul enable-method = "psci"; 1065b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1075b2dae72SDanny Lin dynamic-power-coefficient = <232>; 108e13c6d14SVinod Koul next-level-cache = <&L2_200>; 109fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1102b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 11197c28902SAbel Vesa interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 1128713c5e1SKrzysztof Kozlowski <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 113b2e3f897SDanny Lin power-domains = <&CPU_PD2>; 114b2e3f897SDanny Lin power-domain-names = "psci"; 115d2fa630cSAmit Kucheria #cooling-cells = <2>; 116e13c6d14SVinod Koul L2_200: l2-cache { 117e13c6d14SVinod Koul compatible = "cache"; 1189435294cSPierre Gondois cache-level = <2>; 1199c6e72fbSKrzysztof Kozlowski cache-unified; 120e13c6d14SVinod Koul next-level-cache = <&L3_0>; 121e13c6d14SVinod Koul }; 122e13c6d14SVinod Koul }; 123e13c6d14SVinod Koul 124e13c6d14SVinod Koul CPU3: cpu@300 { 125e13c6d14SVinod Koul device_type = "cpu"; 126e13c6d14SVinod Koul compatible = "qcom,kryo485"; 127e13c6d14SVinod Koul reg = <0x0 0x300>; 128fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 0>; 129e13c6d14SVinod Koul enable-method = "psci"; 1305b2dae72SDanny Lin capacity-dmips-mhz = <488>; 1315b2dae72SDanny Lin dynamic-power-coefficient = <232>; 132e13c6d14SVinod Koul next-level-cache = <&L2_300>; 133fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 0>; 1342b6187abSThara Gopinath operating-points-v2 = <&cpu0_opp_table>; 13597c28902SAbel Vesa interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 1368713c5e1SKrzysztof Kozlowski <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 137b2e3f897SDanny Lin power-domains = <&CPU_PD3>; 138b2e3f897SDanny Lin power-domain-names = "psci"; 139d2fa630cSAmit Kucheria #cooling-cells = <2>; 140e13c6d14SVinod Koul L2_300: l2-cache { 141e13c6d14SVinod Koul compatible = "cache"; 1429435294cSPierre Gondois cache-level = <2>; 1439c6e72fbSKrzysztof Kozlowski cache-unified; 144e13c6d14SVinod Koul next-level-cache = <&L3_0>; 145e13c6d14SVinod Koul }; 146e13c6d14SVinod Koul }; 147e13c6d14SVinod Koul 148e13c6d14SVinod Koul CPU4: cpu@400 { 149e13c6d14SVinod Koul device_type = "cpu"; 150e13c6d14SVinod Koul compatible = "qcom,kryo485"; 151e13c6d14SVinod Koul reg = <0x0 0x400>; 152fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 153e13c6d14SVinod Koul enable-method = "psci"; 1545b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1555b2dae72SDanny Lin dynamic-power-coefficient = <369>; 156e13c6d14SVinod Koul next-level-cache = <&L2_400>; 157fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1582b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 15997c28902SAbel Vesa interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 1608713c5e1SKrzysztof Kozlowski <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 161b2e3f897SDanny Lin power-domains = <&CPU_PD4>; 162b2e3f897SDanny Lin power-domain-names = "psci"; 163d2fa630cSAmit Kucheria #cooling-cells = <2>; 164e13c6d14SVinod Koul L2_400: l2-cache { 165e13c6d14SVinod Koul compatible = "cache"; 1669435294cSPierre Gondois cache-level = <2>; 1679c6e72fbSKrzysztof Kozlowski cache-unified; 168e13c6d14SVinod Koul next-level-cache = <&L3_0>; 169e13c6d14SVinod Koul }; 170e13c6d14SVinod Koul }; 171e13c6d14SVinod Koul 172e13c6d14SVinod Koul CPU5: cpu@500 { 173e13c6d14SVinod Koul device_type = "cpu"; 174e13c6d14SVinod Koul compatible = "qcom,kryo485"; 175e13c6d14SVinod Koul reg = <0x0 0x500>; 176fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 177e13c6d14SVinod Koul enable-method = "psci"; 1785b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 1795b2dae72SDanny Lin dynamic-power-coefficient = <369>; 180e13c6d14SVinod Koul next-level-cache = <&L2_500>; 181fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 1822b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 18397c28902SAbel Vesa interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 1848713c5e1SKrzysztof Kozlowski <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 185b2e3f897SDanny Lin power-domains = <&CPU_PD5>; 186b2e3f897SDanny Lin power-domain-names = "psci"; 187d2fa630cSAmit Kucheria #cooling-cells = <2>; 188e13c6d14SVinod Koul L2_500: l2-cache { 189e13c6d14SVinod Koul compatible = "cache"; 1909435294cSPierre Gondois cache-level = <2>; 1919c6e72fbSKrzysztof Kozlowski cache-unified; 192e13c6d14SVinod Koul next-level-cache = <&L3_0>; 193e13c6d14SVinod Koul }; 194e13c6d14SVinod Koul }; 195e13c6d14SVinod Koul 196e13c6d14SVinod Koul CPU6: cpu@600 { 197e13c6d14SVinod Koul device_type = "cpu"; 198e13c6d14SVinod Koul compatible = "qcom,kryo485"; 199e13c6d14SVinod Koul reg = <0x0 0x600>; 200fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 1>; 201e13c6d14SVinod Koul enable-method = "psci"; 2025b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2035b2dae72SDanny Lin dynamic-power-coefficient = <369>; 204e13c6d14SVinod Koul next-level-cache = <&L2_600>; 205fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 1>; 2062b6187abSThara Gopinath operating-points-v2 = <&cpu4_opp_table>; 20797c28902SAbel Vesa interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 2088713c5e1SKrzysztof Kozlowski <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209b2e3f897SDanny Lin power-domains = <&CPU_PD6>; 210b2e3f897SDanny Lin power-domain-names = "psci"; 211d2fa630cSAmit Kucheria #cooling-cells = <2>; 212e13c6d14SVinod Koul L2_600: l2-cache { 213e13c6d14SVinod Koul compatible = "cache"; 2149435294cSPierre Gondois cache-level = <2>; 2159c6e72fbSKrzysztof Kozlowski cache-unified; 216e13c6d14SVinod Koul next-level-cache = <&L3_0>; 217e13c6d14SVinod Koul }; 218e13c6d14SVinod Koul }; 219e13c6d14SVinod Koul 220e13c6d14SVinod Koul CPU7: cpu@700 { 221e13c6d14SVinod Koul device_type = "cpu"; 222e13c6d14SVinod Koul compatible = "qcom,kryo485"; 223e13c6d14SVinod Koul reg = <0x0 0x700>; 224fc725894SManivannan Sadhasivam clocks = <&cpufreq_hw 2>; 225e13c6d14SVinod Koul enable-method = "psci"; 2265b2dae72SDanny Lin capacity-dmips-mhz = <1024>; 2275b2dae72SDanny Lin dynamic-power-coefficient = <421>; 228e13c6d14SVinod Koul next-level-cache = <&L2_700>; 229fea8930bSSibi Sankar qcom,freq-domain = <&cpufreq_hw 2>; 2302b6187abSThara Gopinath operating-points-v2 = <&cpu7_opp_table>; 23197c28902SAbel Vesa interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 2328713c5e1SKrzysztof Kozlowski <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 233b2e3f897SDanny Lin power-domains = <&CPU_PD7>; 234b2e3f897SDanny Lin power-domain-names = "psci"; 235d2fa630cSAmit Kucheria #cooling-cells = <2>; 236e13c6d14SVinod Koul L2_700: l2-cache { 237e13c6d14SVinod Koul compatible = "cache"; 2389435294cSPierre Gondois cache-level = <2>; 2399c6e72fbSKrzysztof Kozlowski cache-unified; 240e13c6d14SVinod Koul next-level-cache = <&L3_0>; 241e13c6d14SVinod Koul }; 242e13c6d14SVinod Koul }; 243066d21bcSDanny Lin 244066d21bcSDanny Lin cpu-map { 245066d21bcSDanny Lin cluster0 { 246066d21bcSDanny Lin core0 { 247066d21bcSDanny Lin cpu = <&CPU0>; 248066d21bcSDanny Lin }; 249066d21bcSDanny Lin 250066d21bcSDanny Lin core1 { 251066d21bcSDanny Lin cpu = <&CPU1>; 252066d21bcSDanny Lin }; 253066d21bcSDanny Lin 254066d21bcSDanny Lin core2 { 255066d21bcSDanny Lin cpu = <&CPU2>; 256066d21bcSDanny Lin }; 257066d21bcSDanny Lin 258066d21bcSDanny Lin core3 { 259066d21bcSDanny Lin cpu = <&CPU3>; 260066d21bcSDanny Lin }; 261066d21bcSDanny Lin 262066d21bcSDanny Lin core4 { 263066d21bcSDanny Lin cpu = <&CPU4>; 264066d21bcSDanny Lin }; 265066d21bcSDanny Lin 266066d21bcSDanny Lin core5 { 267066d21bcSDanny Lin cpu = <&CPU5>; 268066d21bcSDanny Lin }; 269066d21bcSDanny Lin 270066d21bcSDanny Lin core6 { 271066d21bcSDanny Lin cpu = <&CPU6>; 272066d21bcSDanny Lin }; 273066d21bcSDanny Lin 274066d21bcSDanny Lin core7 { 275066d21bcSDanny Lin cpu = <&CPU7>; 276066d21bcSDanny Lin }; 277066d21bcSDanny Lin }; 278066d21bcSDanny Lin }; 27981188f58SDanny Lin 28081188f58SDanny Lin idle-states { 28181188f58SDanny Lin entry-method = "psci"; 28281188f58SDanny Lin 28381188f58SDanny Lin LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 28481188f58SDanny Lin compatible = "arm,idle-state"; 28581188f58SDanny Lin idle-state-name = "little-rail-power-collapse"; 28681188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 28781188f58SDanny Lin entry-latency-us = <355>; 28881188f58SDanny Lin exit-latency-us = <909>; 28981188f58SDanny Lin min-residency-us = <3934>; 29081188f58SDanny Lin local-timer-stop; 29181188f58SDanny Lin }; 29281188f58SDanny Lin 29381188f58SDanny Lin BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 29481188f58SDanny Lin compatible = "arm,idle-state"; 29581188f58SDanny Lin idle-state-name = "big-rail-power-collapse"; 29681188f58SDanny Lin arm,psci-suspend-param = <0x40000004>; 29781188f58SDanny Lin entry-latency-us = <241>; 29881188f58SDanny Lin exit-latency-us = <1461>; 29981188f58SDanny Lin min-residency-us = <4488>; 30081188f58SDanny Lin local-timer-stop; 30181188f58SDanny Lin }; 302b2e3f897SDanny Lin }; 30381188f58SDanny Lin 304b2e3f897SDanny Lin domain-idle-states { 30581188f58SDanny Lin CLUSTER_SLEEP_0: cluster-sleep-0 { 306b2e3f897SDanny Lin compatible = "domain-idle-state"; 307b2e3f897SDanny Lin arm,psci-suspend-param = <0x4100c244>; 30881188f58SDanny Lin entry-latency-us = <3263>; 30981188f58SDanny Lin exit-latency-us = <6562>; 31081188f58SDanny Lin min-residency-us = <9987>; 31181188f58SDanny Lin }; 31281188f58SDanny Lin }; 313e13c6d14SVinod Koul }; 314e13c6d14SVinod Koul 3150e3e6546SKrzysztof Kozlowski cpu0_opp_table: opp-table-cpu0 { 3162b6187abSThara Gopinath compatible = "operating-points-v2"; 3172b6187abSThara Gopinath opp-shared; 3182b6187abSThara Gopinath 3192b6187abSThara Gopinath cpu0_opp1: opp-300000000 { 3202b6187abSThara Gopinath opp-hz = /bits/ 64 <300000000>; 3212b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3222b6187abSThara Gopinath }; 3232b6187abSThara Gopinath 3242b6187abSThara Gopinath cpu0_opp2: opp-403200000 { 3252b6187abSThara Gopinath opp-hz = /bits/ 64 <403200000>; 3262b6187abSThara Gopinath opp-peak-kBps = <800000 9600000>; 3272b6187abSThara Gopinath }; 3282b6187abSThara Gopinath 3292b6187abSThara Gopinath cpu0_opp3: opp-499200000 { 3302b6187abSThara Gopinath opp-hz = /bits/ 64 <499200000>; 3312b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3322b6187abSThara Gopinath }; 3332b6187abSThara Gopinath 3342b6187abSThara Gopinath cpu0_opp4: opp-576000000 { 3352b6187abSThara Gopinath opp-hz = /bits/ 64 <576000000>; 3362b6187abSThara Gopinath opp-peak-kBps = <800000 12902400>; 3372b6187abSThara Gopinath }; 3382b6187abSThara Gopinath 3392b6187abSThara Gopinath cpu0_opp5: opp-672000000 { 3402b6187abSThara Gopinath opp-hz = /bits/ 64 <672000000>; 3412b6187abSThara Gopinath opp-peak-kBps = <800000 15974400>; 3422b6187abSThara Gopinath }; 3432b6187abSThara Gopinath 3442b6187abSThara Gopinath cpu0_opp6: opp-768000000 { 345ce3b50cfSThara Gopinath opp-hz = /bits/ 64 <768000000>; 3462b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3472b6187abSThara Gopinath }; 3482b6187abSThara Gopinath 3492b6187abSThara Gopinath cpu0_opp7: opp-844800000 { 3502b6187abSThara Gopinath opp-hz = /bits/ 64 <844800000>; 3512b6187abSThara Gopinath opp-peak-kBps = <1804000 19660800>; 3522b6187abSThara Gopinath }; 3532b6187abSThara Gopinath 3542b6187abSThara Gopinath cpu0_opp8: opp-940800000 { 3552b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 3562b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3572b6187abSThara Gopinath }; 3582b6187abSThara Gopinath 3592b6187abSThara Gopinath cpu0_opp9: opp-1036800000 { 3602b6187abSThara Gopinath opp-hz = /bits/ 64 <1036800000>; 3612b6187abSThara Gopinath opp-peak-kBps = <1804000 22732800>; 3622b6187abSThara Gopinath }; 3632b6187abSThara Gopinath 3642b6187abSThara Gopinath cpu0_opp10: opp-1113600000 { 3652b6187abSThara Gopinath opp-hz = /bits/ 64 <1113600000>; 3662b6187abSThara Gopinath opp-peak-kBps = <2188000 25804800>; 3672b6187abSThara Gopinath }; 3682b6187abSThara Gopinath 3692b6187abSThara Gopinath cpu0_opp11: opp-1209600000 { 3702b6187abSThara Gopinath opp-hz = /bits/ 64 <1209600000>; 3712b6187abSThara Gopinath opp-peak-kBps = <2188000 31948800>; 3722b6187abSThara Gopinath }; 3732b6187abSThara Gopinath 3742b6187abSThara Gopinath cpu0_opp12: opp-1305600000 { 3752b6187abSThara Gopinath opp-hz = /bits/ 64 <1305600000>; 3762b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3772b6187abSThara Gopinath }; 3782b6187abSThara Gopinath 3792b6187abSThara Gopinath cpu0_opp13: opp-1382400000 { 3802b6187abSThara Gopinath opp-hz = /bits/ 64 <1382400000>; 3812b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3822b6187abSThara Gopinath }; 3832b6187abSThara Gopinath 3842b6187abSThara Gopinath cpu0_opp14: opp-1478400000 { 3852b6187abSThara Gopinath opp-hz = /bits/ 64 <1478400000>; 3862b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 3872b6187abSThara Gopinath }; 3882b6187abSThara Gopinath 3892b6187abSThara Gopinath cpu0_opp15: opp-1555200000 { 3902b6187abSThara Gopinath opp-hz = /bits/ 64 <1555200000>; 3912b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3922b6187abSThara Gopinath }; 3932b6187abSThara Gopinath 3942b6187abSThara Gopinath cpu0_opp16: opp-1632000000 { 3952b6187abSThara Gopinath opp-hz = /bits/ 64 <1632000000>; 3962b6187abSThara Gopinath opp-peak-kBps = <3072000 40550400>; 3972b6187abSThara Gopinath }; 3982b6187abSThara Gopinath 3992b6187abSThara Gopinath cpu0_opp17: opp-1708800000 { 4002b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4012b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 4022b6187abSThara Gopinath }; 4032b6187abSThara Gopinath 4042b6187abSThara Gopinath cpu0_opp18: opp-1785600000 { 4052b6187abSThara Gopinath opp-hz = /bits/ 64 <1785600000>; 4062b6187abSThara Gopinath opp-peak-kBps = <3072000 43008000>; 4072b6187abSThara Gopinath }; 4082b6187abSThara Gopinath }; 4092b6187abSThara Gopinath 4100e3e6546SKrzysztof Kozlowski cpu4_opp_table: opp-table-cpu4 { 4112b6187abSThara Gopinath compatible = "operating-points-v2"; 4122b6187abSThara Gopinath opp-shared; 4132b6187abSThara Gopinath 4142b6187abSThara Gopinath cpu4_opp1: opp-710400000 { 4152b6187abSThara Gopinath opp-hz = /bits/ 64 <710400000>; 4162b6187abSThara Gopinath opp-peak-kBps = <1804000 15974400>; 4172b6187abSThara Gopinath }; 4182b6187abSThara Gopinath 4192b6187abSThara Gopinath cpu4_opp2: opp-825600000 { 4202b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 4212b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 4222b6187abSThara Gopinath }; 4232b6187abSThara Gopinath 4242b6187abSThara Gopinath cpu4_opp3: opp-940800000 { 4252b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 4262b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 4272b6187abSThara Gopinath }; 4282b6187abSThara Gopinath 4292b6187abSThara Gopinath cpu4_opp4: opp-1056000000 { 4302b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 4312b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 4322b6187abSThara Gopinath }; 4332b6187abSThara Gopinath 4342b6187abSThara Gopinath cpu4_opp5: opp-1171200000 { 4352b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 4362b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 4372b6187abSThara Gopinath }; 4382b6187abSThara Gopinath 4392b6187abSThara Gopinath cpu4_opp6: opp-1286400000 { 4402b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 4412b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4422b6187abSThara Gopinath }; 4432b6187abSThara Gopinath 4442b6187abSThara Gopinath cpu4_opp7: opp-1401600000 { 4452b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 4462b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 4472b6187abSThara Gopinath }; 4482b6187abSThara Gopinath 4492b6187abSThara Gopinath cpu4_opp8: opp-1497600000 { 4502b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 4512b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4522b6187abSThara Gopinath }; 4532b6187abSThara Gopinath 4542b6187abSThara Gopinath cpu4_opp9: opp-1612800000 { 4552b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 4562b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 4572b6187abSThara Gopinath }; 4582b6187abSThara Gopinath 4592b6187abSThara Gopinath cpu4_opp10: opp-1708800000 { 4602b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 4612b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 4622b6187abSThara Gopinath }; 4632b6187abSThara Gopinath 4642b6187abSThara Gopinath cpu4_opp11: opp-1804800000 { 4652b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 4662b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 4672b6187abSThara Gopinath }; 4682b6187abSThara Gopinath 4692b6187abSThara Gopinath cpu4_opp12: opp-1920000000 { 4702b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 4712b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 4722b6187abSThara Gopinath }; 4732b6187abSThara Gopinath 4742b6187abSThara Gopinath cpu4_opp13: opp-2016000000 { 4752b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 4762b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 4772b6187abSThara Gopinath }; 4782b6187abSThara Gopinath 4792b6187abSThara Gopinath cpu4_opp14: opp-2131200000 { 4802b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 4812b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 4822b6187abSThara Gopinath }; 4832b6187abSThara Gopinath 4842b6187abSThara Gopinath cpu4_opp15: opp-2227200000 { 4852b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 4862b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4872b6187abSThara Gopinath }; 4882b6187abSThara Gopinath 4892b6187abSThara Gopinath cpu4_opp16: opp-2323200000 { 4902b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 4912b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4922b6187abSThara Gopinath }; 4932b6187abSThara Gopinath 4942b6187abSThara Gopinath cpu4_opp17: opp-2419200000 { 4952b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 4962b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 4972b6187abSThara Gopinath }; 4982b6187abSThara Gopinath }; 4992b6187abSThara Gopinath 5000e3e6546SKrzysztof Kozlowski cpu7_opp_table: opp-table-cpu7 { 5012b6187abSThara Gopinath compatible = "operating-points-v2"; 5022b6187abSThara Gopinath opp-shared; 5032b6187abSThara Gopinath 5042b6187abSThara Gopinath cpu7_opp1: opp-825600000 { 5052b6187abSThara Gopinath opp-hz = /bits/ 64 <825600000>; 5062b6187abSThara Gopinath opp-peak-kBps = <2188000 19660800>; 5072b6187abSThara Gopinath }; 5082b6187abSThara Gopinath 5092b6187abSThara Gopinath cpu7_opp2: opp-940800000 { 5102b6187abSThara Gopinath opp-hz = /bits/ 64 <940800000>; 5112b6187abSThara Gopinath opp-peak-kBps = <2188000 22732800>; 5122b6187abSThara Gopinath }; 5132b6187abSThara Gopinath 5142b6187abSThara Gopinath cpu7_opp3: opp-1056000000 { 5152b6187abSThara Gopinath opp-hz = /bits/ 64 <1056000000>; 5162b6187abSThara Gopinath opp-peak-kBps = <3072000 25804800>; 5172b6187abSThara Gopinath }; 5182b6187abSThara Gopinath 5192b6187abSThara Gopinath cpu7_opp4: opp-1171200000 { 5202b6187abSThara Gopinath opp-hz = /bits/ 64 <1171200000>; 5212b6187abSThara Gopinath opp-peak-kBps = <3072000 31948800>; 5222b6187abSThara Gopinath }; 5232b6187abSThara Gopinath 5242b6187abSThara Gopinath cpu7_opp5: opp-1286400000 { 5252b6187abSThara Gopinath opp-hz = /bits/ 64 <1286400000>; 5262b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5272b6187abSThara Gopinath }; 5282b6187abSThara Gopinath 5292b6187abSThara Gopinath cpu7_opp6: opp-1401600000 { 5302b6187abSThara Gopinath opp-hz = /bits/ 64 <1401600000>; 5312b6187abSThara Gopinath opp-peak-kBps = <4068000 31948800>; 5322b6187abSThara Gopinath }; 5332b6187abSThara Gopinath 5342b6187abSThara Gopinath cpu7_opp7: opp-1497600000 { 5352b6187abSThara Gopinath opp-hz = /bits/ 64 <1497600000>; 5362b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5372b6187abSThara Gopinath }; 5382b6187abSThara Gopinath 5392b6187abSThara Gopinath cpu7_opp8: opp-1612800000 { 5402b6187abSThara Gopinath opp-hz = /bits/ 64 <1612800000>; 5412b6187abSThara Gopinath opp-peak-kBps = <4068000 40550400>; 5422b6187abSThara Gopinath }; 5432b6187abSThara Gopinath 5442b6187abSThara Gopinath cpu7_opp9: opp-1708800000 { 5452b6187abSThara Gopinath opp-hz = /bits/ 64 <1708800000>; 5462b6187abSThara Gopinath opp-peak-kBps = <4068000 43008000>; 5472b6187abSThara Gopinath }; 5482b6187abSThara Gopinath 5492b6187abSThara Gopinath cpu7_opp10: opp-1804800000 { 5502b6187abSThara Gopinath opp-hz = /bits/ 64 <1804800000>; 5512b6187abSThara Gopinath opp-peak-kBps = <6220000 43008000>; 5522b6187abSThara Gopinath }; 5532b6187abSThara Gopinath 5542b6187abSThara Gopinath cpu7_opp11: opp-1920000000 { 5552b6187abSThara Gopinath opp-hz = /bits/ 64 <1920000000>; 5562b6187abSThara Gopinath opp-peak-kBps = <6220000 49152000>; 5572b6187abSThara Gopinath }; 5582b6187abSThara Gopinath 5592b6187abSThara Gopinath cpu7_opp12: opp-2016000000 { 5602b6187abSThara Gopinath opp-hz = /bits/ 64 <2016000000>; 5612b6187abSThara Gopinath opp-peak-kBps = <7216000 49152000>; 5622b6187abSThara Gopinath }; 5632b6187abSThara Gopinath 5642b6187abSThara Gopinath cpu7_opp13: opp-2131200000 { 5652b6187abSThara Gopinath opp-hz = /bits/ 64 <2131200000>; 5662b6187abSThara Gopinath opp-peak-kBps = <8368000 49152000>; 5672b6187abSThara Gopinath }; 5682b6187abSThara Gopinath 5692b6187abSThara Gopinath cpu7_opp14: opp-2227200000 { 5702b6187abSThara Gopinath opp-hz = /bits/ 64 <2227200000>; 5712b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5722b6187abSThara Gopinath }; 5732b6187abSThara Gopinath 5742b6187abSThara Gopinath cpu7_opp15: opp-2323200000 { 5752b6187abSThara Gopinath opp-hz = /bits/ 64 <2323200000>; 5762b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5772b6187abSThara Gopinath }; 5782b6187abSThara Gopinath 5792b6187abSThara Gopinath cpu7_opp16: opp-2419200000 { 5802b6187abSThara Gopinath opp-hz = /bits/ 64 <2419200000>; 5812b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5822b6187abSThara Gopinath }; 5832b6187abSThara Gopinath 5842b6187abSThara Gopinath cpu7_opp17: opp-2534400000 { 5852b6187abSThara Gopinath opp-hz = /bits/ 64 <2534400000>; 5862b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5872b6187abSThara Gopinath }; 5882b6187abSThara Gopinath 5892b6187abSThara Gopinath cpu7_opp18: opp-2649600000 { 5902b6187abSThara Gopinath opp-hz = /bits/ 64 <2649600000>; 5912b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5922b6187abSThara Gopinath }; 5932b6187abSThara Gopinath 5942b6187abSThara Gopinath cpu7_opp19: opp-2745600000 { 5952b6187abSThara Gopinath opp-hz = /bits/ 64 <2745600000>; 5962b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 5972b6187abSThara Gopinath }; 5982b6187abSThara Gopinath 5992b6187abSThara Gopinath cpu7_opp20: opp-2841600000 { 6002b6187abSThara Gopinath opp-hz = /bits/ 64 <2841600000>; 6012b6187abSThara Gopinath opp-peak-kBps = <8368000 51609600>; 6022b6187abSThara Gopinath }; 6032b6187abSThara Gopinath }; 6042b6187abSThara Gopinath 605e13c6d14SVinod Koul firmware { 606e13c6d14SVinod Koul scm: scm { 607e13c6d14SVinod Koul compatible = "qcom,scm-sm8150", "qcom,scm"; 608e13c6d14SVinod Koul #reset-cells = <1>; 609e13c6d14SVinod Koul }; 610e13c6d14SVinod Koul }; 611e13c6d14SVinod Koul 612e13c6d14SVinod Koul memory@80000000 { 613e13c6d14SVinod Koul device_type = "memory"; 614e13c6d14SVinod Koul /* We expect the bootloader to fill in the size */ 615e13c6d14SVinod Koul reg = <0x0 0x80000000 0x0 0x0>; 616e13c6d14SVinod Koul }; 617e13c6d14SVinod Koul 618d8cf9372SVinod Koul pmu { 619d8cf9372SVinod Koul compatible = "arm,armv8-pmuv3"; 620d8cf9372SVinod Koul interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 621d8cf9372SVinod Koul }; 622d8cf9372SVinod Koul 623e13c6d14SVinod Koul psci { 624e13c6d14SVinod Koul compatible = "arm,psci-1.0"; 625e13c6d14SVinod Koul method = "smc"; 626b2e3f897SDanny Lin 6275ca45690SKrzysztof Kozlowski CPU_PD0: power-domain-cpu0 { 628b2e3f897SDanny Lin #power-domain-cells = <0>; 629b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 630b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 631b2e3f897SDanny Lin }; 632b2e3f897SDanny Lin 6335ca45690SKrzysztof Kozlowski CPU_PD1: power-domain-cpu1 { 634b2e3f897SDanny Lin #power-domain-cells = <0>; 635b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 636b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 637b2e3f897SDanny Lin }; 638b2e3f897SDanny Lin 6395ca45690SKrzysztof Kozlowski CPU_PD2: power-domain-cpu2 { 640b2e3f897SDanny Lin #power-domain-cells = <0>; 641b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 642b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 643b2e3f897SDanny Lin }; 644b2e3f897SDanny Lin 6455ca45690SKrzysztof Kozlowski CPU_PD3: power-domain-cpu3 { 646b2e3f897SDanny Lin #power-domain-cells = <0>; 647b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 648b2e3f897SDanny Lin domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 649b2e3f897SDanny Lin }; 650b2e3f897SDanny Lin 6515ca45690SKrzysztof Kozlowski CPU_PD4: power-domain-cpu4 { 652b2e3f897SDanny Lin #power-domain-cells = <0>; 653b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 654b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 655b2e3f897SDanny Lin }; 656b2e3f897SDanny Lin 6575ca45690SKrzysztof Kozlowski CPU_PD5: power-domain-cpu5 { 658b2e3f897SDanny Lin #power-domain-cells = <0>; 659b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 660b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 661b2e3f897SDanny Lin }; 662b2e3f897SDanny Lin 6635ca45690SKrzysztof Kozlowski CPU_PD6: power-domain-cpu6 { 664b2e3f897SDanny Lin #power-domain-cells = <0>; 665b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 666b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 667b2e3f897SDanny Lin }; 668b2e3f897SDanny Lin 6695ca45690SKrzysztof Kozlowski CPU_PD7: power-domain-cpu7 { 670b2e3f897SDanny Lin #power-domain-cells = <0>; 671b2e3f897SDanny Lin power-domains = <&CLUSTER_PD>; 672b2e3f897SDanny Lin domain-idle-states = <&BIG_CPU_SLEEP_0>; 673b2e3f897SDanny Lin }; 674b2e3f897SDanny Lin 6755ca45690SKrzysztof Kozlowski CLUSTER_PD: power-domain-cpu-cluster0 { 676b2e3f897SDanny Lin #power-domain-cells = <0>; 677b2e3f897SDanny Lin domain-idle-states = <&CLUSTER_SLEEP_0>; 678b2e3f897SDanny Lin }; 679e13c6d14SVinod Koul }; 680e13c6d14SVinod Koul 681912c373aSVinod Koul reserved-memory { 682912c373aSVinod Koul #address-cells = <2>; 683912c373aSVinod Koul #size-cells = <2>; 684912c373aSVinod Koul ranges; 685912c373aSVinod Koul 686912c373aSVinod Koul hyp_mem: memory@85700000 { 687912c373aSVinod Koul reg = <0x0 0x85700000 0x0 0x600000>; 688912c373aSVinod Koul no-map; 689912c373aSVinod Koul }; 690912c373aSVinod Koul 691912c373aSVinod Koul xbl_mem: memory@85d00000 { 692912c373aSVinod Koul reg = <0x0 0x85d00000 0x0 0x140000>; 693912c373aSVinod Koul no-map; 694912c373aSVinod Koul }; 695912c373aSVinod Koul 696912c373aSVinod Koul aop_mem: memory@85f00000 { 697912c373aSVinod Koul reg = <0x0 0x85f00000 0x0 0x20000>; 698912c373aSVinod Koul no-map; 699912c373aSVinod Koul }; 700912c373aSVinod Koul 701912c373aSVinod Koul aop_cmd_db: memory@85f20000 { 702912c373aSVinod Koul compatible = "qcom,cmd-db"; 703912c373aSVinod Koul reg = <0x0 0x85f20000 0x0 0x20000>; 704912c373aSVinod Koul no-map; 705912c373aSVinod Koul }; 706912c373aSVinod Koul 707912c373aSVinod Koul smem_mem: memory@86000000 { 708912c373aSVinod Koul reg = <0x0 0x86000000 0x0 0x200000>; 709912c373aSVinod Koul no-map; 710912c373aSVinod Koul }; 711912c373aSVinod Koul 712912c373aSVinod Koul tz_mem: memory@86200000 { 713912c373aSVinod Koul reg = <0x0 0x86200000 0x0 0x3900000>; 714912c373aSVinod Koul no-map; 715912c373aSVinod Koul }; 716912c373aSVinod Koul 717912c373aSVinod Koul rmtfs_mem: memory@89b00000 { 718912c373aSVinod Koul compatible = "qcom,rmtfs-mem"; 719912c373aSVinod Koul reg = <0x0 0x89b00000 0x0 0x200000>; 720912c373aSVinod Koul no-map; 721912c373aSVinod Koul 722912c373aSVinod Koul qcom,client-id = <1>; 723912c373aSVinod Koul qcom,vmid = <15>; 724912c373aSVinod Koul }; 725912c373aSVinod Koul 726912c373aSVinod Koul camera_mem: memory@8b700000 { 727912c373aSVinod Koul reg = <0x0 0x8b700000 0x0 0x500000>; 728912c373aSVinod Koul no-map; 729912c373aSVinod Koul }; 730912c373aSVinod Koul 731912c373aSVinod Koul wlan_mem: memory@8bc00000 { 732912c373aSVinod Koul reg = <0x0 0x8bc00000 0x0 0x180000>; 733912c373aSVinod Koul no-map; 734912c373aSVinod Koul }; 735912c373aSVinod Koul 736912c373aSVinod Koul npu_mem: memory@8bd80000 { 737912c373aSVinod Koul reg = <0x0 0x8bd80000 0x0 0x80000>; 738912c373aSVinod Koul no-map; 739912c373aSVinod Koul }; 740912c373aSVinod Koul 741912c373aSVinod Koul adsp_mem: memory@8be00000 { 742912c373aSVinod Koul reg = <0x0 0x8be00000 0x0 0x1a00000>; 743912c373aSVinod Koul no-map; 744912c373aSVinod Koul }; 745912c373aSVinod Koul 746912c373aSVinod Koul mpss_mem: memory@8d800000 { 747912c373aSVinod Koul reg = <0x0 0x8d800000 0x0 0x9600000>; 748912c373aSVinod Koul no-map; 749912c373aSVinod Koul }; 750912c373aSVinod Koul 751912c373aSVinod Koul venus_mem: memory@96e00000 { 752912c373aSVinod Koul reg = <0x0 0x96e00000 0x0 0x500000>; 753912c373aSVinod Koul no-map; 754912c373aSVinod Koul }; 755912c373aSVinod Koul 756912c373aSVinod Koul slpi_mem: memory@97300000 { 757912c373aSVinod Koul reg = <0x0 0x97300000 0x0 0x1400000>; 758912c373aSVinod Koul no-map; 759912c373aSVinod Koul }; 760912c373aSVinod Koul 761912c373aSVinod Koul ipa_fw_mem: memory@98700000 { 762912c373aSVinod Koul reg = <0x0 0x98700000 0x0 0x10000>; 763912c373aSVinod Koul no-map; 764912c373aSVinod Koul }; 765912c373aSVinod Koul 766912c373aSVinod Koul ipa_gsi_mem: memory@98710000 { 767912c373aSVinod Koul reg = <0x0 0x98710000 0x0 0x5000>; 768912c373aSVinod Koul no-map; 769912c373aSVinod Koul }; 770912c373aSVinod Koul 771912c373aSVinod Koul gpu_mem: memory@98715000 { 772912c373aSVinod Koul reg = <0x0 0x98715000 0x0 0x2000>; 773912c373aSVinod Koul no-map; 774912c373aSVinod Koul }; 775912c373aSVinod Koul 776912c373aSVinod Koul spss_mem: memory@98800000 { 777912c373aSVinod Koul reg = <0x0 0x98800000 0x0 0x100000>; 778912c373aSVinod Koul no-map; 779912c373aSVinod Koul }; 780912c373aSVinod Koul 781912c373aSVinod Koul cdsp_mem: memory@98900000 { 782912c373aSVinod Koul reg = <0x0 0x98900000 0x0 0x1400000>; 783912c373aSVinod Koul no-map; 784912c373aSVinod Koul }; 785912c373aSVinod Koul 786912c373aSVinod Koul qseecom_mem: memory@9e400000 { 787912c373aSVinod Koul reg = <0x0 0x9e400000 0x0 0x1400000>; 788912c373aSVinod Koul no-map; 789912c373aSVinod Koul }; 790912c373aSVinod Koul }; 791912c373aSVinod Koul 792d8cf9372SVinod Koul smem { 793d8cf9372SVinod Koul compatible = "qcom,smem"; 794d8cf9372SVinod Koul memory-region = <&smem_mem>; 795d8cf9372SVinod Koul hwlocks = <&tcsr_mutex 3>; 796d8cf9372SVinod Koul }; 797d8cf9372SVinod Koul 79861025b81SSibi Sankar smp2p-cdsp { 79961025b81SSibi Sankar compatible = "qcom,smp2p"; 80061025b81SSibi Sankar qcom,smem = <94>, <432>; 80161025b81SSibi Sankar 80261025b81SSibi Sankar interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 80361025b81SSibi Sankar 80461025b81SSibi Sankar mboxes = <&apss_shared 6>; 80561025b81SSibi Sankar 80661025b81SSibi Sankar qcom,local-pid = <0>; 80761025b81SSibi Sankar qcom,remote-pid = <5>; 80861025b81SSibi Sankar 80961025b81SSibi Sankar cdsp_smp2p_out: master-kernel { 81061025b81SSibi Sankar qcom,entry-name = "master-kernel"; 81161025b81SSibi Sankar #qcom,smem-state-cells = <1>; 81261025b81SSibi Sankar }; 81361025b81SSibi Sankar 81461025b81SSibi Sankar cdsp_smp2p_in: slave-kernel { 81561025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 81661025b81SSibi Sankar 81761025b81SSibi Sankar interrupt-controller; 81861025b81SSibi Sankar #interrupt-cells = <2>; 81961025b81SSibi Sankar }; 82061025b81SSibi Sankar }; 82161025b81SSibi Sankar 82261025b81SSibi Sankar smp2p-lpass { 82361025b81SSibi Sankar compatible = "qcom,smp2p"; 82461025b81SSibi Sankar qcom,smem = <443>, <429>; 82561025b81SSibi Sankar 82661025b81SSibi Sankar interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 82761025b81SSibi Sankar 82861025b81SSibi Sankar mboxes = <&apss_shared 10>; 82961025b81SSibi Sankar 83061025b81SSibi Sankar qcom,local-pid = <0>; 83161025b81SSibi Sankar qcom,remote-pid = <2>; 83261025b81SSibi Sankar 83361025b81SSibi Sankar adsp_smp2p_out: master-kernel { 83461025b81SSibi Sankar qcom,entry-name = "master-kernel"; 83561025b81SSibi Sankar #qcom,smem-state-cells = <1>; 83661025b81SSibi Sankar }; 83761025b81SSibi Sankar 83861025b81SSibi Sankar adsp_smp2p_in: slave-kernel { 83961025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 84061025b81SSibi Sankar 84161025b81SSibi Sankar interrupt-controller; 84261025b81SSibi Sankar #interrupt-cells = <2>; 84361025b81SSibi Sankar }; 84461025b81SSibi Sankar }; 84561025b81SSibi Sankar 84661025b81SSibi Sankar smp2p-mpss { 84761025b81SSibi Sankar compatible = "qcom,smp2p"; 84861025b81SSibi Sankar qcom,smem = <435>, <428>; 84961025b81SSibi Sankar 85061025b81SSibi Sankar interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 85161025b81SSibi Sankar 85261025b81SSibi Sankar mboxes = <&apss_shared 14>; 85361025b81SSibi Sankar 85461025b81SSibi Sankar qcom,local-pid = <0>; 85561025b81SSibi Sankar qcom,remote-pid = <1>; 85661025b81SSibi Sankar 85761025b81SSibi Sankar modem_smp2p_out: master-kernel { 85861025b81SSibi Sankar qcom,entry-name = "master-kernel"; 85961025b81SSibi Sankar #qcom,smem-state-cells = <1>; 86061025b81SSibi Sankar }; 86161025b81SSibi Sankar 86261025b81SSibi Sankar modem_smp2p_in: slave-kernel { 86361025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 86461025b81SSibi Sankar 86561025b81SSibi Sankar interrupt-controller; 86661025b81SSibi Sankar #interrupt-cells = <2>; 86761025b81SSibi Sankar }; 86861025b81SSibi Sankar }; 86961025b81SSibi Sankar 87061025b81SSibi Sankar smp2p-slpi { 87161025b81SSibi Sankar compatible = "qcom,smp2p"; 87261025b81SSibi Sankar qcom,smem = <481>, <430>; 87361025b81SSibi Sankar 87461025b81SSibi Sankar interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 87561025b81SSibi Sankar 87661025b81SSibi Sankar mboxes = <&apss_shared 26>; 87761025b81SSibi Sankar 87861025b81SSibi Sankar qcom,local-pid = <0>; 87961025b81SSibi Sankar qcom,remote-pid = <3>; 88061025b81SSibi Sankar 88161025b81SSibi Sankar slpi_smp2p_out: master-kernel { 88261025b81SSibi Sankar qcom,entry-name = "master-kernel"; 88361025b81SSibi Sankar #qcom,smem-state-cells = <1>; 88461025b81SSibi Sankar }; 88561025b81SSibi Sankar 88661025b81SSibi Sankar slpi_smp2p_in: slave-kernel { 88761025b81SSibi Sankar qcom,entry-name = "slave-kernel"; 88861025b81SSibi Sankar 88961025b81SSibi Sankar interrupt-controller; 89061025b81SSibi Sankar #interrupt-cells = <2>; 89161025b81SSibi Sankar }; 89261025b81SSibi Sankar }; 89361025b81SSibi Sankar 894e13c6d14SVinod Koul soc: soc@0 { 895e13c6d14SVinod Koul #address-cells = <2>; 896e13c6d14SVinod Koul #size-cells = <2>; 897e13c6d14SVinod Koul ranges = <0 0 0 0 0x10 0>; 898e13c6d14SVinod Koul dma-ranges = <0 0 0 0 0x10 0>; 899e13c6d14SVinod Koul compatible = "simple-bus"; 900e13c6d14SVinod Koul 901e13c6d14SVinod Koul gcc: clock-controller@100000 { 902e13c6d14SVinod Koul compatible = "qcom,gcc-sm8150"; 903e13c6d14SVinod Koul reg = <0x0 0x00100000 0x0 0x1f0000>; 904e13c6d14SVinod Koul #clock-cells = <1>; 905e13c6d14SVinod Koul #reset-cells = <1>; 906e13c6d14SVinod Koul #power-domain-cells = <1>; 907e13c6d14SVinod Koul clock-names = "bi_tcxo", 908e13c6d14SVinod Koul "sleep_clk"; 909e13c6d14SVinod Koul clocks = <&rpmhcc RPMH_CXO_CLK>, 910e13c6d14SVinod Koul <&sleep_clk>; 911e13c6d14SVinod Koul }; 912e13c6d14SVinod Koul 91305006290SFelipe Balbi gpi_dma0: dma-controller@800000 { 914e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 915f6973229SKonrad Dybcio reg = <0 0x00800000 0 0x60000>; 91605006290SFelipe Balbi interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 91705006290SFelipe Balbi <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 91805006290SFelipe Balbi <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 91905006290SFelipe Balbi <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 92005006290SFelipe Balbi <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 92105006290SFelipe Balbi <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 92205006290SFelipe Balbi <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 92305006290SFelipe Balbi <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 92405006290SFelipe Balbi <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 92505006290SFelipe Balbi <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 92605006290SFelipe Balbi <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 92705006290SFelipe Balbi <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 92805006290SFelipe Balbi <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 92905006290SFelipe Balbi dma-channels = <13>; 93005006290SFelipe Balbi dma-channel-mask = <0xfa>; 93105006290SFelipe Balbi iommus = <&apps_smmu 0x00d6 0x0>; 93205006290SFelipe Balbi #dma-cells = <3>; 93305006290SFelipe Balbi status = "disabled"; 93405006290SFelipe Balbi }; 93505006290SFelipe Balbi 93605f333b7SVinod Koul ethernet: ethernet@20000 { 93705f333b7SVinod Koul compatible = "qcom,sm8150-ethqos"; 93805f333b7SVinod Koul reg = <0x0 0x00020000 0x0 0x10000>, 93905f333b7SVinod Koul <0x0 0x00036000 0x0 0x100>; 94005f333b7SVinod Koul reg-names = "stmmaceth", "rgmii"; 94105f333b7SVinod Koul clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 94205f333b7SVinod Koul clocks = <&gcc GCC_EMAC_AXI_CLK>, 94305f333b7SVinod Koul <&gcc GCC_EMAC_SLV_AHB_CLK>, 94405f333b7SVinod Koul <&gcc GCC_EMAC_PTP_CLK>, 94505f333b7SVinod Koul <&gcc GCC_EMAC_RGMII_CLK>; 94605f333b7SVinod Koul interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 94705f333b7SVinod Koul <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 94805f333b7SVinod Koul interrupt-names = "macirq", "eth_lpi"; 94905f333b7SVinod Koul 95005f333b7SVinod Koul power-domains = <&gcc EMAC_GDSC>; 95105f333b7SVinod Koul resets = <&gcc GCC_EMAC_BCR>; 95205f333b7SVinod Koul 95351f748c6SKonrad Dybcio iommus = <&apps_smmu 0x3c0 0x0>; 95405f333b7SVinod Koul 95505f333b7SVinod Koul snps,tso; 95605f333b7SVinod Koul rx-fifo-depth = <4096>; 95705f333b7SVinod Koul tx-fifo-depth = <4096>; 95805f333b7SVinod Koul 95905f333b7SVinod Koul status = "disabled"; 96005f333b7SVinod Koul }; 96105f333b7SVinod Koul 962b53ae6b6SKonrad Dybcio qfprom: efuse@784000 { 963b53ae6b6SKonrad Dybcio compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 964b53ae6b6SKonrad Dybcio reg = <0 0x00784000 0 0x8ff>; 965b53ae6b6SKonrad Dybcio #address-cells = <1>; 966b53ae6b6SKonrad Dybcio #size-cells = <1>; 967b53ae6b6SKonrad Dybcio 968b53ae6b6SKonrad Dybcio gpu_speed_bin: gpu_speed_bin@133 { 969b53ae6b6SKonrad Dybcio reg = <0x133 0x1>; 970b53ae6b6SKonrad Dybcio bits = <5 3>; 971b53ae6b6SKonrad Dybcio }; 972b53ae6b6SKonrad Dybcio }; 97305f333b7SVinod Koul 9749cf3ebd1SCaleb Connolly qupv3_id_0: geniqup@8c0000 { 9759cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 9769cf3ebd1SCaleb Connolly reg = <0x0 0x008c0000 0x0 0x6000>; 9779cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 9789cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 9799cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 9809cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0xc3 0x0>; 9819cf3ebd1SCaleb Connolly #address-cells = <2>; 9829cf3ebd1SCaleb Connolly #size-cells = <2>; 9839cf3ebd1SCaleb Connolly ranges; 9849cf3ebd1SCaleb Connolly status = "disabled"; 98581bee695SCaleb Connolly 98681bee695SCaleb Connolly i2c0: i2c@880000 { 98781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 98881bee695SCaleb Connolly reg = <0 0x00880000 0 0x4000>; 98981bee695SCaleb Connolly clock-names = "se"; 99081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 991abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 992abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_I2C>; 993abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 99481bee695SCaleb Connolly pinctrl-names = "default"; 99581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c0_default>; 99681bee695SCaleb Connolly interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 99781bee695SCaleb Connolly #address-cells = <1>; 99881bee695SCaleb Connolly #size-cells = <0>; 99981bee695SCaleb Connolly status = "disabled"; 100081bee695SCaleb Connolly }; 100181bee695SCaleb Connolly 1002129e1c96SFelipe Balbi spi0: spi@880000 { 1003129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1004f6973229SKonrad Dybcio reg = <0 0x00880000 0 0x4000>; 1005129e1c96SFelipe Balbi reg-names = "se"; 1006129e1c96SFelipe Balbi clock-names = "se"; 1007129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1008abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1009abdd4b7aSFelipe Balbi <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1010abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1011129e1c96SFelipe Balbi pinctrl-names = "default"; 1012129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi0_default>; 1013129e1c96SFelipe Balbi interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1014129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1015129e1c96SFelipe Balbi #address-cells = <1>; 1016129e1c96SFelipe Balbi #size-cells = <0>; 1017129e1c96SFelipe Balbi status = "disabled"; 1018129e1c96SFelipe Balbi }; 1019129e1c96SFelipe Balbi 102081bee695SCaleb Connolly i2c1: i2c@884000 { 102181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 102281bee695SCaleb Connolly reg = <0 0x00884000 0 0x4000>; 102381bee695SCaleb Connolly clock-names = "se"; 102481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1025abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1026abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1027abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 102881bee695SCaleb Connolly pinctrl-names = "default"; 102981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c1_default>; 103081bee695SCaleb Connolly interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 103181bee695SCaleb Connolly #address-cells = <1>; 103281bee695SCaleb Connolly #size-cells = <0>; 103381bee695SCaleb Connolly status = "disabled"; 103481bee695SCaleb Connolly }; 103581bee695SCaleb Connolly 1036129e1c96SFelipe Balbi spi1: spi@884000 { 1037129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1038f6973229SKonrad Dybcio reg = <0 0x00884000 0 0x4000>; 1039129e1c96SFelipe Balbi reg-names = "se"; 1040129e1c96SFelipe Balbi clock-names = "se"; 1041129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1042abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1043abdd4b7aSFelipe Balbi <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1044abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1045129e1c96SFelipe Balbi pinctrl-names = "default"; 1046129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi1_default>; 1047129e1c96SFelipe Balbi interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1048129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1049129e1c96SFelipe Balbi #address-cells = <1>; 1050129e1c96SFelipe Balbi #size-cells = <0>; 1051129e1c96SFelipe Balbi status = "disabled"; 1052129e1c96SFelipe Balbi }; 1053129e1c96SFelipe Balbi 105481bee695SCaleb Connolly i2c2: i2c@888000 { 105581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 105681bee695SCaleb Connolly reg = <0 0x00888000 0 0x4000>; 105781bee695SCaleb Connolly clock-names = "se"; 105881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1059abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1060abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1061abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 106281bee695SCaleb Connolly pinctrl-names = "default"; 106381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c2_default>; 106481bee695SCaleb Connolly interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 106581bee695SCaleb Connolly #address-cells = <1>; 106681bee695SCaleb Connolly #size-cells = <0>; 106781bee695SCaleb Connolly status = "disabled"; 106881bee695SCaleb Connolly }; 106981bee695SCaleb Connolly 1070129e1c96SFelipe Balbi spi2: spi@888000 { 1071129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1072f6973229SKonrad Dybcio reg = <0 0x00888000 0 0x4000>; 1073129e1c96SFelipe Balbi reg-names = "se"; 1074129e1c96SFelipe Balbi clock-names = "se"; 1075129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1076abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1077abdd4b7aSFelipe Balbi <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1078abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1079129e1c96SFelipe Balbi pinctrl-names = "default"; 1080129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi2_default>; 1081129e1c96SFelipe Balbi interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1082129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1083129e1c96SFelipe Balbi #address-cells = <1>; 1084129e1c96SFelipe Balbi #size-cells = <0>; 1085129e1c96SFelipe Balbi status = "disabled"; 1086129e1c96SFelipe Balbi }; 1087129e1c96SFelipe Balbi 108881bee695SCaleb Connolly i2c3: i2c@88c000 { 108981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 109081bee695SCaleb Connolly reg = <0 0x0088c000 0 0x4000>; 109181bee695SCaleb Connolly clock-names = "se"; 109281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1093abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1094abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1095abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 109681bee695SCaleb Connolly pinctrl-names = "default"; 109781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c3_default>; 109881bee695SCaleb Connolly interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 109981bee695SCaleb Connolly #address-cells = <1>; 110081bee695SCaleb Connolly #size-cells = <0>; 110181bee695SCaleb Connolly status = "disabled"; 110281bee695SCaleb Connolly }; 110381bee695SCaleb Connolly 1104129e1c96SFelipe Balbi spi3: spi@88c000 { 1105129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1106f6973229SKonrad Dybcio reg = <0 0x0088c000 0 0x4000>; 1107129e1c96SFelipe Balbi reg-names = "se"; 1108129e1c96SFelipe Balbi clock-names = "se"; 1109129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1110abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1111abdd4b7aSFelipe Balbi <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1112abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1113129e1c96SFelipe Balbi pinctrl-names = "default"; 1114129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi3_default>; 1115129e1c96SFelipe Balbi interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1116129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1117129e1c96SFelipe Balbi #address-cells = <1>; 1118129e1c96SFelipe Balbi #size-cells = <0>; 1119129e1c96SFelipe Balbi status = "disabled"; 1120129e1c96SFelipe Balbi }; 1121129e1c96SFelipe Balbi 112281bee695SCaleb Connolly i2c4: i2c@890000 { 112381bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 112481bee695SCaleb Connolly reg = <0 0x00890000 0 0x4000>; 112581bee695SCaleb Connolly clock-names = "se"; 112681bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1127abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1128abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1129abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 113081bee695SCaleb Connolly pinctrl-names = "default"; 113181bee695SCaleb Connolly pinctrl-0 = <&qup_i2c4_default>; 113281bee695SCaleb Connolly interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 113381bee695SCaleb Connolly #address-cells = <1>; 113481bee695SCaleb Connolly #size-cells = <0>; 113581bee695SCaleb Connolly status = "disabled"; 113681bee695SCaleb Connolly }; 113781bee695SCaleb Connolly 1138129e1c96SFelipe Balbi spi4: spi@890000 { 1139129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1140f6973229SKonrad Dybcio reg = <0 0x00890000 0 0x4000>; 1141129e1c96SFelipe Balbi reg-names = "se"; 1142129e1c96SFelipe Balbi clock-names = "se"; 1143129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1144abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1145abdd4b7aSFelipe Balbi <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1146abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1147129e1c96SFelipe Balbi pinctrl-names = "default"; 1148129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi4_default>; 1149129e1c96SFelipe Balbi interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1150129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1151129e1c96SFelipe Balbi #address-cells = <1>; 1152129e1c96SFelipe Balbi #size-cells = <0>; 1153129e1c96SFelipe Balbi status = "disabled"; 1154129e1c96SFelipe Balbi }; 1155129e1c96SFelipe Balbi 115681bee695SCaleb Connolly i2c5: i2c@894000 { 115781bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 115881bee695SCaleb Connolly reg = <0 0x00894000 0 0x4000>; 115981bee695SCaleb Connolly clock-names = "se"; 116081bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1161abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1162abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1163abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 116481bee695SCaleb Connolly pinctrl-names = "default"; 116581bee695SCaleb Connolly pinctrl-0 = <&qup_i2c5_default>; 116681bee695SCaleb Connolly interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 116781bee695SCaleb Connolly #address-cells = <1>; 116881bee695SCaleb Connolly #size-cells = <0>; 116981bee695SCaleb Connolly status = "disabled"; 117081bee695SCaleb Connolly }; 117181bee695SCaleb Connolly 1172129e1c96SFelipe Balbi spi5: spi@894000 { 1173129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1174f6973229SKonrad Dybcio reg = <0 0x00894000 0 0x4000>; 1175129e1c96SFelipe Balbi reg-names = "se"; 1176129e1c96SFelipe Balbi clock-names = "se"; 1177129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1178abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1179abdd4b7aSFelipe Balbi <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1180abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1181129e1c96SFelipe Balbi pinctrl-names = "default"; 1182129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi5_default>; 1183129e1c96SFelipe Balbi interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1184129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1185129e1c96SFelipe Balbi #address-cells = <1>; 1186129e1c96SFelipe Balbi #size-cells = <0>; 1187129e1c96SFelipe Balbi status = "disabled"; 1188129e1c96SFelipe Balbi }; 1189129e1c96SFelipe Balbi 119081bee695SCaleb Connolly i2c6: i2c@898000 { 119181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 119281bee695SCaleb Connolly reg = <0 0x00898000 0 0x4000>; 119381bee695SCaleb Connolly clock-names = "se"; 119481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1195abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1196abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1197abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 119881bee695SCaleb Connolly pinctrl-names = "default"; 119981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c6_default>; 120081bee695SCaleb Connolly interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 120181bee695SCaleb Connolly #address-cells = <1>; 120281bee695SCaleb Connolly #size-cells = <0>; 120381bee695SCaleb Connolly status = "disabled"; 120481bee695SCaleb Connolly }; 120581bee695SCaleb Connolly 1206129e1c96SFelipe Balbi spi6: spi@898000 { 1207129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1208f6973229SKonrad Dybcio reg = <0 0x00898000 0 0x4000>; 1209129e1c96SFelipe Balbi reg-names = "se"; 1210129e1c96SFelipe Balbi clock-names = "se"; 1211129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1212abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1213abdd4b7aSFelipe Balbi <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1214abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1215129e1c96SFelipe Balbi pinctrl-names = "default"; 1216129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi6_default>; 1217129e1c96SFelipe Balbi interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1218129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1219129e1c96SFelipe Balbi #address-cells = <1>; 1220129e1c96SFelipe Balbi #size-cells = <0>; 1221129e1c96SFelipe Balbi status = "disabled"; 1222129e1c96SFelipe Balbi }; 1223129e1c96SFelipe Balbi 122481bee695SCaleb Connolly i2c7: i2c@89c000 { 122581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 122681bee695SCaleb Connolly reg = <0 0x0089c000 0 0x4000>; 122781bee695SCaleb Connolly clock-names = "se"; 122881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1229abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1230abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1231abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 123281bee695SCaleb Connolly pinctrl-names = "default"; 123381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c7_default>; 1234f9568d22SZeyan Li interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 123581bee695SCaleb Connolly #address-cells = <1>; 123681bee695SCaleb Connolly #size-cells = <0>; 123781bee695SCaleb Connolly status = "disabled"; 123881bee695SCaleb Connolly }; 123981bee695SCaleb Connolly 1240129e1c96SFelipe Balbi spi7: spi@89c000 { 1241129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1242f6973229SKonrad Dybcio reg = <0 0x0089c000 0 0x4000>; 1243129e1c96SFelipe Balbi reg-names = "se"; 1244129e1c96SFelipe Balbi clock-names = "se"; 1245129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1246abdd4b7aSFelipe Balbi dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1247abdd4b7aSFelipe Balbi <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1248abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1249129e1c96SFelipe Balbi pinctrl-names = "default"; 1250129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi7_default>; 1251129e1c96SFelipe Balbi interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1252129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1253129e1c96SFelipe Balbi #address-cells = <1>; 1254129e1c96SFelipe Balbi #size-cells = <0>; 1255129e1c96SFelipe Balbi status = "disabled"; 1256129e1c96SFelipe Balbi }; 12579cf3ebd1SCaleb Connolly }; 12589cf3ebd1SCaleb Connolly 125905006290SFelipe Balbi gpi_dma1: dma-controller@a00000 { 1260e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1261f6973229SKonrad Dybcio reg = <0 0x00a00000 0 0x60000>; 126205006290SFelipe Balbi interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 126305006290SFelipe Balbi <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 126405006290SFelipe Balbi <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 126505006290SFelipe Balbi <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 126605006290SFelipe Balbi <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 126705006290SFelipe Balbi <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 126805006290SFelipe Balbi <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 126905006290SFelipe Balbi <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 127005006290SFelipe Balbi <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 127105006290SFelipe Balbi <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 127205006290SFelipe Balbi <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 127305006290SFelipe Balbi <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 127405006290SFelipe Balbi <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 127505006290SFelipe Balbi dma-channels = <13>; 127605006290SFelipe Balbi dma-channel-mask = <0xfa>; 127705006290SFelipe Balbi iommus = <&apps_smmu 0x0616 0x0>; 127805006290SFelipe Balbi #dma-cells = <3>; 127905006290SFelipe Balbi status = "disabled"; 128005006290SFelipe Balbi }; 128105006290SFelipe Balbi 1282e13c6d14SVinod Koul qupv3_id_1: geniqup@ac0000 { 1283e13c6d14SVinod Koul compatible = "qcom,geni-se-qup"; 1284e13c6d14SVinod Koul reg = <0x0 0x00ac0000 0x0 0x6000>; 1285e13c6d14SVinod Koul clock-names = "m-ahb", "s-ahb"; 1286d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1287d6f55763SVinod Koul <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 12889cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x603 0x0>; 1289e13c6d14SVinod Koul #address-cells = <2>; 1290e13c6d14SVinod Koul #size-cells = <2>; 1291e13c6d14SVinod Koul ranges; 1292e13c6d14SVinod Koul status = "disabled"; 1293e13c6d14SVinod Koul 129481bee695SCaleb Connolly i2c8: i2c@a80000 { 129581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 129681bee695SCaleb Connolly reg = <0 0x00a80000 0 0x4000>; 129781bee695SCaleb Connolly clock-names = "se"; 129881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1299abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1300abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1301abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 130281bee695SCaleb Connolly pinctrl-names = "default"; 130381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c8_default>; 130481bee695SCaleb Connolly interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 130581bee695SCaleb Connolly #address-cells = <1>; 130681bee695SCaleb Connolly #size-cells = <0>; 130781bee695SCaleb Connolly status = "disabled"; 130881bee695SCaleb Connolly }; 130981bee695SCaleb Connolly 1310129e1c96SFelipe Balbi spi8: spi@a80000 { 1311129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1312f6973229SKonrad Dybcio reg = <0 0x00a80000 0 0x4000>; 1313129e1c96SFelipe Balbi reg-names = "se"; 1314129e1c96SFelipe Balbi clock-names = "se"; 1315129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1316abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1317abdd4b7aSFelipe Balbi <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1318abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1319129e1c96SFelipe Balbi pinctrl-names = "default"; 1320129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi8_default>; 1321129e1c96SFelipe Balbi interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1322129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1323129e1c96SFelipe Balbi #address-cells = <1>; 1324129e1c96SFelipe Balbi #size-cells = <0>; 1325129e1c96SFelipe Balbi status = "disabled"; 1326129e1c96SFelipe Balbi }; 1327129e1c96SFelipe Balbi 132881bee695SCaleb Connolly i2c9: i2c@a84000 { 132981bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 133081bee695SCaleb Connolly reg = <0 0x00a84000 0 0x4000>; 133181bee695SCaleb Connolly clock-names = "se"; 133281bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1333abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1334abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1335abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 133681bee695SCaleb Connolly pinctrl-names = "default"; 133781bee695SCaleb Connolly pinctrl-0 = <&qup_i2c9_default>; 133881bee695SCaleb Connolly interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 133981bee695SCaleb Connolly #address-cells = <1>; 134081bee695SCaleb Connolly #size-cells = <0>; 134181bee695SCaleb Connolly status = "disabled"; 134281bee695SCaleb Connolly }; 134381bee695SCaleb Connolly 1344129e1c96SFelipe Balbi spi9: spi@a84000 { 1345129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1346f6973229SKonrad Dybcio reg = <0 0x00a84000 0 0x4000>; 1347129e1c96SFelipe Balbi reg-names = "se"; 1348129e1c96SFelipe Balbi clock-names = "se"; 1349129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1350abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1351abdd4b7aSFelipe Balbi <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1352abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1353129e1c96SFelipe Balbi pinctrl-names = "default"; 1354129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi9_default>; 1355129e1c96SFelipe Balbi interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1356129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1357129e1c96SFelipe Balbi #address-cells = <1>; 1358129e1c96SFelipe Balbi #size-cells = <0>; 1359129e1c96SFelipe Balbi status = "disabled"; 1360129e1c96SFelipe Balbi }; 1361129e1c96SFelipe Balbi 13629ebaa4a8SBartosz Golaszewski uart9: serial@a84000 { 136310d900a8SBartosz Golaszewski compatible = "qcom,geni-uart"; 136410d900a8SBartosz Golaszewski reg = <0x0 0x00a84000 0x0 0x4000>; 136510d900a8SBartosz Golaszewski clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 136610d900a8SBartosz Golaszewski clock-names = "se"; 136710d900a8SBartosz Golaszewski pinctrl-0 = <&qup_uart9_default>; 136810d900a8SBartosz Golaszewski pinctrl-names = "default"; 136910d900a8SBartosz Golaszewski interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 137010d900a8SBartosz Golaszewski status = "disabled"; 137110d900a8SBartosz Golaszewski }; 137210d900a8SBartosz Golaszewski 137381bee695SCaleb Connolly i2c10: i2c@a88000 { 137481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 137581bee695SCaleb Connolly reg = <0 0x00a88000 0 0x4000>; 137681bee695SCaleb Connolly clock-names = "se"; 137781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1378abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1379abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1380abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 138181bee695SCaleb Connolly pinctrl-names = "default"; 138281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c10_default>; 138381bee695SCaleb Connolly interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 138481bee695SCaleb Connolly #address-cells = <1>; 138581bee695SCaleb Connolly #size-cells = <0>; 138681bee695SCaleb Connolly status = "disabled"; 138781bee695SCaleb Connolly }; 138881bee695SCaleb Connolly 1389129e1c96SFelipe Balbi spi10: spi@a88000 { 1390129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1391f6973229SKonrad Dybcio reg = <0 0x00a88000 0 0x4000>; 1392129e1c96SFelipe Balbi reg-names = "se"; 1393129e1c96SFelipe Balbi clock-names = "se"; 1394129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1395abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1396abdd4b7aSFelipe Balbi <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1397abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1398129e1c96SFelipe Balbi pinctrl-names = "default"; 1399129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi10_default>; 1400129e1c96SFelipe Balbi interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1401129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1402129e1c96SFelipe Balbi #address-cells = <1>; 1403129e1c96SFelipe Balbi #size-cells = <0>; 1404129e1c96SFelipe Balbi status = "disabled"; 1405129e1c96SFelipe Balbi }; 1406129e1c96SFelipe Balbi 140781bee695SCaleb Connolly i2c11: i2c@a8c000 { 140881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 140981bee695SCaleb Connolly reg = <0 0x00a8c000 0 0x4000>; 141081bee695SCaleb Connolly clock-names = "se"; 141181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1412abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1413abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1414abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 141581bee695SCaleb Connolly pinctrl-names = "default"; 141681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c11_default>; 141781bee695SCaleb Connolly interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 141881bee695SCaleb Connolly #address-cells = <1>; 141981bee695SCaleb Connolly #size-cells = <0>; 142081bee695SCaleb Connolly status = "disabled"; 142181bee695SCaleb Connolly }; 142281bee695SCaleb Connolly 1423129e1c96SFelipe Balbi spi11: spi@a8c000 { 1424129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1425f6973229SKonrad Dybcio reg = <0 0x00a8c000 0 0x4000>; 1426129e1c96SFelipe Balbi reg-names = "se"; 1427129e1c96SFelipe Balbi clock-names = "se"; 1428129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1429abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1430abdd4b7aSFelipe Balbi <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1431abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1432129e1c96SFelipe Balbi pinctrl-names = "default"; 1433129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi11_default>; 1434129e1c96SFelipe Balbi interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1435129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1436129e1c96SFelipe Balbi #address-cells = <1>; 1437129e1c96SFelipe Balbi #size-cells = <0>; 1438129e1c96SFelipe Balbi status = "disabled"; 1439129e1c96SFelipe Balbi }; 1440129e1c96SFelipe Balbi 1441e13c6d14SVinod Koul uart2: serial@a90000 { 1442e13c6d14SVinod Koul compatible = "qcom,geni-debug-uart"; 1443e13c6d14SVinod Koul reg = <0x0 0x00a90000 0x0 0x4000>; 1444e13c6d14SVinod Koul clock-names = "se"; 1445d6f55763SVinod Koul clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1446e13c6d14SVinod Koul interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1447e13c6d14SVinod Koul status = "disabled"; 1448e13c6d14SVinod Koul }; 144981bee695SCaleb Connolly 145081bee695SCaleb Connolly i2c12: i2c@a90000 { 145181bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 145281bee695SCaleb Connolly reg = <0 0x00a90000 0 0x4000>; 145381bee695SCaleb Connolly clock-names = "se"; 145481bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1455abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1456abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1457abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 145881bee695SCaleb Connolly pinctrl-names = "default"; 145981bee695SCaleb Connolly pinctrl-0 = <&qup_i2c12_default>; 146081bee695SCaleb Connolly interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 146181bee695SCaleb Connolly #address-cells = <1>; 146281bee695SCaleb Connolly #size-cells = <0>; 146381bee695SCaleb Connolly status = "disabled"; 146481bee695SCaleb Connolly }; 146581bee695SCaleb Connolly 1466129e1c96SFelipe Balbi spi12: spi@a90000 { 1467129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1468f6973229SKonrad Dybcio reg = <0 0x00a90000 0 0x4000>; 1469129e1c96SFelipe Balbi reg-names = "se"; 1470129e1c96SFelipe Balbi clock-names = "se"; 1471129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1472abdd4b7aSFelipe Balbi dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1473abdd4b7aSFelipe Balbi <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1474abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1475129e1c96SFelipe Balbi pinctrl-names = "default"; 1476129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi12_default>; 1477129e1c96SFelipe Balbi interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1478129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1479129e1c96SFelipe Balbi #address-cells = <1>; 1480129e1c96SFelipe Balbi #size-cells = <0>; 1481129e1c96SFelipe Balbi status = "disabled"; 1482129e1c96SFelipe Balbi }; 1483129e1c96SFelipe Balbi 148481bee695SCaleb Connolly i2c16: i2c@94000 { 148581bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 1486f6973229SKonrad Dybcio reg = <0 0x00094000 0 0x4000>; 148781bee695SCaleb Connolly clock-names = "se"; 148881bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1489abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1490abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1491abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 149281bee695SCaleb Connolly pinctrl-names = "default"; 149381bee695SCaleb Connolly pinctrl-0 = <&qup_i2c16_default>; 149481bee695SCaleb Connolly interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 149581bee695SCaleb Connolly #address-cells = <1>; 149681bee695SCaleb Connolly #size-cells = <0>; 149781bee695SCaleb Connolly status = "disabled"; 149881bee695SCaleb Connolly }; 1499129e1c96SFelipe Balbi 1500129e1c96SFelipe Balbi spi16: spi@a94000 { 1501129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1502f6973229SKonrad Dybcio reg = <0 0x00a94000 0 0x4000>; 1503129e1c96SFelipe Balbi reg-names = "se"; 1504129e1c96SFelipe Balbi clock-names = "se"; 1505129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1506abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1507abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1508abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1509129e1c96SFelipe Balbi pinctrl-names = "default"; 1510129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi16_default>; 1511129e1c96SFelipe Balbi interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1512129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1513129e1c96SFelipe Balbi #address-cells = <1>; 1514129e1c96SFelipe Balbi #size-cells = <0>; 1515129e1c96SFelipe Balbi status = "disabled"; 1516129e1c96SFelipe Balbi }; 1517e13c6d14SVinod Koul }; 1518e13c6d14SVinod Koul 151905006290SFelipe Balbi gpi_dma2: dma-controller@c00000 { 1520e7e24786SRichard Acayan compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1521f6973229SKonrad Dybcio reg = <0 0x00c00000 0 0x60000>; 152205006290SFelipe Balbi interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 152305006290SFelipe Balbi <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 152405006290SFelipe Balbi <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 152505006290SFelipe Balbi <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 152605006290SFelipe Balbi <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 152705006290SFelipe Balbi <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 152805006290SFelipe Balbi <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 152905006290SFelipe Balbi <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 153005006290SFelipe Balbi <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 153105006290SFelipe Balbi <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 153205006290SFelipe Balbi <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 153305006290SFelipe Balbi <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 153405006290SFelipe Balbi <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 153505006290SFelipe Balbi dma-channels = <13>; 153605006290SFelipe Balbi dma-channel-mask = <0xfa>; 153705006290SFelipe Balbi iommus = <&apps_smmu 0x07b6 0x0>; 153805006290SFelipe Balbi #dma-cells = <3>; 153905006290SFelipe Balbi status = "disabled"; 154005006290SFelipe Balbi }; 154105006290SFelipe Balbi 15429cf3ebd1SCaleb Connolly qupv3_id_2: geniqup@cc0000 { 15439cf3ebd1SCaleb Connolly compatible = "qcom,geni-se-qup"; 15449cf3ebd1SCaleb Connolly reg = <0x0 0x00cc0000 0x0 0x6000>; 15459cf3ebd1SCaleb Connolly 15469cf3ebd1SCaleb Connolly clock-names = "m-ahb", "s-ahb"; 15479cf3ebd1SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 15489cf3ebd1SCaleb Connolly <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 15499cf3ebd1SCaleb Connolly iommus = <&apps_smmu 0x7a3 0x0>; 15509cf3ebd1SCaleb Connolly #address-cells = <2>; 15519cf3ebd1SCaleb Connolly #size-cells = <2>; 15529cf3ebd1SCaleb Connolly ranges; 15539cf3ebd1SCaleb Connolly status = "disabled"; 155481bee695SCaleb Connolly 155581bee695SCaleb Connolly i2c17: i2c@c80000 { 155681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 155781bee695SCaleb Connolly reg = <0 0x00c80000 0 0x4000>; 155881bee695SCaleb Connolly clock-names = "se"; 155981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1560abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1561abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1562abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 156381bee695SCaleb Connolly pinctrl-names = "default"; 156481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c17_default>; 156581bee695SCaleb Connolly interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 156681bee695SCaleb Connolly #address-cells = <1>; 156781bee695SCaleb Connolly #size-cells = <0>; 156881bee695SCaleb Connolly status = "disabled"; 156981bee695SCaleb Connolly }; 157081bee695SCaleb Connolly 1571129e1c96SFelipe Balbi spi17: spi@c80000 { 1572129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1573f6973229SKonrad Dybcio reg = <0 0x00c80000 0 0x4000>; 1574129e1c96SFelipe Balbi reg-names = "se"; 1575129e1c96SFelipe Balbi clock-names = "se"; 1576129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1577abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1578abdd4b7aSFelipe Balbi <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1579abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1580129e1c96SFelipe Balbi pinctrl-names = "default"; 1581129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi17_default>; 1582129e1c96SFelipe Balbi interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1583129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1584129e1c96SFelipe Balbi #address-cells = <1>; 1585129e1c96SFelipe Balbi #size-cells = <0>; 1586129e1c96SFelipe Balbi status = "disabled"; 1587129e1c96SFelipe Balbi }; 1588129e1c96SFelipe Balbi 158981bee695SCaleb Connolly i2c18: i2c@c84000 { 159081bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 159181bee695SCaleb Connolly reg = <0 0x00c84000 0 0x4000>; 159281bee695SCaleb Connolly clock-names = "se"; 159381bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1594abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1595abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1596abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 159781bee695SCaleb Connolly pinctrl-names = "default"; 159881bee695SCaleb Connolly pinctrl-0 = <&qup_i2c18_default>; 159981bee695SCaleb Connolly interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 160081bee695SCaleb Connolly #address-cells = <1>; 160181bee695SCaleb Connolly #size-cells = <0>; 160281bee695SCaleb Connolly status = "disabled"; 160381bee695SCaleb Connolly }; 160481bee695SCaleb Connolly 1605129e1c96SFelipe Balbi spi18: spi@c84000 { 1606129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1607f6973229SKonrad Dybcio reg = <0 0x00c84000 0 0x4000>; 1608129e1c96SFelipe Balbi reg-names = "se"; 1609129e1c96SFelipe Balbi clock-names = "se"; 1610129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1611abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1612abdd4b7aSFelipe Balbi <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1613abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1614129e1c96SFelipe Balbi pinctrl-names = "default"; 1615129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi18_default>; 1616129e1c96SFelipe Balbi interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1617129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1618129e1c96SFelipe Balbi #address-cells = <1>; 1619129e1c96SFelipe Balbi #size-cells = <0>; 1620129e1c96SFelipe Balbi status = "disabled"; 1621129e1c96SFelipe Balbi }; 1622129e1c96SFelipe Balbi 162381bee695SCaleb Connolly i2c19: i2c@c88000 { 162481bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 162581bee695SCaleb Connolly reg = <0 0x00c88000 0 0x4000>; 162681bee695SCaleb Connolly clock-names = "se"; 162781bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1628abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1629abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1630abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 163181bee695SCaleb Connolly pinctrl-names = "default"; 163281bee695SCaleb Connolly pinctrl-0 = <&qup_i2c19_default>; 163381bee695SCaleb Connolly interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 163481bee695SCaleb Connolly #address-cells = <1>; 163581bee695SCaleb Connolly #size-cells = <0>; 163681bee695SCaleb Connolly status = "disabled"; 163781bee695SCaleb Connolly }; 163881bee695SCaleb Connolly 1639129e1c96SFelipe Balbi spi19: spi@c88000 { 1640129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1641f6973229SKonrad Dybcio reg = <0 0x00c88000 0 0x4000>; 1642129e1c96SFelipe Balbi reg-names = "se"; 1643129e1c96SFelipe Balbi clock-names = "se"; 1644129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1645abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1646abdd4b7aSFelipe Balbi <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1647abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1648129e1c96SFelipe Balbi pinctrl-names = "default"; 1649129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi19_default>; 1650129e1c96SFelipe Balbi interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1651129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1652129e1c96SFelipe Balbi #address-cells = <1>; 1653129e1c96SFelipe Balbi #size-cells = <0>; 1654129e1c96SFelipe Balbi status = "disabled"; 1655129e1c96SFelipe Balbi }; 1656129e1c96SFelipe Balbi 165781bee695SCaleb Connolly i2c13: i2c@c8c000 { 165881bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 165981bee695SCaleb Connolly reg = <0 0x00c8c000 0 0x4000>; 166081bee695SCaleb Connolly clock-names = "se"; 166181bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1662abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1663abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1664abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 166581bee695SCaleb Connolly pinctrl-names = "default"; 166681bee695SCaleb Connolly pinctrl-0 = <&qup_i2c13_default>; 166781bee695SCaleb Connolly interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 166881bee695SCaleb Connolly #address-cells = <1>; 166981bee695SCaleb Connolly #size-cells = <0>; 167081bee695SCaleb Connolly status = "disabled"; 167181bee695SCaleb Connolly }; 167281bee695SCaleb Connolly 1673129e1c96SFelipe Balbi spi13: spi@c8c000 { 1674129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1675f6973229SKonrad Dybcio reg = <0 0x00c8c000 0 0x4000>; 1676129e1c96SFelipe Balbi reg-names = "se"; 1677129e1c96SFelipe Balbi clock-names = "se"; 1678129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1679abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1680abdd4b7aSFelipe Balbi <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1681abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1682129e1c96SFelipe Balbi pinctrl-names = "default"; 1683129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi13_default>; 1684129e1c96SFelipe Balbi interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1685129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1686129e1c96SFelipe Balbi #address-cells = <1>; 1687129e1c96SFelipe Balbi #size-cells = <0>; 1688129e1c96SFelipe Balbi status = "disabled"; 1689129e1c96SFelipe Balbi }; 1690129e1c96SFelipe Balbi 169181bee695SCaleb Connolly i2c14: i2c@c90000 { 169281bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 169381bee695SCaleb Connolly reg = <0 0x00c90000 0 0x4000>; 169481bee695SCaleb Connolly clock-names = "se"; 169581bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1696abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1697abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1698abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 169981bee695SCaleb Connolly pinctrl-names = "default"; 170081bee695SCaleb Connolly pinctrl-0 = <&qup_i2c14_default>; 170181bee695SCaleb Connolly interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 170281bee695SCaleb Connolly #address-cells = <1>; 170381bee695SCaleb Connolly #size-cells = <0>; 170481bee695SCaleb Connolly status = "disabled"; 170581bee695SCaleb Connolly }; 170681bee695SCaleb Connolly 1707129e1c96SFelipe Balbi spi14: spi@c90000 { 1708129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1709f6973229SKonrad Dybcio reg = <0 0x00c90000 0 0x4000>; 1710129e1c96SFelipe Balbi reg-names = "se"; 1711129e1c96SFelipe Balbi clock-names = "se"; 1712129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1713abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1714abdd4b7aSFelipe Balbi <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1715abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1716129e1c96SFelipe Balbi pinctrl-names = "default"; 1717129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi14_default>; 1718129e1c96SFelipe Balbi interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1719129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1720129e1c96SFelipe Balbi #address-cells = <1>; 1721129e1c96SFelipe Balbi #size-cells = <0>; 1722129e1c96SFelipe Balbi status = "disabled"; 1723129e1c96SFelipe Balbi }; 1724129e1c96SFelipe Balbi 172581bee695SCaleb Connolly i2c15: i2c@c94000 { 172681bee695SCaleb Connolly compatible = "qcom,geni-i2c"; 172781bee695SCaleb Connolly reg = <0 0x00c94000 0 0x4000>; 172881bee695SCaleb Connolly clock-names = "se"; 172981bee695SCaleb Connolly clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1730abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1731abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1732abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 173381bee695SCaleb Connolly pinctrl-names = "default"; 173481bee695SCaleb Connolly pinctrl-0 = <&qup_i2c15_default>; 173581bee695SCaleb Connolly interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 173681bee695SCaleb Connolly #address-cells = <1>; 173781bee695SCaleb Connolly #size-cells = <0>; 173881bee695SCaleb Connolly status = "disabled"; 173981bee695SCaleb Connolly }; 1740129e1c96SFelipe Balbi 1741129e1c96SFelipe Balbi spi15: spi@c94000 { 1742129e1c96SFelipe Balbi compatible = "qcom,geni-spi"; 1743f6973229SKonrad Dybcio reg = <0 0x00c94000 0 0x4000>; 1744129e1c96SFelipe Balbi reg-names = "se"; 1745129e1c96SFelipe Balbi clock-names = "se"; 1746129e1c96SFelipe Balbi clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1747abdd4b7aSFelipe Balbi dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1748abdd4b7aSFelipe Balbi <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1749abdd4b7aSFelipe Balbi dma-names = "tx", "rx"; 1750129e1c96SFelipe Balbi pinctrl-names = "default"; 1751129e1c96SFelipe Balbi pinctrl-0 = <&qup_spi15_default>; 1752129e1c96SFelipe Balbi interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1753129e1c96SFelipe Balbi spi-max-frequency = <50000000>; 1754129e1c96SFelipe Balbi #address-cells = <1>; 1755129e1c96SFelipe Balbi #size-cells = <0>; 1756129e1c96SFelipe Balbi status = "disabled"; 1757129e1c96SFelipe Balbi }; 17589cf3ebd1SCaleb Connolly }; 17599cf3ebd1SCaleb Connolly 176071a2fc6eSJonathan Marek config_noc: interconnect@1500000 { 176171a2fc6eSJonathan Marek compatible = "qcom,sm8150-config-noc"; 176271a2fc6eSJonathan Marek reg = <0 0x01500000 0 0x7400>; 176397c28902SAbel Vesa #interconnect-cells = <2>; 176471a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 176571a2fc6eSJonathan Marek }; 176671a2fc6eSJonathan Marek 176771a2fc6eSJonathan Marek system_noc: interconnect@1620000 { 176871a2fc6eSJonathan Marek compatible = "qcom,sm8150-system-noc"; 176971a2fc6eSJonathan Marek reg = <0 0x01620000 0 0x19400>; 177097c28902SAbel Vesa #interconnect-cells = <2>; 177171a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 177271a2fc6eSJonathan Marek }; 177371a2fc6eSJonathan Marek 177471a2fc6eSJonathan Marek mc_virt: interconnect@163a000 { 177571a2fc6eSJonathan Marek compatible = "qcom,sm8150-mc-virt"; 177671a2fc6eSJonathan Marek reg = <0 0x0163a000 0 0x1000>; 177797c28902SAbel Vesa #interconnect-cells = <2>; 177871a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 177971a2fc6eSJonathan Marek }; 178071a2fc6eSJonathan Marek 178171a2fc6eSJonathan Marek aggre1_noc: interconnect@16e0000 { 178271a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre1-noc"; 178371a2fc6eSJonathan Marek reg = <0 0x016e0000 0 0xd080>; 178497c28902SAbel Vesa #interconnect-cells = <2>; 178571a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 178671a2fc6eSJonathan Marek }; 178771a2fc6eSJonathan Marek 178871a2fc6eSJonathan Marek aggre2_noc: interconnect@1700000 { 178971a2fc6eSJonathan Marek compatible = "qcom,sm8150-aggre2-noc"; 179071a2fc6eSJonathan Marek reg = <0 0x01700000 0 0x20000>; 179197c28902SAbel Vesa #interconnect-cells = <2>; 179271a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 179371a2fc6eSJonathan Marek }; 179471a2fc6eSJonathan Marek 179571a2fc6eSJonathan Marek compute_noc: interconnect@1720000 { 179671a2fc6eSJonathan Marek compatible = "qcom,sm8150-compute-noc"; 179771a2fc6eSJonathan Marek reg = <0 0x01720000 0 0x7000>; 179897c28902SAbel Vesa #interconnect-cells = <2>; 179971a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 180071a2fc6eSJonathan Marek }; 180171a2fc6eSJonathan Marek 180271a2fc6eSJonathan Marek mmss_noc: interconnect@1740000 { 180371a2fc6eSJonathan Marek compatible = "qcom,sm8150-mmss-noc"; 180471a2fc6eSJonathan Marek reg = <0 0x01740000 0 0x1c100>; 180597c28902SAbel Vesa #interconnect-cells = <2>; 180671a2fc6eSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 180771a2fc6eSJonathan Marek }; 180871a2fc6eSJonathan Marek 1809bb1f7cf6SSouradeep Chowdhury system-cache-controller@9200000 { 1810bb1f7cf6SSouradeep Chowdhury compatible = "qcom,sm8150-llcc"; 1811c5ccf8d3SManivannan Sadhasivam reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1812c5ccf8d3SManivannan Sadhasivam <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1813c5ccf8d3SManivannan Sadhasivam <0 0x09600000 0 0x50000>; 1814c5ccf8d3SManivannan Sadhasivam reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1815c5ccf8d3SManivannan Sadhasivam "llcc3_base", "llcc_broadcast_base"; 1816bb1f7cf6SSouradeep Chowdhury interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1817bb1f7cf6SSouradeep Chowdhury }; 1818bb1f7cf6SSouradeep Chowdhury 1819d4b94c82SSouradeep Chowdhury dma@10a2000 { 1820d4b94c82SSouradeep Chowdhury compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1821d4b94c82SSouradeep Chowdhury reg = <0x0 0x010a2000 0x0 0x1000>, 1822d4b94c82SSouradeep Chowdhury <0x0 0x010ad000 0x0 0x3000>; 1823d4b94c82SSouradeep Chowdhury }; 1824d4b94c82SSouradeep Chowdhury 1825a1c86c68SBhupesh Sharma pcie0: pci@1c00000 { 18267df52233SKrzysztof Kozlowski compatible = "qcom,pcie-sm8150"; 1827a1c86c68SBhupesh Sharma reg = <0 0x01c00000 0 0x3000>, 1828a1c86c68SBhupesh Sharma <0 0x60000000 0 0xf1d>, 1829a1c86c68SBhupesh Sharma <0 0x60000f20 0 0xa8>, 1830a1c86c68SBhupesh Sharma <0 0x60001000 0 0x1000>, 1831a1c86c68SBhupesh Sharma <0 0x60100000 0 0x100000>; 1832a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1833a1c86c68SBhupesh Sharma device_type = "pci"; 1834a1c86c68SBhupesh Sharma linux,pci-domain = <0>; 1835a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1836a1c86c68SBhupesh Sharma num-lanes = <1>; 1837a1c86c68SBhupesh Sharma 1838a1c86c68SBhupesh Sharma #address-cells = <3>; 1839a1c86c68SBhupesh Sharma #size-cells = <2>; 1840a1c86c68SBhupesh Sharma 1841422b110bSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1842422b110bSManivannan Sadhasivam <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1843a1c86c68SBhupesh Sharma 1844a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1845a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1846a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1847a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1848a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1849a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1850a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1851a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1852a1c86c68SBhupesh Sharma 1853a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1854a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_AUX_CLK>, 1855a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1856a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1857a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1858a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1859a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1860a1c86c68SBhupesh Sharma clock-names = "pipe", 1861a1c86c68SBhupesh Sharma "aux", 1862a1c86c68SBhupesh Sharma "cfg", 1863a1c86c68SBhupesh Sharma "bus_master", 1864a1c86c68SBhupesh Sharma "bus_slave", 1865a1c86c68SBhupesh Sharma "slave_q2a", 1866a1c86c68SBhupesh Sharma "tbu"; 1867a1c86c68SBhupesh Sharma 1868a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1869a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1d81 0x1>; 1870a1c86c68SBhupesh Sharma 1871a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_BCR>; 1872a1c86c68SBhupesh Sharma reset-names = "pci"; 1873a1c86c68SBhupesh Sharma 1874a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_0_GDSC>; 1875a1c86c68SBhupesh Sharma 1876a1c86c68SBhupesh Sharma phys = <&pcie0_lane>; 1877a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1878a1c86c68SBhupesh Sharma 1879d2a519c7SKrzysztof Kozlowski perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1880*9f31b114SKrzysztof Kozlowski wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1881a1c86c68SBhupesh Sharma 1882a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1883a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie0_default_state>; 1884a1c86c68SBhupesh Sharma 1885a1c86c68SBhupesh Sharma status = "disabled"; 1886a1c86c68SBhupesh Sharma }; 1887a1c86c68SBhupesh Sharma 1888a1c86c68SBhupesh Sharma pcie0_phy: phy@1c06000 { 1889a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1890a1c86c68SBhupesh Sharma reg = <0 0x01c06000 0 0x1c0>; 1891a1c86c68SBhupesh Sharma #address-cells = <2>; 1892a1c86c68SBhupesh Sharma #size-cells = <2>; 1893a1c86c68SBhupesh Sharma ranges; 1894a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1895a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 18964ac3d9afSDmitry Baryshkov <&gcc GCC_PCIE_0_CLKREF_CLK>, 1897a1c86c68SBhupesh Sharma <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 18984ac3d9afSDmitry Baryshkov clock-names = "aux", 18994ac3d9afSDmitry Baryshkov "cfg_ahb", 19004ac3d9afSDmitry Baryshkov "ref", 19014ac3d9afSDmitry Baryshkov "refgen"; 1902a1c86c68SBhupesh Sharma 1903a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1904a1c86c68SBhupesh Sharma reset-names = "phy"; 1905a1c86c68SBhupesh Sharma 1906a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1907a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 1908a1c86c68SBhupesh Sharma 1909a1c86c68SBhupesh Sharma status = "disabled"; 1910a1c86c68SBhupesh Sharma 1911a1c86c68SBhupesh Sharma pcie0_lane: phy@1c06200 { 1912f6973229SKonrad Dybcio reg = <0 0x01c06200 0 0x170>, /* tx */ 1913f6973229SKonrad Dybcio <0 0x01c06400 0 0x200>, /* rx */ 1914f6973229SKonrad Dybcio <0 0x01c06800 0 0x1f0>, /* pcs */ 1915f6973229SKonrad Dybcio <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1916a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1917a1c86c68SBhupesh Sharma clock-names = "pipe0"; 1918a1c86c68SBhupesh Sharma 1919a1c86c68SBhupesh Sharma #phy-cells = <0>; 1920a1c86c68SBhupesh Sharma clock-output-names = "pcie_0_pipe_clk"; 1921a1c86c68SBhupesh Sharma }; 1922a1c86c68SBhupesh Sharma }; 1923a1c86c68SBhupesh Sharma 1924a1c86c68SBhupesh Sharma pcie1: pci@1c08000 { 19257df52233SKrzysztof Kozlowski compatible = "qcom,pcie-sm8150"; 1926a1c86c68SBhupesh Sharma reg = <0 0x01c08000 0 0x3000>, 1927a1c86c68SBhupesh Sharma <0 0x40000000 0 0xf1d>, 1928a1c86c68SBhupesh Sharma <0 0x40000f20 0 0xa8>, 1929a1c86c68SBhupesh Sharma <0 0x40001000 0 0x1000>, 1930a1c86c68SBhupesh Sharma <0 0x40100000 0 0x100000>; 1931a1c86c68SBhupesh Sharma reg-names = "parf", "dbi", "elbi", "atu", "config"; 1932a1c86c68SBhupesh Sharma device_type = "pci"; 1933a1c86c68SBhupesh Sharma linux,pci-domain = <1>; 1934a1c86c68SBhupesh Sharma bus-range = <0x00 0xff>; 1935a1c86c68SBhupesh Sharma num-lanes = <2>; 1936a1c86c68SBhupesh Sharma 1937a1c86c68SBhupesh Sharma #address-cells = <3>; 1938a1c86c68SBhupesh Sharma #size-cells = <2>; 1939a1c86c68SBhupesh Sharma 1940422b110bSManivannan Sadhasivam ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1941a1c86c68SBhupesh Sharma <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1942a1c86c68SBhupesh Sharma 1943a1c86c68SBhupesh Sharma interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1944a1c86c68SBhupesh Sharma interrupt-names = "msi"; 1945a1c86c68SBhupesh Sharma #interrupt-cells = <1>; 1946a1c86c68SBhupesh Sharma interrupt-map-mask = <0 0 0 0x7>; 1947a1c86c68SBhupesh Sharma interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1948a1c86c68SBhupesh Sharma <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1949a1c86c68SBhupesh Sharma <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1950a1c86c68SBhupesh Sharma <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1951a1c86c68SBhupesh Sharma 1952a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1953a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_AUX_CLK>, 1954a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1955a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1956a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1957a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1958a1c86c68SBhupesh Sharma <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1959a1c86c68SBhupesh Sharma clock-names = "pipe", 1960a1c86c68SBhupesh Sharma "aux", 1961a1c86c68SBhupesh Sharma "cfg", 1962a1c86c68SBhupesh Sharma "bus_master", 1963a1c86c68SBhupesh Sharma "bus_slave", 1964a1c86c68SBhupesh Sharma "slave_q2a", 1965a1c86c68SBhupesh Sharma "tbu"; 1966a1c86c68SBhupesh Sharma 1967a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1968a1c86c68SBhupesh Sharma assigned-clock-rates = <19200000>; 1969a1c86c68SBhupesh Sharma 1970a1c86c68SBhupesh Sharma iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1971a1c86c68SBhupesh Sharma <0x100 &apps_smmu 0x1e01 0x1>; 1972a1c86c68SBhupesh Sharma 1973a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_BCR>; 1974a1c86c68SBhupesh Sharma reset-names = "pci"; 1975a1c86c68SBhupesh Sharma 1976a1c86c68SBhupesh Sharma power-domains = <&gcc PCIE_1_GDSC>; 1977a1c86c68SBhupesh Sharma 1978a1c86c68SBhupesh Sharma phys = <&pcie1_lane>; 1979a1c86c68SBhupesh Sharma phy-names = "pciephy"; 1980a1c86c68SBhupesh Sharma 1981d2a519c7SKrzysztof Kozlowski perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1982a1c86c68SBhupesh Sharma enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1983a1c86c68SBhupesh Sharma 1984a1c86c68SBhupesh Sharma pinctrl-names = "default"; 1985a1c86c68SBhupesh Sharma pinctrl-0 = <&pcie1_default_state>; 1986a1c86c68SBhupesh Sharma 1987a1c86c68SBhupesh Sharma status = "disabled"; 1988a1c86c68SBhupesh Sharma }; 1989a1c86c68SBhupesh Sharma 1990a1c86c68SBhupesh Sharma pcie1_phy: phy@1c0e000 { 1991a1c86c68SBhupesh Sharma compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1992a1c86c68SBhupesh Sharma reg = <0 0x01c0e000 0 0x1c0>; 1993a1c86c68SBhupesh Sharma #address-cells = <2>; 1994a1c86c68SBhupesh Sharma #size-cells = <2>; 1995a1c86c68SBhupesh Sharma ranges; 1996a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1997a1c86c68SBhupesh Sharma <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 19984ac3d9afSDmitry Baryshkov <&gcc GCC_PCIE_1_CLKREF_CLK>, 1999a1c86c68SBhupesh Sharma <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 20004ac3d9afSDmitry Baryshkov clock-names = "aux", 20014ac3d9afSDmitry Baryshkov "cfg_ahb", 20024ac3d9afSDmitry Baryshkov "ref", 20034ac3d9afSDmitry Baryshkov "refgen"; 2004a1c86c68SBhupesh Sharma 2005a1c86c68SBhupesh Sharma resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2006a1c86c68SBhupesh Sharma reset-names = "phy"; 2007a1c86c68SBhupesh Sharma 2008a1c86c68SBhupesh Sharma assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2009a1c86c68SBhupesh Sharma assigned-clock-rates = <100000000>; 2010a1c86c68SBhupesh Sharma 2011a1c86c68SBhupesh Sharma status = "disabled"; 2012a1c86c68SBhupesh Sharma 2013a1c86c68SBhupesh Sharma pcie1_lane: phy@1c0e200 { 2014f6973229SKonrad Dybcio reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2015f6973229SKonrad Dybcio <0 0x01c0e400 0 0x200>, /* rx0 */ 2016f6973229SKonrad Dybcio <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2017f6973229SKonrad Dybcio <0 0x01c0e600 0 0x170>, /* tx1 */ 2018f6973229SKonrad Dybcio <0 0x01c0e800 0 0x200>, /* rx1 */ 2019f6973229SKonrad Dybcio <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2020a1c86c68SBhupesh Sharma clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2021a1c86c68SBhupesh Sharma clock-names = "pipe0"; 2022a1c86c68SBhupesh Sharma 2023a1c86c68SBhupesh Sharma #phy-cells = <0>; 2024a1c86c68SBhupesh Sharma clock-output-names = "pcie_1_pipe_clk"; 2025a1c86c68SBhupesh Sharma }; 2026a1c86c68SBhupesh Sharma }; 2027a1c86c68SBhupesh Sharma 20283834a2e9SVinod Koul ufs_mem_hc: ufshc@1d84000 { 20293834a2e9SVinod Koul compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 20303834a2e9SVinod Koul "jedec,ufs-2.0"; 203198aee1e3SBhupesh Sharma reg = <0 0x01d84000 0 0x2500>, 203298aee1e3SBhupesh Sharma <0 0x01d90000 0 0x8000>; 203398aee1e3SBhupesh Sharma reg-names = "std", "ice"; 20343834a2e9SVinod Koul interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 20353834a2e9SVinod Koul phys = <&ufs_mem_phy_lanes>; 20363834a2e9SVinod Koul phy-names = "ufsphy"; 20373834a2e9SVinod Koul lanes-per-direction = <2>; 20383834a2e9SVinod Koul #reset-cells = <1>; 20393834a2e9SVinod Koul resets = <&gcc GCC_UFS_PHY_BCR>; 20403834a2e9SVinod Koul reset-names = "rst"; 20413834a2e9SVinod Koul 204248156232SJonathan Marek iommus = <&apps_smmu 0x300 0>; 204348156232SJonathan Marek 20443834a2e9SVinod Koul clock-names = 20453834a2e9SVinod Koul "core_clk", 20463834a2e9SVinod Koul "bus_aggr_clk", 20473834a2e9SVinod Koul "iface_clk", 20483834a2e9SVinod Koul "core_clk_unipro", 20493834a2e9SVinod Koul "ref_clk", 20503834a2e9SVinod Koul "tx_lane0_sync_clk", 20513834a2e9SVinod Koul "rx_lane0_sync_clk", 205298aee1e3SBhupesh Sharma "rx_lane1_sync_clk", 205398aee1e3SBhupesh Sharma "ice_core_clk"; 20543834a2e9SVinod Koul clocks = 20553834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AXI_CLK>, 20563834a2e9SVinod Koul <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 20573834a2e9SVinod Koul <&gcc GCC_UFS_PHY_AHB_CLK>, 20583834a2e9SVinod Koul <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 20593834a2e9SVinod Koul <&rpmhcc RPMH_CXO_CLK>, 20603834a2e9SVinod Koul <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 20613834a2e9SVinod Koul <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 206298aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 206398aee1e3SBhupesh Sharma <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 20643834a2e9SVinod Koul freq-table-hz = 20653834a2e9SVinod Koul <37500000 300000000>, 20663834a2e9SVinod Koul <0 0>, 20673834a2e9SVinod Koul <0 0>, 20683834a2e9SVinod Koul <37500000 300000000>, 20693834a2e9SVinod Koul <0 0>, 20703834a2e9SVinod Koul <0 0>, 20713834a2e9SVinod Koul <0 0>, 207298aee1e3SBhupesh Sharma <0 0>, 207398aee1e3SBhupesh Sharma <0 300000000>; 20743834a2e9SVinod Koul 20753834a2e9SVinod Koul status = "disabled"; 20763834a2e9SVinod Koul }; 20773834a2e9SVinod Koul 20783834a2e9SVinod Koul ufs_mem_phy: phy@1d87000 { 20793834a2e9SVinod Koul compatible = "qcom,sm8150-qmp-ufs-phy"; 2080c79ec891SVinod Koul reg = <0 0x01d87000 0 0x1c0>; 20813834a2e9SVinod Koul #address-cells = <2>; 20823834a2e9SVinod Koul #size-cells = <2>; 20833834a2e9SVinod Koul ranges; 20843834a2e9SVinod Koul clock-names = "ref", 20853834a2e9SVinod Koul "ref_aux"; 20863834a2e9SVinod Koul clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 20873834a2e9SVinod Koul <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 20883834a2e9SVinod Koul 2089fe75b0c4SBhupesh Sharma power-domains = <&gcc UFS_PHY_GDSC>; 2090fe75b0c4SBhupesh Sharma 20913834a2e9SVinod Koul resets = <&ufs_mem_hc 0>; 20923834a2e9SVinod Koul reset-names = "ufsphy"; 20933834a2e9SVinod Koul status = "disabled"; 20943834a2e9SVinod Koul 20951351512fSShawn Guo ufs_mem_phy_lanes: phy@1d87400 { 209636a31b3aSJohan Hovold reg = <0 0x01d87400 0 0x16c>, 209736a31b3aSJohan Hovold <0 0x01d87600 0 0x200>, 209836a31b3aSJohan Hovold <0 0x01d87c00 0 0x200>, 209936a31b3aSJohan Hovold <0 0x01d87800 0 0x16c>, 210036a31b3aSJohan Hovold <0 0x01d87a00 0 0x200>; 21013834a2e9SVinod Koul #phy-cells = <0>; 21023834a2e9SVinod Koul }; 21033834a2e9SVinod Koul }; 21043834a2e9SVinod Koul 2105f7f485f3SBhupesh Sharma cryptobam: dma-controller@1dc4000 { 2106f7f485f3SBhupesh Sharma compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2107f7f485f3SBhupesh Sharma reg = <0 0x01dc4000 0 0x24000>; 2108f7f485f3SBhupesh Sharma interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2109f7f485f3SBhupesh Sharma #dma-cells = <1>; 2110f7f485f3SBhupesh Sharma qcom,ee = <0>; 2111f7f485f3SBhupesh Sharma qcom,controlled-remotely; 2112f7f485f3SBhupesh Sharma num-channels = <8>; 2113f7f485f3SBhupesh Sharma qcom,num-ees = <2>; 2114f7f485f3SBhupesh Sharma iommus = <&apps_smmu 0x502 0x0641>, 2115f7f485f3SBhupesh Sharma <&apps_smmu 0x504 0x0011>, 2116f7f485f3SBhupesh Sharma <&apps_smmu 0x506 0x0011>, 2117f7f485f3SBhupesh Sharma <&apps_smmu 0x508 0x0011>, 2118f7f485f3SBhupesh Sharma <&apps_smmu 0x512 0x0000>; 2119f7f485f3SBhupesh Sharma }; 2120f7f485f3SBhupesh Sharma 2121f7f485f3SBhupesh Sharma crypto: crypto@1dfa000 { 2122f7f485f3SBhupesh Sharma compatible = "qcom,sm8150-qce", "qcom,qce"; 2123f7f485f3SBhupesh Sharma reg = <0 0x01dfa000 0 0x6000>; 2124f7f485f3SBhupesh Sharma dmas = <&cryptobam 4>, <&cryptobam 5>; 2125f7f485f3SBhupesh Sharma dma-names = "rx", "tx"; 2126f7f485f3SBhupesh Sharma iommus = <&apps_smmu 0x502 0x0641>, 2127f7f485f3SBhupesh Sharma <&apps_smmu 0x504 0x0011>, 2128f7f485f3SBhupesh Sharma <&apps_smmu 0x506 0x0011>, 2129f7f485f3SBhupesh Sharma <&apps_smmu 0x508 0x0011>, 2130f7f485f3SBhupesh Sharma <&apps_smmu 0x512 0x0000>; 213197c28902SAbel Vesa interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2132f7f485f3SBhupesh Sharma interconnect-names = "memory"; 2133f7f485f3SBhupesh Sharma }; 2134f7f485f3SBhupesh Sharma 2135c752d491SKrzysztof Kozlowski tcsr_mutex: hwlock@1f40000 { 2136c752d491SKrzysztof Kozlowski compatible = "qcom,tcsr-mutex"; 213786d7c946SKrzysztof Kozlowski reg = <0x0 0x01f40000 0x0 0x20000>; 2138c752d491SKrzysztof Kozlowski #hwlock-cells = <1>; 213986d7c946SKrzysztof Kozlowski }; 214086d7c946SKrzysztof Kozlowski 2141d0909bf4SJohan Hovold tcsr_regs_1: syscon@1f60000 { 214286d7c946SKrzysztof Kozlowski compatible = "qcom,sm8150-tcsr", "syscon"; 214386d7c946SKrzysztof Kozlowski reg = <0x0 0x01f60000 0x0 0x20000>; 2144d8cf9372SVinod Koul }; 2145d8cf9372SVinod Koul 214649076351SSibi Sankar remoteproc_slpi: remoteproc@2400000 { 214749076351SSibi Sankar compatible = "qcom,sm8150-slpi-pas"; 214849076351SSibi Sankar reg = <0x0 0x02400000 0x0 0x4040>; 214949076351SSibi Sankar 215049076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 215149076351SSibi Sankar <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 215249076351SSibi Sankar <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 215349076351SSibi Sankar <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 215449076351SSibi Sankar <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 215549076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 215649076351SSibi Sankar "handover", "stop-ack"; 215749076351SSibi Sankar 215849076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 215949076351SSibi Sankar clock-names = "xo"; 216049076351SSibi Sankar 2161a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_LCX>, 2162a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_LMX>; 2163d9d327f6SSibi Sankar power-domain-names = "lcx", "lmx"; 216449076351SSibi Sankar 216549076351SSibi Sankar memory-region = <&slpi_mem>; 216649076351SSibi Sankar 2167d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2168d9d327f6SSibi Sankar 216949076351SSibi Sankar qcom,smem-states = <&slpi_smp2p_out 0>; 217049076351SSibi Sankar qcom,smem-state-names = "stop"; 217149076351SSibi Sankar 217249076351SSibi Sankar status = "disabled"; 217349076351SSibi Sankar 217449076351SSibi Sankar glink-edge { 217549076351SSibi Sankar interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 217649076351SSibi Sankar label = "dsps"; 217749076351SSibi Sankar qcom,remote-pid = <3>; 217849076351SSibi Sankar mboxes = <&apss_shared 24>; 217981729330SBhupesh Sharma 218081729330SBhupesh Sharma fastrpc { 218181729330SBhupesh Sharma compatible = "qcom,fastrpc"; 218281729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 218381729330SBhupesh Sharma label = "sdsp"; 21848c8ce95bSJeya R qcom,non-secure-domain; 218581729330SBhupesh Sharma #address-cells = <1>; 218681729330SBhupesh Sharma #size-cells = <0>; 218781729330SBhupesh Sharma 218881729330SBhupesh Sharma compute-cb@1 { 218981729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 219081729330SBhupesh Sharma reg = <1>; 219181729330SBhupesh Sharma iommus = <&apps_smmu 0x05a1 0x0>; 219281729330SBhupesh Sharma }; 219381729330SBhupesh Sharma 219481729330SBhupesh Sharma compute-cb@2 { 219581729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 219681729330SBhupesh Sharma reg = <2>; 219781729330SBhupesh Sharma iommus = <&apps_smmu 0x05a2 0x0>; 219881729330SBhupesh Sharma }; 219981729330SBhupesh Sharma 220081729330SBhupesh Sharma compute-cb@3 { 220181729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 220281729330SBhupesh Sharma reg = <3>; 220381729330SBhupesh Sharma iommus = <&apps_smmu 0x05a3 0x0>; 220481729330SBhupesh Sharma /* note: shared-cb = <4> in downstream */ 220581729330SBhupesh Sharma }; 220681729330SBhupesh Sharma }; 220749076351SSibi Sankar }; 220849076351SSibi Sankar }; 220949076351SSibi Sankar 2210f30ac26dSJonathan Marek gpu: gpu@2c00000 { 22111642ab96SKonrad Dybcio compatible = "qcom,adreno-640.1", "qcom,adreno"; 2212f30ac26dSJonathan Marek reg = <0 0x02c00000 0 0x40000>; 2213f30ac26dSJonathan Marek reg-names = "kgsl_3d0_reg_memory"; 2214f30ac26dSJonathan Marek 2215f30ac26dSJonathan Marek interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2216f30ac26dSJonathan Marek 2217f30ac26dSJonathan Marek iommus = <&adreno_smmu 0 0x401>; 2218f30ac26dSJonathan Marek 2219f30ac26dSJonathan Marek operating-points-v2 = <&gpu_opp_table>; 2220f30ac26dSJonathan Marek 2221f30ac26dSJonathan Marek qcom,gmu = <&gmu>; 2222f30ac26dSJonathan Marek 2223b53ae6b6SKonrad Dybcio nvmem-cells = <&gpu_speed_bin>; 2224b53ae6b6SKonrad Dybcio nvmem-cell-names = "speed_bin"; 2225b53ae6b6SKonrad Dybcio 2226b1dc3c6bSKonrad Dybcio status = "disabled"; 2227b1dc3c6bSKonrad Dybcio 2228f30ac26dSJonathan Marek zap-shader { 2229f30ac26dSJonathan Marek memory-region = <&gpu_mem>; 2230f30ac26dSJonathan Marek }; 2231f30ac26dSJonathan Marek 2232f30ac26dSJonathan Marek gpu_opp_table: opp-table { 2233f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2234f30ac26dSJonathan Marek 2235f30ac26dSJonathan Marek opp-675000000 { 2236f30ac26dSJonathan Marek opp-hz = /bits/ 64 <675000000>; 2237f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2238b53ae6b6SKonrad Dybcio opp-supported-hw = <0x2>; 2239f30ac26dSJonathan Marek }; 2240f30ac26dSJonathan Marek 2241f30ac26dSJonathan Marek opp-585000000 { 2242f30ac26dSJonathan Marek opp-hz = /bits/ 64 <585000000>; 2243f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2244b53ae6b6SKonrad Dybcio opp-supported-hw = <0x3>; 2245f30ac26dSJonathan Marek }; 2246f30ac26dSJonathan Marek 2247f30ac26dSJonathan Marek opp-499200000 { 2248f30ac26dSJonathan Marek opp-hz = /bits/ 64 <499200000>; 2249f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2250b53ae6b6SKonrad Dybcio opp-supported-hw = <0x3>; 2251f30ac26dSJonathan Marek }; 2252f30ac26dSJonathan Marek 2253f30ac26dSJonathan Marek opp-427000000 { 2254f30ac26dSJonathan Marek opp-hz = /bits/ 64 <427000000>; 2255f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2256b53ae6b6SKonrad Dybcio opp-supported-hw = <0x3>; 2257f30ac26dSJonathan Marek }; 2258f30ac26dSJonathan Marek 2259f30ac26dSJonathan Marek opp-345000000 { 2260f30ac26dSJonathan Marek opp-hz = /bits/ 64 <345000000>; 2261f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2262b53ae6b6SKonrad Dybcio opp-supported-hw = <0x3>; 2263f30ac26dSJonathan Marek }; 2264f30ac26dSJonathan Marek 2265f30ac26dSJonathan Marek opp-257000000 { 2266f30ac26dSJonathan Marek opp-hz = /bits/ 64 <257000000>; 2267f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2268b53ae6b6SKonrad Dybcio opp-supported-hw = <0x3>; 2269f30ac26dSJonathan Marek }; 2270f30ac26dSJonathan Marek }; 2271f30ac26dSJonathan Marek }; 2272f30ac26dSJonathan Marek 2273f30ac26dSJonathan Marek gmu: gmu@2c6a000 { 2274f30ac26dSJonathan Marek compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2275f30ac26dSJonathan Marek 2276f30ac26dSJonathan Marek reg = <0 0x02c6a000 0 0x30000>, 2277f30ac26dSJonathan Marek <0 0x0b290000 0 0x10000>, 2278f30ac26dSJonathan Marek <0 0x0b490000 0 0x10000>; 2279f30ac26dSJonathan Marek reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2280f30ac26dSJonathan Marek 2281f30ac26dSJonathan Marek interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2282f30ac26dSJonathan Marek <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2283f30ac26dSJonathan Marek interrupt-names = "hfi", "gmu"; 2284f30ac26dSJonathan Marek 2285f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2286f1269916SJonathan Marek <&gpucc GPU_CC_CX_GMU_CLK>, 2287f1269916SJonathan Marek <&gpucc GPU_CC_CXO_CLK>, 2288f30ac26dSJonathan Marek <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2289f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2290f30ac26dSJonathan Marek clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2291f30ac26dSJonathan Marek 2292f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>, 2293f1269916SJonathan Marek <&gpucc GPU_GX_GDSC>; 2294f30ac26dSJonathan Marek power-domain-names = "cx", "gx"; 2295f30ac26dSJonathan Marek 2296f30ac26dSJonathan Marek iommus = <&adreno_smmu 5 0x400>; 2297f30ac26dSJonathan Marek 2298f30ac26dSJonathan Marek operating-points-v2 = <&gmu_opp_table>; 2299f30ac26dSJonathan Marek 2300b1dc3c6bSKonrad Dybcio status = "disabled"; 2301b1dc3c6bSKonrad Dybcio 2302f30ac26dSJonathan Marek gmu_opp_table: opp-table { 2303f30ac26dSJonathan Marek compatible = "operating-points-v2"; 2304f30ac26dSJonathan Marek 2305f30ac26dSJonathan Marek opp-200000000 { 2306f30ac26dSJonathan Marek opp-hz = /bits/ 64 <200000000>; 2307f30ac26dSJonathan Marek opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2308f30ac26dSJonathan Marek }; 2309f30ac26dSJonathan Marek }; 2310f30ac26dSJonathan Marek }; 2311f30ac26dSJonathan Marek 2312f30ac26dSJonathan Marek gpucc: clock-controller@2c90000 { 2313f30ac26dSJonathan Marek compatible = "qcom,sm8150-gpucc"; 2314f30ac26dSJonathan Marek reg = <0 0x02c90000 0 0x9000>; 2315f30ac26dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>, 2316f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2317f30ac26dSJonathan Marek <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2318f30ac26dSJonathan Marek clock-names = "bi_tcxo", 2319f30ac26dSJonathan Marek "gcc_gpu_gpll0_clk_src", 2320f30ac26dSJonathan Marek "gcc_gpu_gpll0_div_clk_src"; 2321f30ac26dSJonathan Marek #clock-cells = <1>; 2322f30ac26dSJonathan Marek #reset-cells = <1>; 2323f30ac26dSJonathan Marek #power-domain-cells = <1>; 2324f30ac26dSJonathan Marek }; 2325f30ac26dSJonathan Marek 2326f30ac26dSJonathan Marek adreno_smmu: iommu@2ca0000 { 23273e5c0025SKonrad Dybcio compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 23283e5c0025SKonrad Dybcio "qcom,smmu-500", "arm,mmu-500"; 2329f30ac26dSJonathan Marek reg = <0 0x02ca0000 0 0x10000>; 2330f30ac26dSJonathan Marek #iommu-cells = <2>; 2331f30ac26dSJonathan Marek #global-interrupts = <1>; 2332f30ac26dSJonathan Marek interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2333f30ac26dSJonathan Marek <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2334f30ac26dSJonathan Marek <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2335f30ac26dSJonathan Marek <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2336f30ac26dSJonathan Marek <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2337f30ac26dSJonathan Marek <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2338f30ac26dSJonathan Marek <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2339f30ac26dSJonathan Marek <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2340f30ac26dSJonathan Marek <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2341f1269916SJonathan Marek clocks = <&gpucc GPU_CC_AHB_CLK>, 2342f30ac26dSJonathan Marek <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2343f30ac26dSJonathan Marek <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2344f30ac26dSJonathan Marek clock-names = "ahb", "bus", "iface"; 2345f30ac26dSJonathan Marek 2346f1269916SJonathan Marek power-domains = <&gpucc GPU_CX_GDSC>; 2347f30ac26dSJonathan Marek }; 2348f30ac26dSJonathan Marek 2349e13c6d14SVinod Koul tlmm: pinctrl@3100000 { 2350e13c6d14SVinod Koul compatible = "qcom,sm8150-pinctrl"; 2351e13c6d14SVinod Koul reg = <0x0 0x03100000 0x0 0x300000>, 2352e13c6d14SVinod Koul <0x0 0x03500000 0x0 0x300000>, 2353e13c6d14SVinod Koul <0x0 0x03900000 0x0 0x300000>, 2354e13c6d14SVinod Koul <0x0 0x03D00000 0x0 0x300000>; 2355e13c6d14SVinod Koul reg-names = "west", "east", "north", "south"; 2356e13c6d14SVinod Koul interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2357de3abdf3SShawn Guo gpio-ranges = <&tlmm 0 0 176>; 2358e13c6d14SVinod Koul gpio-controller; 2359e13c6d14SVinod Koul #gpio-cells = <2>; 2360e13c6d14SVinod Koul interrupt-controller; 2361e13c6d14SVinod Koul #interrupt-cells = <2>; 23626127d8e4SBhupesh Sharma wakeup-parent = <&pdc>; 236381bee695SCaleb Connolly 2364028fe09cSKrzysztof Kozlowski qup_i2c0_default: qup-i2c0-default-state { 236581bee695SCaleb Connolly pins = "gpio0", "gpio1"; 236681bee695SCaleb Connolly function = "qup0"; 236781bee695SCaleb Connolly drive-strength = <0x02>; 236881bee695SCaleb Connolly bias-disable; 236981bee695SCaleb Connolly }; 237081bee695SCaleb Connolly 2371028fe09cSKrzysztof Kozlowski qup_spi0_default: qup-spi0-default-state { 2372129e1c96SFelipe Balbi pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2373129e1c96SFelipe Balbi function = "qup0"; 2374129e1c96SFelipe Balbi drive-strength = <6>; 2375129e1c96SFelipe Balbi bias-disable; 2376129e1c96SFelipe Balbi }; 2377129e1c96SFelipe Balbi 2378028fe09cSKrzysztof Kozlowski qup_i2c1_default: qup-i2c1-default-state { 237981bee695SCaleb Connolly pins = "gpio114", "gpio115"; 238081bee695SCaleb Connolly function = "qup1"; 2381028fe09cSKrzysztof Kozlowski drive-strength = <2>; 238281bee695SCaleb Connolly bias-disable; 238381bee695SCaleb Connolly }; 238481bee695SCaleb Connolly 2385028fe09cSKrzysztof Kozlowski qup_spi1_default: qup-spi1-default-state { 2386129e1c96SFelipe Balbi pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2387129e1c96SFelipe Balbi function = "qup1"; 2388129e1c96SFelipe Balbi drive-strength = <6>; 2389129e1c96SFelipe Balbi bias-disable; 2390129e1c96SFelipe Balbi }; 2391129e1c96SFelipe Balbi 2392028fe09cSKrzysztof Kozlowski qup_i2c2_default: qup-i2c2-default-state { 239381bee695SCaleb Connolly pins = "gpio126", "gpio127"; 239481bee695SCaleb Connolly function = "qup2"; 2395028fe09cSKrzysztof Kozlowski drive-strength = <2>; 239681bee695SCaleb Connolly bias-disable; 239781bee695SCaleb Connolly }; 239881bee695SCaleb Connolly 2399028fe09cSKrzysztof Kozlowski qup_spi2_default: qup-spi2-default-state { 2400129e1c96SFelipe Balbi pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2401129e1c96SFelipe Balbi function = "qup2"; 2402129e1c96SFelipe Balbi drive-strength = <6>; 2403129e1c96SFelipe Balbi bias-disable; 2404129e1c96SFelipe Balbi }; 2405129e1c96SFelipe Balbi 2406028fe09cSKrzysztof Kozlowski qup_i2c3_default: qup-i2c3-default-state { 240781bee695SCaleb Connolly pins = "gpio144", "gpio145"; 240881bee695SCaleb Connolly function = "qup3"; 2409028fe09cSKrzysztof Kozlowski drive-strength = <2>; 241081bee695SCaleb Connolly bias-disable; 241181bee695SCaleb Connolly }; 241281bee695SCaleb Connolly 2413028fe09cSKrzysztof Kozlowski qup_spi3_default: qup-spi3-default-state { 2414129e1c96SFelipe Balbi pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2415129e1c96SFelipe Balbi function = "qup3"; 2416129e1c96SFelipe Balbi drive-strength = <6>; 2417129e1c96SFelipe Balbi bias-disable; 2418129e1c96SFelipe Balbi }; 2419129e1c96SFelipe Balbi 2420028fe09cSKrzysztof Kozlowski qup_i2c4_default: qup-i2c4-default-state { 242181bee695SCaleb Connolly pins = "gpio51", "gpio52"; 242281bee695SCaleb Connolly function = "qup4"; 2423028fe09cSKrzysztof Kozlowski drive-strength = <2>; 242481bee695SCaleb Connolly bias-disable; 242581bee695SCaleb Connolly }; 242681bee695SCaleb Connolly 2427028fe09cSKrzysztof Kozlowski qup_spi4_default: qup-spi4-default-state { 2428129e1c96SFelipe Balbi pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2429129e1c96SFelipe Balbi function = "qup4"; 2430129e1c96SFelipe Balbi drive-strength = <6>; 2431129e1c96SFelipe Balbi bias-disable; 2432129e1c96SFelipe Balbi }; 2433129e1c96SFelipe Balbi 2434028fe09cSKrzysztof Kozlowski qup_i2c5_default: qup-i2c5-default-state { 243581bee695SCaleb Connolly pins = "gpio121", "gpio122"; 243681bee695SCaleb Connolly function = "qup5"; 2437028fe09cSKrzysztof Kozlowski drive-strength = <2>; 243881bee695SCaleb Connolly bias-disable; 243981bee695SCaleb Connolly }; 244081bee695SCaleb Connolly 2441028fe09cSKrzysztof Kozlowski qup_spi5_default: qup-spi5-default-state { 2442129e1c96SFelipe Balbi pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2443129e1c96SFelipe Balbi function = "qup5"; 2444129e1c96SFelipe Balbi drive-strength = <6>; 2445129e1c96SFelipe Balbi bias-disable; 2446129e1c96SFelipe Balbi }; 2447129e1c96SFelipe Balbi 2448028fe09cSKrzysztof Kozlowski qup_i2c6_default: qup-i2c6-default-state { 244981bee695SCaleb Connolly pins = "gpio6", "gpio7"; 245081bee695SCaleb Connolly function = "qup6"; 2451028fe09cSKrzysztof Kozlowski drive-strength = <2>; 245281bee695SCaleb Connolly bias-disable; 245381bee695SCaleb Connolly }; 245481bee695SCaleb Connolly 2455028fe09cSKrzysztof Kozlowski qup_spi6_default: qup-spi6_default-state { 2456129e1c96SFelipe Balbi pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2457129e1c96SFelipe Balbi function = "qup6"; 2458129e1c96SFelipe Balbi drive-strength = <6>; 2459129e1c96SFelipe Balbi bias-disable; 2460129e1c96SFelipe Balbi }; 2461129e1c96SFelipe Balbi 2462028fe09cSKrzysztof Kozlowski qup_i2c7_default: qup-i2c7-default-state { 246381bee695SCaleb Connolly pins = "gpio98", "gpio99"; 246481bee695SCaleb Connolly function = "qup7"; 2465028fe09cSKrzysztof Kozlowski drive-strength = <2>; 246681bee695SCaleb Connolly bias-disable; 246781bee695SCaleb Connolly }; 246881bee695SCaleb Connolly 2469028fe09cSKrzysztof Kozlowski qup_spi7_default: qup-spi7_default-state { 2470129e1c96SFelipe Balbi pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2471129e1c96SFelipe Balbi function = "qup7"; 2472129e1c96SFelipe Balbi drive-strength = <6>; 2473129e1c96SFelipe Balbi bias-disable; 2474129e1c96SFelipe Balbi }; 2475129e1c96SFelipe Balbi 2476028fe09cSKrzysztof Kozlowski qup_i2c8_default: qup-i2c8-default-state { 247781bee695SCaleb Connolly pins = "gpio88", "gpio89"; 247881bee695SCaleb Connolly function = "qup8"; 2479028fe09cSKrzysztof Kozlowski drive-strength = <2>; 248081bee695SCaleb Connolly bias-disable; 248181bee695SCaleb Connolly }; 248281bee695SCaleb Connolly 2483028fe09cSKrzysztof Kozlowski qup_spi8_default: qup-spi8-default-state { 2484129e1c96SFelipe Balbi pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2485129e1c96SFelipe Balbi function = "qup8"; 2486129e1c96SFelipe Balbi drive-strength = <6>; 2487129e1c96SFelipe Balbi bias-disable; 2488129e1c96SFelipe Balbi }; 2489129e1c96SFelipe Balbi 2490028fe09cSKrzysztof Kozlowski qup_i2c9_default: qup-i2c9-default-state { 249181bee695SCaleb Connolly pins = "gpio39", "gpio40"; 249281bee695SCaleb Connolly function = "qup9"; 2493028fe09cSKrzysztof Kozlowski drive-strength = <2>; 249481bee695SCaleb Connolly bias-disable; 249581bee695SCaleb Connolly }; 249681bee695SCaleb Connolly 2497028fe09cSKrzysztof Kozlowski qup_spi9_default: qup-spi9-default-state { 2498129e1c96SFelipe Balbi pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2499129e1c96SFelipe Balbi function = "qup9"; 2500129e1c96SFelipe Balbi drive-strength = <6>; 2501129e1c96SFelipe Balbi bias-disable; 2502129e1c96SFelipe Balbi }; 2503129e1c96SFelipe Balbi 250410d900a8SBartosz Golaszewski qup_uart9_default: qup-uart9-default-state { 250510d900a8SBartosz Golaszewski pins = "gpio41", "gpio42"; 250610d900a8SBartosz Golaszewski function = "qup9"; 250710d900a8SBartosz Golaszewski drive-strength = <2>; 250810d900a8SBartosz Golaszewski bias-disable; 250910d900a8SBartosz Golaszewski }; 251010d900a8SBartosz Golaszewski 2511028fe09cSKrzysztof Kozlowski qup_i2c10_default: qup-i2c10-default-state { 251281bee695SCaleb Connolly pins = "gpio9", "gpio10"; 251381bee695SCaleb Connolly function = "qup10"; 2514028fe09cSKrzysztof Kozlowski drive-strength = <2>; 251581bee695SCaleb Connolly bias-disable; 251681bee695SCaleb Connolly }; 251781bee695SCaleb Connolly 2518028fe09cSKrzysztof Kozlowski qup_spi10_default: qup-spi10-default-state { 2519129e1c96SFelipe Balbi pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2520129e1c96SFelipe Balbi function = "qup10"; 2521129e1c96SFelipe Balbi drive-strength = <6>; 2522129e1c96SFelipe Balbi bias-disable; 2523129e1c96SFelipe Balbi }; 2524129e1c96SFelipe Balbi 2525028fe09cSKrzysztof Kozlowski qup_i2c11_default: qup-i2c11-default-state { 252681bee695SCaleb Connolly pins = "gpio94", "gpio95"; 252781bee695SCaleb Connolly function = "qup11"; 2528028fe09cSKrzysztof Kozlowski drive-strength = <2>; 252981bee695SCaleb Connolly bias-disable; 253081bee695SCaleb Connolly }; 253181bee695SCaleb Connolly 2532028fe09cSKrzysztof Kozlowski qup_spi11_default: qup-spi11-default-state { 2533129e1c96SFelipe Balbi pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2534129e1c96SFelipe Balbi function = "qup11"; 2535129e1c96SFelipe Balbi drive-strength = <6>; 2536129e1c96SFelipe Balbi bias-disable; 2537129e1c96SFelipe Balbi }; 2538129e1c96SFelipe Balbi 2539028fe09cSKrzysztof Kozlowski qup_i2c12_default: qup-i2c12-default-state { 254081bee695SCaleb Connolly pins = "gpio83", "gpio84"; 254181bee695SCaleb Connolly function = "qup12"; 2542028fe09cSKrzysztof Kozlowski drive-strength = <2>; 254381bee695SCaleb Connolly bias-disable; 254481bee695SCaleb Connolly }; 254581bee695SCaleb Connolly 2546028fe09cSKrzysztof Kozlowski qup_spi12_default: qup-spi12-default-state { 2547129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2548129e1c96SFelipe Balbi function = "qup12"; 2549129e1c96SFelipe Balbi drive-strength = <6>; 2550129e1c96SFelipe Balbi bias-disable; 2551129e1c96SFelipe Balbi }; 2552129e1c96SFelipe Balbi 2553028fe09cSKrzysztof Kozlowski qup_i2c13_default: qup-i2c13-default-state { 255481bee695SCaleb Connolly pins = "gpio43", "gpio44"; 255581bee695SCaleb Connolly function = "qup13"; 2556028fe09cSKrzysztof Kozlowski drive-strength = <2>; 255781bee695SCaleb Connolly bias-disable; 255881bee695SCaleb Connolly }; 255981bee695SCaleb Connolly 2560028fe09cSKrzysztof Kozlowski qup_spi13_default: qup-spi13-default-state { 2561129e1c96SFelipe Balbi pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2562129e1c96SFelipe Balbi function = "qup13"; 2563129e1c96SFelipe Balbi drive-strength = <6>; 2564129e1c96SFelipe Balbi bias-disable; 2565129e1c96SFelipe Balbi }; 2566129e1c96SFelipe Balbi 2567028fe09cSKrzysztof Kozlowski qup_i2c14_default: qup-i2c14-default-state { 256881bee695SCaleb Connolly pins = "gpio47", "gpio48"; 256981bee695SCaleb Connolly function = "qup14"; 2570028fe09cSKrzysztof Kozlowski drive-strength = <2>; 257181bee695SCaleb Connolly bias-disable; 257281bee695SCaleb Connolly }; 257381bee695SCaleb Connolly 2574028fe09cSKrzysztof Kozlowski qup_spi14_default: qup-spi14-default-state { 2575129e1c96SFelipe Balbi pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2576129e1c96SFelipe Balbi function = "qup14"; 2577129e1c96SFelipe Balbi drive-strength = <6>; 2578129e1c96SFelipe Balbi bias-disable; 2579129e1c96SFelipe Balbi }; 2580129e1c96SFelipe Balbi 2581028fe09cSKrzysztof Kozlowski qup_i2c15_default: qup-i2c15-default-state { 258281bee695SCaleb Connolly pins = "gpio27", "gpio28"; 258381bee695SCaleb Connolly function = "qup15"; 2584028fe09cSKrzysztof Kozlowski drive-strength = <2>; 258581bee695SCaleb Connolly bias-disable; 258681bee695SCaleb Connolly }; 258781bee695SCaleb Connolly 2588028fe09cSKrzysztof Kozlowski qup_spi15_default: qup-spi15-default-state { 2589129e1c96SFelipe Balbi pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2590129e1c96SFelipe Balbi function = "qup15"; 2591129e1c96SFelipe Balbi drive-strength = <6>; 2592129e1c96SFelipe Balbi bias-disable; 2593129e1c96SFelipe Balbi }; 2594129e1c96SFelipe Balbi 2595028fe09cSKrzysztof Kozlowski qup_i2c16_default: qup-i2c16-default-state { 259681bee695SCaleb Connolly pins = "gpio86", "gpio85"; 259781bee695SCaleb Connolly function = "qup16"; 2598028fe09cSKrzysztof Kozlowski drive-strength = <2>; 259981bee695SCaleb Connolly bias-disable; 260081bee695SCaleb Connolly }; 260181bee695SCaleb Connolly 2602028fe09cSKrzysztof Kozlowski qup_spi16_default: qup-spi16-default-state { 2603129e1c96SFelipe Balbi pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2604129e1c96SFelipe Balbi function = "qup16"; 2605129e1c96SFelipe Balbi drive-strength = <6>; 2606129e1c96SFelipe Balbi bias-disable; 2607129e1c96SFelipe Balbi }; 2608129e1c96SFelipe Balbi 2609028fe09cSKrzysztof Kozlowski qup_i2c17_default: qup-i2c17-default-state { 261081bee695SCaleb Connolly pins = "gpio55", "gpio56"; 261181bee695SCaleb Connolly function = "qup17"; 2612028fe09cSKrzysztof Kozlowski drive-strength = <2>; 261381bee695SCaleb Connolly bias-disable; 261481bee695SCaleb Connolly }; 261581bee695SCaleb Connolly 2616028fe09cSKrzysztof Kozlowski qup_spi17_default: qup-spi17-default-state { 2617129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2618129e1c96SFelipe Balbi function = "qup17"; 2619129e1c96SFelipe Balbi drive-strength = <6>; 2620129e1c96SFelipe Balbi bias-disable; 2621129e1c96SFelipe Balbi }; 2622129e1c96SFelipe Balbi 2623028fe09cSKrzysztof Kozlowski qup_i2c18_default: qup-i2c18-default-state { 262481bee695SCaleb Connolly pins = "gpio23", "gpio24"; 262581bee695SCaleb Connolly function = "qup18"; 2626028fe09cSKrzysztof Kozlowski drive-strength = <2>; 262781bee695SCaleb Connolly bias-disable; 262881bee695SCaleb Connolly }; 262981bee695SCaleb Connolly 2630028fe09cSKrzysztof Kozlowski qup_spi18_default: qup-spi18-default-state { 2631129e1c96SFelipe Balbi pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2632129e1c96SFelipe Balbi function = "qup18"; 2633129e1c96SFelipe Balbi drive-strength = <6>; 2634129e1c96SFelipe Balbi bias-disable; 2635129e1c96SFelipe Balbi }; 2636129e1c96SFelipe Balbi 2637028fe09cSKrzysztof Kozlowski qup_i2c19_default: qup-i2c19-default-state { 263881bee695SCaleb Connolly pins = "gpio57", "gpio58"; 263981bee695SCaleb Connolly function = "qup19"; 2640028fe09cSKrzysztof Kozlowski drive-strength = <2>; 264181bee695SCaleb Connolly bias-disable; 264281bee695SCaleb Connolly }; 2643129e1c96SFelipe Balbi 2644028fe09cSKrzysztof Kozlowski qup_spi19_default: qup-spi19-default-state { 2645129e1c96SFelipe Balbi pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2646129e1c96SFelipe Balbi function = "qup19"; 2647129e1c96SFelipe Balbi drive-strength = <6>; 2648129e1c96SFelipe Balbi bias-disable; 2649129e1c96SFelipe Balbi }; 2650a1c86c68SBhupesh Sharma 2651028fe09cSKrzysztof Kozlowski pcie0_default_state: pcie0-default-state { 2652028fe09cSKrzysztof Kozlowski perst-pins { 2653a1c86c68SBhupesh Sharma pins = "gpio35"; 2654a1c86c68SBhupesh Sharma function = "gpio"; 2655a1c86c68SBhupesh Sharma drive-strength = <2>; 2656a1c86c68SBhupesh Sharma bias-pull-down; 2657a1c86c68SBhupesh Sharma }; 2658a1c86c68SBhupesh Sharma 2659028fe09cSKrzysztof Kozlowski clkreq-pins { 2660a1c86c68SBhupesh Sharma pins = "gpio36"; 2661a1c86c68SBhupesh Sharma function = "pci_e0"; 2662a1c86c68SBhupesh Sharma drive-strength = <2>; 2663a1c86c68SBhupesh Sharma bias-pull-up; 2664a1c86c68SBhupesh Sharma }; 2665a1c86c68SBhupesh Sharma 2666028fe09cSKrzysztof Kozlowski wake-pins { 2667a1c86c68SBhupesh Sharma pins = "gpio37"; 2668a1c86c68SBhupesh Sharma function = "gpio"; 2669a1c86c68SBhupesh Sharma drive-strength = <2>; 2670a1c86c68SBhupesh Sharma bias-pull-up; 2671a1c86c68SBhupesh Sharma }; 2672a1c86c68SBhupesh Sharma }; 2673a1c86c68SBhupesh Sharma 2674028fe09cSKrzysztof Kozlowski pcie1_default_state: pcie1-default-state { 2675028fe09cSKrzysztof Kozlowski perst-pins { 2676a1c86c68SBhupesh Sharma pins = "gpio102"; 2677a1c86c68SBhupesh Sharma function = "gpio"; 2678a1c86c68SBhupesh Sharma drive-strength = <2>; 2679a1c86c68SBhupesh Sharma bias-pull-down; 2680a1c86c68SBhupesh Sharma }; 2681a1c86c68SBhupesh Sharma 2682028fe09cSKrzysztof Kozlowski clkreq-pins { 2683a1c86c68SBhupesh Sharma pins = "gpio103"; 2684a1c86c68SBhupesh Sharma function = "pci_e1"; 2685a1c86c68SBhupesh Sharma drive-strength = <2>; 2686a1c86c68SBhupesh Sharma bias-pull-up; 2687a1c86c68SBhupesh Sharma }; 2688a1c86c68SBhupesh Sharma 2689028fe09cSKrzysztof Kozlowski wake-pins { 2690a1c86c68SBhupesh Sharma pins = "gpio104"; 2691a1c86c68SBhupesh Sharma function = "gpio"; 2692a1c86c68SBhupesh Sharma drive-strength = <2>; 2693a1c86c68SBhupesh Sharma bias-pull-up; 2694a1c86c68SBhupesh Sharma }; 2695a1c86c68SBhupesh Sharma }; 2696e13c6d14SVinod Koul }; 2697e13c6d14SVinod Koul 269849076351SSibi Sankar remoteproc_mpss: remoteproc@4080000 { 269949076351SSibi Sankar compatible = "qcom,sm8150-mpss-pas"; 270049076351SSibi Sankar reg = <0x0 0x04080000 0x0 0x4040>; 270149076351SSibi Sankar 270249076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 270349076351SSibi Sankar <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 270449076351SSibi Sankar <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 270549076351SSibi Sankar <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 270649076351SSibi Sankar <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 270749076351SSibi Sankar <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 270849076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", "handover", 270949076351SSibi Sankar "stop-ack", "shutdown-ack"; 271049076351SSibi Sankar 271149076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 271249076351SSibi Sankar clock-names = "xo"; 271349076351SSibi Sankar 2714a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>, 2715a94ed9f3SKonrad Dybcio <&rpmhpd SM8150_MSS>; 2716d9d327f6SSibi Sankar power-domain-names = "cx", "mss"; 271749076351SSibi Sankar 271849076351SSibi Sankar memory-region = <&mpss_mem>; 271949076351SSibi Sankar 2720d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 2721d9d327f6SSibi Sankar 272249076351SSibi Sankar qcom,smem-states = <&modem_smp2p_out 0>; 272349076351SSibi Sankar qcom,smem-state-names = "stop"; 272449076351SSibi Sankar 2725b1dc3c6bSKonrad Dybcio status = "disabled"; 2726b1dc3c6bSKonrad Dybcio 272749076351SSibi Sankar glink-edge { 272849076351SSibi Sankar interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 272949076351SSibi Sankar label = "modem"; 273049076351SSibi Sankar qcom,remote-pid = <1>; 273149076351SSibi Sankar mboxes = <&apss_shared 12>; 273249076351SSibi Sankar }; 273349076351SSibi Sankar }; 273449076351SSibi Sankar 273524244cefSSai Prakash Ranjan stm@6002000 { 273624244cefSSai Prakash Ranjan compatible = "arm,coresight-stm", "arm,primecell"; 273724244cefSSai Prakash Ranjan reg = <0 0x06002000 0 0x1000>, 273824244cefSSai Prakash Ranjan <0 0x16280000 0 0x180000>; 273924244cefSSai Prakash Ranjan reg-names = "stm-base", "stm-stimulus-base"; 274024244cefSSai Prakash Ranjan 274124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 274224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 274324244cefSSai Prakash Ranjan 274424244cefSSai Prakash Ranjan out-ports { 274524244cefSSai Prakash Ranjan port { 274624244cefSSai Prakash Ranjan stm_out: endpoint { 274724244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_in7>; 274824244cefSSai Prakash Ranjan }; 274924244cefSSai Prakash Ranjan }; 275024244cefSSai Prakash Ranjan }; 275124244cefSSai Prakash Ranjan }; 275224244cefSSai Prakash Ranjan 275324244cefSSai Prakash Ranjan funnel@6041000 { 275424244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 275524244cefSSai Prakash Ranjan reg = <0 0x06041000 0 0x1000>; 275624244cefSSai Prakash Ranjan 275724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 275824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 275924244cefSSai Prakash Ranjan 276024244cefSSai Prakash Ranjan out-ports { 276124244cefSSai Prakash Ranjan port { 276224244cefSSai Prakash Ranjan funnel0_out: endpoint { 276324244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in0>; 276424244cefSSai Prakash Ranjan }; 276524244cefSSai Prakash Ranjan }; 276624244cefSSai Prakash Ranjan }; 276724244cefSSai Prakash Ranjan 276824244cefSSai Prakash Ranjan in-ports { 276924244cefSSai Prakash Ranjan #address-cells = <1>; 277024244cefSSai Prakash Ranjan #size-cells = <0>; 277124244cefSSai Prakash Ranjan 277224244cefSSai Prakash Ranjan port@7 { 277324244cefSSai Prakash Ranjan reg = <7>; 277424244cefSSai Prakash Ranjan funnel0_in7: endpoint { 277524244cefSSai Prakash Ranjan remote-endpoint = <&stm_out>; 277624244cefSSai Prakash Ranjan }; 277724244cefSSai Prakash Ranjan }; 277824244cefSSai Prakash Ranjan }; 277924244cefSSai Prakash Ranjan }; 278024244cefSSai Prakash Ranjan 278124244cefSSai Prakash Ranjan funnel@6042000 { 278224244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 278324244cefSSai Prakash Ranjan reg = <0 0x06042000 0 0x1000>; 278424244cefSSai Prakash Ranjan 278524244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 278624244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 278724244cefSSai Prakash Ranjan 278824244cefSSai Prakash Ranjan out-ports { 278924244cefSSai Prakash Ranjan port { 279024244cefSSai Prakash Ranjan funnel1_out: endpoint { 279124244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in1>; 279224244cefSSai Prakash Ranjan }; 279324244cefSSai Prakash Ranjan }; 279424244cefSSai Prakash Ranjan }; 279524244cefSSai Prakash Ranjan 279624244cefSSai Prakash Ranjan in-ports { 279724244cefSSai Prakash Ranjan #address-cells = <1>; 279824244cefSSai Prakash Ranjan #size-cells = <0>; 279924244cefSSai Prakash Ranjan 280024244cefSSai Prakash Ranjan port@4 { 280124244cefSSai Prakash Ranjan reg = <4>; 280224244cefSSai Prakash Ranjan funnel1_in4: endpoint { 280324244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_out>; 280424244cefSSai Prakash Ranjan }; 280524244cefSSai Prakash Ranjan }; 280624244cefSSai Prakash Ranjan }; 280724244cefSSai Prakash Ranjan }; 280824244cefSSai Prakash Ranjan 280924244cefSSai Prakash Ranjan funnel@6043000 { 281024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 281124244cefSSai Prakash Ranjan reg = <0 0x06043000 0 0x1000>; 281224244cefSSai Prakash Ranjan 281324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 281424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 281524244cefSSai Prakash Ranjan 281624244cefSSai Prakash Ranjan out-ports { 281724244cefSSai Prakash Ranjan port { 281824244cefSSai Prakash Ranjan funnel2_out: endpoint { 281924244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_in2>; 282024244cefSSai Prakash Ranjan }; 282124244cefSSai Prakash Ranjan }; 282224244cefSSai Prakash Ranjan }; 282324244cefSSai Prakash Ranjan 282424244cefSSai Prakash Ranjan in-ports { 282524244cefSSai Prakash Ranjan #address-cells = <1>; 282624244cefSSai Prakash Ranjan #size-cells = <0>; 282724244cefSSai Prakash Ranjan 282824244cefSSai Prakash Ranjan port@2 { 282924244cefSSai Prakash Ranjan reg = <2>; 283024244cefSSai Prakash Ranjan funnel2_in2: endpoint { 283124244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_out>; 283224244cefSSai Prakash Ranjan }; 283324244cefSSai Prakash Ranjan }; 283424244cefSSai Prakash Ranjan }; 283524244cefSSai Prakash Ranjan }; 283624244cefSSai Prakash Ranjan 283724244cefSSai Prakash Ranjan funnel@6045000 { 283824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 283924244cefSSai Prakash Ranjan reg = <0 0x06045000 0 0x1000>; 284024244cefSSai Prakash Ranjan 284124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 284224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 284324244cefSSai Prakash Ranjan 284424244cefSSai Prakash Ranjan out-ports { 284524244cefSSai Prakash Ranjan port { 284624244cefSSai Prakash Ranjan merge_funnel_out: endpoint { 284724244cefSSai Prakash Ranjan remote-endpoint = <&etf_in>; 284824244cefSSai Prakash Ranjan }; 284924244cefSSai Prakash Ranjan }; 285024244cefSSai Prakash Ranjan }; 285124244cefSSai Prakash Ranjan 285224244cefSSai Prakash Ranjan in-ports { 285324244cefSSai Prakash Ranjan #address-cells = <1>; 285424244cefSSai Prakash Ranjan #size-cells = <0>; 285524244cefSSai Prakash Ranjan 285624244cefSSai Prakash Ranjan port@0 { 285724244cefSSai Prakash Ranjan reg = <0>; 285824244cefSSai Prakash Ranjan merge_funnel_in0: endpoint { 285924244cefSSai Prakash Ranjan remote-endpoint = <&funnel0_out>; 286024244cefSSai Prakash Ranjan }; 286124244cefSSai Prakash Ranjan }; 286224244cefSSai Prakash Ranjan 286324244cefSSai Prakash Ranjan port@1 { 286424244cefSSai Prakash Ranjan reg = <1>; 286524244cefSSai Prakash Ranjan merge_funnel_in1: endpoint { 286624244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_out>; 286724244cefSSai Prakash Ranjan }; 286824244cefSSai Prakash Ranjan }; 286924244cefSSai Prakash Ranjan 287024244cefSSai Prakash Ranjan port@2 { 287124244cefSSai Prakash Ranjan reg = <2>; 287224244cefSSai Prakash Ranjan merge_funnel_in2: endpoint { 287324244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_out>; 287424244cefSSai Prakash Ranjan }; 287524244cefSSai Prakash Ranjan }; 287624244cefSSai Prakash Ranjan }; 287724244cefSSai Prakash Ranjan }; 287824244cefSSai Prakash Ranjan 287924244cefSSai Prakash Ranjan replicator@6046000 { 288024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 288124244cefSSai Prakash Ranjan reg = <0 0x06046000 0 0x1000>; 288224244cefSSai Prakash Ranjan 288324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 288424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 288524244cefSSai Prakash Ranjan 288624244cefSSai Prakash Ranjan out-ports { 288724244cefSSai Prakash Ranjan #address-cells = <1>; 288824244cefSSai Prakash Ranjan #size-cells = <0>; 288924244cefSSai Prakash Ranjan 289024244cefSSai Prakash Ranjan port@0 { 289124244cefSSai Prakash Ranjan reg = <0>; 289224244cefSSai Prakash Ranjan replicator_out0: endpoint { 289324244cefSSai Prakash Ranjan remote-endpoint = <&etr_in>; 289424244cefSSai Prakash Ranjan }; 289524244cefSSai Prakash Ranjan }; 289624244cefSSai Prakash Ranjan 289724244cefSSai Prakash Ranjan port@1 { 289824244cefSSai Prakash Ranjan reg = <1>; 289924244cefSSai Prakash Ranjan replicator_out1: endpoint { 290024244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_in>; 290124244cefSSai Prakash Ranjan }; 290224244cefSSai Prakash Ranjan }; 290324244cefSSai Prakash Ranjan }; 290424244cefSSai Prakash Ranjan 290524244cefSSai Prakash Ranjan in-ports { 290624244cefSSai Prakash Ranjan port { 290724244cefSSai Prakash Ranjan replicator_in0: endpoint { 290824244cefSSai Prakash Ranjan remote-endpoint = <&etf_out>; 290924244cefSSai Prakash Ranjan }; 291024244cefSSai Prakash Ranjan }; 291124244cefSSai Prakash Ranjan }; 291224244cefSSai Prakash Ranjan }; 291324244cefSSai Prakash Ranjan 291424244cefSSai Prakash Ranjan etf@6047000 { 291524244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 291624244cefSSai Prakash Ranjan reg = <0 0x06047000 0 0x1000>; 291724244cefSSai Prakash Ranjan 291824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 291924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 292024244cefSSai Prakash Ranjan 292124244cefSSai Prakash Ranjan out-ports { 292224244cefSSai Prakash Ranjan port { 292324244cefSSai Prakash Ranjan etf_out: endpoint { 292424244cefSSai Prakash Ranjan remote-endpoint = <&replicator_in0>; 292524244cefSSai Prakash Ranjan }; 292624244cefSSai Prakash Ranjan }; 292724244cefSSai Prakash Ranjan }; 292824244cefSSai Prakash Ranjan 292924244cefSSai Prakash Ranjan in-ports { 293024244cefSSai Prakash Ranjan port { 293124244cefSSai Prakash Ranjan etf_in: endpoint { 293224244cefSSai Prakash Ranjan remote-endpoint = <&merge_funnel_out>; 293324244cefSSai Prakash Ranjan }; 293424244cefSSai Prakash Ranjan }; 293524244cefSSai Prakash Ranjan }; 293624244cefSSai Prakash Ranjan }; 293724244cefSSai Prakash Ranjan 293824244cefSSai Prakash Ranjan etr@6048000 { 293924244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 294024244cefSSai Prakash Ranjan reg = <0 0x06048000 0 0x1000>; 294124244cefSSai Prakash Ranjan iommus = <&apps_smmu 0x05e0 0x0>; 294224244cefSSai Prakash Ranjan 294324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 294424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 294524244cefSSai Prakash Ranjan arm,scatter-gather; 294624244cefSSai Prakash Ranjan 294724244cefSSai Prakash Ranjan in-ports { 294824244cefSSai Prakash Ranjan port { 294924244cefSSai Prakash Ranjan etr_in: endpoint { 295024244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out0>; 295124244cefSSai Prakash Ranjan }; 295224244cefSSai Prakash Ranjan }; 295324244cefSSai Prakash Ranjan }; 295424244cefSSai Prakash Ranjan }; 295524244cefSSai Prakash Ranjan 295624244cefSSai Prakash Ranjan replicator@604a000 { 295724244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 295824244cefSSai Prakash Ranjan reg = <0 0x0604a000 0 0x1000>; 295924244cefSSai Prakash Ranjan 296024244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 296124244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 296224244cefSSai Prakash Ranjan 296324244cefSSai Prakash Ranjan out-ports { 296424244cefSSai Prakash Ranjan #address-cells = <1>; 296524244cefSSai Prakash Ranjan #size-cells = <0>; 296624244cefSSai Prakash Ranjan 296724244cefSSai Prakash Ranjan port@1 { 296824244cefSSai Prakash Ranjan reg = <1>; 296924244cefSSai Prakash Ranjan replicator1_out: endpoint { 297024244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_in>; 297124244cefSSai Prakash Ranjan }; 297224244cefSSai Prakash Ranjan }; 297324244cefSSai Prakash Ranjan }; 297424244cefSSai Prakash Ranjan 297524244cefSSai Prakash Ranjan in-ports { 297624244cefSSai Prakash Ranjan 2977cdb7f0e9SMao Jinlong port { 297824244cefSSai Prakash Ranjan replicator1_in: endpoint { 297924244cefSSai Prakash Ranjan remote-endpoint = <&replicator_out1>; 298024244cefSSai Prakash Ranjan }; 298124244cefSSai Prakash Ranjan }; 298224244cefSSai Prakash Ranjan }; 298324244cefSSai Prakash Ranjan }; 298424244cefSSai Prakash Ranjan 298524244cefSSai Prakash Ranjan funnel@6b08000 { 298624244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 298724244cefSSai Prakash Ranjan reg = <0 0x06b08000 0 0x1000>; 298824244cefSSai Prakash Ranjan 298924244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 299024244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 299124244cefSSai Prakash Ranjan 299224244cefSSai Prakash Ranjan out-ports { 299324244cefSSai Prakash Ranjan port { 299424244cefSSai Prakash Ranjan swao_funnel_out: endpoint { 299524244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_in>; 299624244cefSSai Prakash Ranjan }; 299724244cefSSai Prakash Ranjan }; 299824244cefSSai Prakash Ranjan }; 299924244cefSSai Prakash Ranjan 300024244cefSSai Prakash Ranjan in-ports { 300124244cefSSai Prakash Ranjan #address-cells = <1>; 300224244cefSSai Prakash Ranjan #size-cells = <0>; 300324244cefSSai Prakash Ranjan 300424244cefSSai Prakash Ranjan port@6 { 300524244cefSSai Prakash Ranjan reg = <6>; 300624244cefSSai Prakash Ranjan swao_funnel_in: endpoint { 300724244cefSSai Prakash Ranjan remote-endpoint = <&replicator1_out>; 300824244cefSSai Prakash Ranjan }; 300924244cefSSai Prakash Ranjan }; 301024244cefSSai Prakash Ranjan }; 301124244cefSSai Prakash Ranjan }; 301224244cefSSai Prakash Ranjan 301324244cefSSai Prakash Ranjan etf@6b09000 { 301424244cefSSai Prakash Ranjan compatible = "arm,coresight-tmc", "arm,primecell"; 301524244cefSSai Prakash Ranjan reg = <0 0x06b09000 0 0x1000>; 301624244cefSSai Prakash Ranjan 301724244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 301824244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 301924244cefSSai Prakash Ranjan 302024244cefSSai Prakash Ranjan out-ports { 302124244cefSSai Prakash Ranjan port { 302224244cefSSai Prakash Ranjan swao_etf_out: endpoint { 302324244cefSSai Prakash Ranjan remote-endpoint = <&swao_replicator_in>; 302424244cefSSai Prakash Ranjan }; 302524244cefSSai Prakash Ranjan }; 302624244cefSSai Prakash Ranjan }; 302724244cefSSai Prakash Ranjan 302824244cefSSai Prakash Ranjan in-ports { 302924244cefSSai Prakash Ranjan port { 303024244cefSSai Prakash Ranjan swao_etf_in: endpoint { 303124244cefSSai Prakash Ranjan remote-endpoint = <&swao_funnel_out>; 303224244cefSSai Prakash Ranjan }; 303324244cefSSai Prakash Ranjan }; 303424244cefSSai Prakash Ranjan }; 303524244cefSSai Prakash Ranjan }; 303624244cefSSai Prakash Ranjan 303724244cefSSai Prakash Ranjan replicator@6b0a000 { 303824244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 303924244cefSSai Prakash Ranjan reg = <0 0x06b0a000 0 0x1000>; 304024244cefSSai Prakash Ranjan 304124244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 304224244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 304324244cefSSai Prakash Ranjan qcom,replicator-loses-context; 304424244cefSSai Prakash Ranjan 304524244cefSSai Prakash Ranjan out-ports { 304624244cefSSai Prakash Ranjan port { 304724244cefSSai Prakash Ranjan swao_replicator_out: endpoint { 304824244cefSSai Prakash Ranjan remote-endpoint = <&funnel1_in4>; 304924244cefSSai Prakash Ranjan }; 305024244cefSSai Prakash Ranjan }; 305124244cefSSai Prakash Ranjan }; 305224244cefSSai Prakash Ranjan 305324244cefSSai Prakash Ranjan in-ports { 305424244cefSSai Prakash Ranjan port { 305524244cefSSai Prakash Ranjan swao_replicator_in: endpoint { 305624244cefSSai Prakash Ranjan remote-endpoint = <&swao_etf_out>; 305724244cefSSai Prakash Ranjan }; 305824244cefSSai Prakash Ranjan }; 305924244cefSSai Prakash Ranjan }; 306024244cefSSai Prakash Ranjan }; 306124244cefSSai Prakash Ranjan 306224244cefSSai Prakash Ranjan etm@7040000 { 306324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 306424244cefSSai Prakash Ranjan reg = <0 0x07040000 0 0x1000>; 306524244cefSSai Prakash Ranjan 306624244cefSSai Prakash Ranjan cpu = <&CPU0>; 306724244cefSSai Prakash Ranjan 306824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 306924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 307024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 307124244cefSSai Prakash Ranjan qcom,skip-power-up; 307224244cefSSai Prakash Ranjan 307324244cefSSai Prakash Ranjan out-ports { 307424244cefSSai Prakash Ranjan port { 307524244cefSSai Prakash Ranjan etm0_out: endpoint { 307624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in0>; 307724244cefSSai Prakash Ranjan }; 307824244cefSSai Prakash Ranjan }; 307924244cefSSai Prakash Ranjan }; 308024244cefSSai Prakash Ranjan }; 308124244cefSSai Prakash Ranjan 308224244cefSSai Prakash Ranjan etm@7140000 { 308324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 308424244cefSSai Prakash Ranjan reg = <0 0x07140000 0 0x1000>; 308524244cefSSai Prakash Ranjan 308624244cefSSai Prakash Ranjan cpu = <&CPU1>; 308724244cefSSai Prakash Ranjan 308824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 308924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 309024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 309124244cefSSai Prakash Ranjan qcom,skip-power-up; 309224244cefSSai Prakash Ranjan 309324244cefSSai Prakash Ranjan out-ports { 309424244cefSSai Prakash Ranjan port { 309524244cefSSai Prakash Ranjan etm1_out: endpoint { 309624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in1>; 309724244cefSSai Prakash Ranjan }; 309824244cefSSai Prakash Ranjan }; 309924244cefSSai Prakash Ranjan }; 310024244cefSSai Prakash Ranjan }; 310124244cefSSai Prakash Ranjan 310224244cefSSai Prakash Ranjan etm@7240000 { 310324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 310424244cefSSai Prakash Ranjan reg = <0 0x07240000 0 0x1000>; 310524244cefSSai Prakash Ranjan 310624244cefSSai Prakash Ranjan cpu = <&CPU2>; 310724244cefSSai Prakash Ranjan 310824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 310924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 311024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 311124244cefSSai Prakash Ranjan qcom,skip-power-up; 311224244cefSSai Prakash Ranjan 311324244cefSSai Prakash Ranjan out-ports { 311424244cefSSai Prakash Ranjan port { 311524244cefSSai Prakash Ranjan etm2_out: endpoint { 311624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in2>; 311724244cefSSai Prakash Ranjan }; 311824244cefSSai Prakash Ranjan }; 311924244cefSSai Prakash Ranjan }; 312024244cefSSai Prakash Ranjan }; 312124244cefSSai Prakash Ranjan 312224244cefSSai Prakash Ranjan etm@7340000 { 312324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 312424244cefSSai Prakash Ranjan reg = <0 0x07340000 0 0x1000>; 312524244cefSSai Prakash Ranjan 312624244cefSSai Prakash Ranjan cpu = <&CPU3>; 312724244cefSSai Prakash Ranjan 312824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 312924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 313024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 313124244cefSSai Prakash Ranjan qcom,skip-power-up; 313224244cefSSai Prakash Ranjan 313324244cefSSai Prakash Ranjan out-ports { 313424244cefSSai Prakash Ranjan port { 313524244cefSSai Prakash Ranjan etm3_out: endpoint { 313624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in3>; 313724244cefSSai Prakash Ranjan }; 313824244cefSSai Prakash Ranjan }; 313924244cefSSai Prakash Ranjan }; 314024244cefSSai Prakash Ranjan }; 314124244cefSSai Prakash Ranjan 314224244cefSSai Prakash Ranjan etm@7440000 { 314324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 314424244cefSSai Prakash Ranjan reg = <0 0x07440000 0 0x1000>; 314524244cefSSai Prakash Ranjan 314624244cefSSai Prakash Ranjan cpu = <&CPU4>; 314724244cefSSai Prakash Ranjan 314824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 314924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 315024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 315124244cefSSai Prakash Ranjan qcom,skip-power-up; 315224244cefSSai Prakash Ranjan 315324244cefSSai Prakash Ranjan out-ports { 315424244cefSSai Prakash Ranjan port { 315524244cefSSai Prakash Ranjan etm4_out: endpoint { 315624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in4>; 315724244cefSSai Prakash Ranjan }; 315824244cefSSai Prakash Ranjan }; 315924244cefSSai Prakash Ranjan }; 316024244cefSSai Prakash Ranjan }; 316124244cefSSai Prakash Ranjan 316224244cefSSai Prakash Ranjan etm@7540000 { 316324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 316424244cefSSai Prakash Ranjan reg = <0 0x07540000 0 0x1000>; 316524244cefSSai Prakash Ranjan 316624244cefSSai Prakash Ranjan cpu = <&CPU5>; 316724244cefSSai Prakash Ranjan 316824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 316924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 317024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 317124244cefSSai Prakash Ranjan qcom,skip-power-up; 317224244cefSSai Prakash Ranjan 317324244cefSSai Prakash Ranjan out-ports { 317424244cefSSai Prakash Ranjan port { 317524244cefSSai Prakash Ranjan etm5_out: endpoint { 317624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in5>; 317724244cefSSai Prakash Ranjan }; 317824244cefSSai Prakash Ranjan }; 317924244cefSSai Prakash Ranjan }; 318024244cefSSai Prakash Ranjan }; 318124244cefSSai Prakash Ranjan 318224244cefSSai Prakash Ranjan etm@7640000 { 318324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 318424244cefSSai Prakash Ranjan reg = <0 0x07640000 0 0x1000>; 318524244cefSSai Prakash Ranjan 318624244cefSSai Prakash Ranjan cpu = <&CPU6>; 318724244cefSSai Prakash Ranjan 318824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 318924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 319024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 319124244cefSSai Prakash Ranjan qcom,skip-power-up; 319224244cefSSai Prakash Ranjan 319324244cefSSai Prakash Ranjan out-ports { 319424244cefSSai Prakash Ranjan port { 319524244cefSSai Prakash Ranjan etm6_out: endpoint { 319624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in6>; 319724244cefSSai Prakash Ranjan }; 319824244cefSSai Prakash Ranjan }; 319924244cefSSai Prakash Ranjan }; 320024244cefSSai Prakash Ranjan }; 320124244cefSSai Prakash Ranjan 320224244cefSSai Prakash Ranjan etm@7740000 { 320324244cefSSai Prakash Ranjan compatible = "arm,coresight-etm4x", "arm,primecell"; 320424244cefSSai Prakash Ranjan reg = <0 0x07740000 0 0x1000>; 320524244cefSSai Prakash Ranjan 320624244cefSSai Prakash Ranjan cpu = <&CPU7>; 320724244cefSSai Prakash Ranjan 320824244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 320924244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 321024244cefSSai Prakash Ranjan arm,coresight-loses-context-with-cpu; 321124244cefSSai Prakash Ranjan qcom,skip-power-up; 321224244cefSSai Prakash Ranjan 321324244cefSSai Prakash Ranjan out-ports { 321424244cefSSai Prakash Ranjan port { 321524244cefSSai Prakash Ranjan etm7_out: endpoint { 321624244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_in7>; 321724244cefSSai Prakash Ranjan }; 321824244cefSSai Prakash Ranjan }; 321924244cefSSai Prakash Ranjan }; 322024244cefSSai Prakash Ranjan }; 322124244cefSSai Prakash Ranjan 322224244cefSSai Prakash Ranjan funnel@7800000 { /* APSS Funnel */ 322324244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 322424244cefSSai Prakash Ranjan reg = <0 0x07800000 0 0x1000>; 322524244cefSSai Prakash Ranjan 322624244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 322724244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 322824244cefSSai Prakash Ranjan 322924244cefSSai Prakash Ranjan out-ports { 323024244cefSSai Prakash Ranjan port { 323124244cefSSai Prakash Ranjan apss_funnel_out: endpoint { 323224244cefSSai Prakash Ranjan remote-endpoint = <&apss_merge_funnel_in>; 323324244cefSSai Prakash Ranjan }; 323424244cefSSai Prakash Ranjan }; 323524244cefSSai Prakash Ranjan }; 323624244cefSSai Prakash Ranjan 323724244cefSSai Prakash Ranjan in-ports { 323824244cefSSai Prakash Ranjan #address-cells = <1>; 323924244cefSSai Prakash Ranjan #size-cells = <0>; 324024244cefSSai Prakash Ranjan 324124244cefSSai Prakash Ranjan port@0 { 324224244cefSSai Prakash Ranjan reg = <0>; 324324244cefSSai Prakash Ranjan apss_funnel_in0: endpoint { 324424244cefSSai Prakash Ranjan remote-endpoint = <&etm0_out>; 324524244cefSSai Prakash Ranjan }; 324624244cefSSai Prakash Ranjan }; 324724244cefSSai Prakash Ranjan 324824244cefSSai Prakash Ranjan port@1 { 324924244cefSSai Prakash Ranjan reg = <1>; 325024244cefSSai Prakash Ranjan apss_funnel_in1: endpoint { 325124244cefSSai Prakash Ranjan remote-endpoint = <&etm1_out>; 325224244cefSSai Prakash Ranjan }; 325324244cefSSai Prakash Ranjan }; 325424244cefSSai Prakash Ranjan 325524244cefSSai Prakash Ranjan port@2 { 325624244cefSSai Prakash Ranjan reg = <2>; 325724244cefSSai Prakash Ranjan apss_funnel_in2: endpoint { 325824244cefSSai Prakash Ranjan remote-endpoint = <&etm2_out>; 325924244cefSSai Prakash Ranjan }; 326024244cefSSai Prakash Ranjan }; 326124244cefSSai Prakash Ranjan 326224244cefSSai Prakash Ranjan port@3 { 326324244cefSSai Prakash Ranjan reg = <3>; 326424244cefSSai Prakash Ranjan apss_funnel_in3: endpoint { 326524244cefSSai Prakash Ranjan remote-endpoint = <&etm3_out>; 326624244cefSSai Prakash Ranjan }; 326724244cefSSai Prakash Ranjan }; 326824244cefSSai Prakash Ranjan 326924244cefSSai Prakash Ranjan port@4 { 327024244cefSSai Prakash Ranjan reg = <4>; 327124244cefSSai Prakash Ranjan apss_funnel_in4: endpoint { 327224244cefSSai Prakash Ranjan remote-endpoint = <&etm4_out>; 327324244cefSSai Prakash Ranjan }; 327424244cefSSai Prakash Ranjan }; 327524244cefSSai Prakash Ranjan 327624244cefSSai Prakash Ranjan port@5 { 327724244cefSSai Prakash Ranjan reg = <5>; 327824244cefSSai Prakash Ranjan apss_funnel_in5: endpoint { 327924244cefSSai Prakash Ranjan remote-endpoint = <&etm5_out>; 328024244cefSSai Prakash Ranjan }; 328124244cefSSai Prakash Ranjan }; 328224244cefSSai Prakash Ranjan 328324244cefSSai Prakash Ranjan port@6 { 328424244cefSSai Prakash Ranjan reg = <6>; 328524244cefSSai Prakash Ranjan apss_funnel_in6: endpoint { 328624244cefSSai Prakash Ranjan remote-endpoint = <&etm6_out>; 328724244cefSSai Prakash Ranjan }; 328824244cefSSai Prakash Ranjan }; 328924244cefSSai Prakash Ranjan 329024244cefSSai Prakash Ranjan port@7 { 329124244cefSSai Prakash Ranjan reg = <7>; 329224244cefSSai Prakash Ranjan apss_funnel_in7: endpoint { 329324244cefSSai Prakash Ranjan remote-endpoint = <&etm7_out>; 329424244cefSSai Prakash Ranjan }; 329524244cefSSai Prakash Ranjan }; 329624244cefSSai Prakash Ranjan }; 329724244cefSSai Prakash Ranjan }; 329824244cefSSai Prakash Ranjan 329924244cefSSai Prakash Ranjan funnel@7810000 { 330024244cefSSai Prakash Ranjan compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 330124244cefSSai Prakash Ranjan reg = <0 0x07810000 0 0x1000>; 330224244cefSSai Prakash Ranjan 330324244cefSSai Prakash Ranjan clocks = <&aoss_qmp>; 330424244cefSSai Prakash Ranjan clock-names = "apb_pclk"; 330524244cefSSai Prakash Ranjan 330624244cefSSai Prakash Ranjan out-ports { 330724244cefSSai Prakash Ranjan port { 330824244cefSSai Prakash Ranjan apss_merge_funnel_out: endpoint { 330924244cefSSai Prakash Ranjan remote-endpoint = <&funnel2_in2>; 331024244cefSSai Prakash Ranjan }; 331124244cefSSai Prakash Ranjan }; 331224244cefSSai Prakash Ranjan }; 331324244cefSSai Prakash Ranjan 331424244cefSSai Prakash Ranjan in-ports { 331524244cefSSai Prakash Ranjan port { 331624244cefSSai Prakash Ranjan apss_merge_funnel_in: endpoint { 331724244cefSSai Prakash Ranjan remote-endpoint = <&apss_funnel_out>; 331824244cefSSai Prakash Ranjan }; 331924244cefSSai Prakash Ranjan }; 332024244cefSSai Prakash Ranjan }; 332124244cefSSai Prakash Ranjan }; 332224244cefSSai Prakash Ranjan 332349076351SSibi Sankar remoteproc_cdsp: remoteproc@8300000 { 332449076351SSibi Sankar compatible = "qcom,sm8150-cdsp-pas"; 332549076351SSibi Sankar reg = <0x0 0x08300000 0x0 0x4040>; 332649076351SSibi Sankar 332749076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 332849076351SSibi Sankar <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 332949076351SSibi Sankar <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 333049076351SSibi Sankar <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 333149076351SSibi Sankar <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 333249076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 333349076351SSibi Sankar "handover", "stop-ack"; 333449076351SSibi Sankar 333549076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 333649076351SSibi Sankar clock-names = "xo"; 333749076351SSibi Sankar 3338a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 333949076351SSibi Sankar 334049076351SSibi Sankar memory-region = <&cdsp_mem>; 334149076351SSibi Sankar 3342d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 3343d9d327f6SSibi Sankar 334449076351SSibi Sankar qcom,smem-states = <&cdsp_smp2p_out 0>; 334549076351SSibi Sankar qcom,smem-state-names = "stop"; 334649076351SSibi Sankar 334749076351SSibi Sankar status = "disabled"; 334849076351SSibi Sankar 334949076351SSibi Sankar glink-edge { 335049076351SSibi Sankar interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 335149076351SSibi Sankar label = "cdsp"; 335249076351SSibi Sankar qcom,remote-pid = <5>; 335349076351SSibi Sankar mboxes = <&apss_shared 4>; 335481729330SBhupesh Sharma 335581729330SBhupesh Sharma fastrpc { 335681729330SBhupesh Sharma compatible = "qcom,fastrpc"; 335781729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 335881729330SBhupesh Sharma label = "cdsp"; 33598c8ce95bSJeya R qcom,non-secure-domain; 336081729330SBhupesh Sharma #address-cells = <1>; 336181729330SBhupesh Sharma #size-cells = <0>; 336281729330SBhupesh Sharma 336381729330SBhupesh Sharma compute-cb@1 { 336481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 336581729330SBhupesh Sharma reg = <1>; 33661d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1001 0x0460>; 336781729330SBhupesh Sharma }; 336881729330SBhupesh Sharma 336981729330SBhupesh Sharma compute-cb@2 { 337081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 337181729330SBhupesh Sharma reg = <2>; 33721d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1002 0x0460>; 337381729330SBhupesh Sharma }; 337481729330SBhupesh Sharma 337581729330SBhupesh Sharma compute-cb@3 { 337681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 337781729330SBhupesh Sharma reg = <3>; 33781d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1003 0x0460>; 337981729330SBhupesh Sharma }; 338081729330SBhupesh Sharma 338181729330SBhupesh Sharma compute-cb@4 { 338281729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 338381729330SBhupesh Sharma reg = <4>; 33841d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1004 0x0460>; 338581729330SBhupesh Sharma }; 338681729330SBhupesh Sharma 338781729330SBhupesh Sharma compute-cb@5 { 338881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 338981729330SBhupesh Sharma reg = <5>; 33901d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1005 0x0460>; 339181729330SBhupesh Sharma }; 339281729330SBhupesh Sharma 339381729330SBhupesh Sharma compute-cb@6 { 339481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 339581729330SBhupesh Sharma reg = <6>; 33961d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1006 0x0460>; 339781729330SBhupesh Sharma }; 339881729330SBhupesh Sharma 339981729330SBhupesh Sharma compute-cb@7 { 340081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 340181729330SBhupesh Sharma reg = <7>; 34021d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1007 0x0460>; 340381729330SBhupesh Sharma }; 340481729330SBhupesh Sharma 340581729330SBhupesh Sharma compute-cb@8 { 340681729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 340781729330SBhupesh Sharma reg = <8>; 34081d330a67SBhupesh Sharma iommus = <&apps_smmu 0x1008 0x0460>; 340981729330SBhupesh Sharma }; 341081729330SBhupesh Sharma 341181729330SBhupesh Sharma /* note: secure cb9 in downstream */ 341281729330SBhupesh Sharma }; 341349076351SSibi Sankar }; 341449076351SSibi Sankar }; 341549076351SSibi Sankar 3416b33d2868SJack Pham usb_1_hsphy: phy@88e2000 { 3417b33d2868SJack Pham compatible = "qcom,sm8150-usb-hs-phy", 3418b33d2868SJack Pham "qcom,usb-snps-hs-7nm-phy"; 3419b33d2868SJack Pham reg = <0 0x088e2000 0 0x400>; 3420b33d2868SJack Pham status = "disabled"; 3421b33d2868SJack Pham #phy-cells = <0>; 3422b33d2868SJack Pham 3423b33d2868SJack Pham clocks = <&rpmhcc RPMH_CXO_CLK>; 3424b33d2868SJack Pham clock-names = "ref"; 3425b33d2868SJack Pham 3426b33d2868SJack Pham resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3427b33d2868SJack Pham }; 3428b33d2868SJack Pham 34290c9dde0dSJonathan Marek usb_2_hsphy: phy@88e3000 { 34300c9dde0dSJonathan Marek compatible = "qcom,sm8150-usb-hs-phy", 34310c9dde0dSJonathan Marek "qcom,usb-snps-hs-7nm-phy"; 34320c9dde0dSJonathan Marek reg = <0 0x088e3000 0 0x400>; 34330c9dde0dSJonathan Marek status = "disabled"; 34340c9dde0dSJonathan Marek #phy-cells = <0>; 34350c9dde0dSJonathan Marek 34360c9dde0dSJonathan Marek clocks = <&rpmhcc RPMH_CXO_CLK>; 34370c9dde0dSJonathan Marek clock-names = "ref"; 34380c9dde0dSJonathan Marek 34390c9dde0dSJonathan Marek resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 34400c9dde0dSJonathan Marek }; 34410c9dde0dSJonathan Marek 3442b33d2868SJack Pham usb_1_qmpphy: phy@88e9000 { 3443b33d2868SJack Pham compatible = "qcom,sm8150-qmp-usb3-phy"; 3444b33d2868SJack Pham reg = <0 0x088e9000 0 0x18c>, 3445b33d2868SJack Pham <0 0x088e8000 0 0x10>; 3446b33d2868SJack Pham status = "disabled"; 3447b33d2868SJack Pham #address-cells = <2>; 3448b33d2868SJack Pham #size-cells = <2>; 3449b33d2868SJack Pham ranges; 3450b33d2868SJack Pham 3451b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3452b33d2868SJack Pham <&rpmhcc RPMH_CXO_CLK>, 3453b33d2868SJack Pham <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3454b33d2868SJack Pham <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3455b33d2868SJack Pham clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3456b33d2868SJack Pham 3457b33d2868SJack Pham resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3458b33d2868SJack Pham <&gcc GCC_USB3_PHY_PRIM_BCR>; 3459b33d2868SJack Pham reset-names = "phy", "common"; 3460b33d2868SJack Pham 34611351512fSShawn Guo usb_1_ssphy: phy@88e9200 { 3462b33d2868SJack Pham reg = <0 0x088e9200 0 0x200>, 3463b33d2868SJack Pham <0 0x088e9400 0 0x200>, 3464b33d2868SJack Pham <0 0x088e9c00 0 0x218>, 3465b33d2868SJack Pham <0 0x088e9600 0 0x200>, 3466b33d2868SJack Pham <0 0x088e9800 0 0x200>, 3467b33d2868SJack Pham <0 0x088e9a00 0 0x100>; 34687178d4ccSJonathan Marek #clock-cells = <0>; 3469b33d2868SJack Pham #phy-cells = <0>; 3470b33d2868SJack Pham clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3471b33d2868SJack Pham clock-names = "pipe0"; 3472b33d2868SJack Pham clock-output-names = "usb3_phy_pipe_clk_src"; 3473b33d2868SJack Pham }; 3474b33d2868SJack Pham }; 3475b33d2868SJack Pham 34760c9dde0dSJonathan Marek usb_2_qmpphy: phy@88eb000 { 34770c9dde0dSJonathan Marek compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 34780c9dde0dSJonathan Marek reg = <0 0x088eb000 0 0x200>; 34790c9dde0dSJonathan Marek status = "disabled"; 34800c9dde0dSJonathan Marek #address-cells = <2>; 34810c9dde0dSJonathan Marek #size-cells = <2>; 34820c9dde0dSJonathan Marek ranges; 34830c9dde0dSJonathan Marek 34840c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 34850c9dde0dSJonathan Marek <&rpmhcc RPMH_CXO_CLK>, 34860c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>, 34870c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 34880c9dde0dSJonathan Marek clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 34890c9dde0dSJonathan Marek 34900c9dde0dSJonathan Marek resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 34910c9dde0dSJonathan Marek <&gcc GCC_USB3_PHY_SEC_BCR>; 34920c9dde0dSJonathan Marek reset-names = "phy", "common"; 34930c9dde0dSJonathan Marek 34941351512fSShawn Guo usb_2_ssphy: phy@88eb200 { 34950c9dde0dSJonathan Marek reg = <0 0x088eb200 0 0x200>, 34960c9dde0dSJonathan Marek <0 0x088eb400 0 0x200>, 34970c9dde0dSJonathan Marek <0 0x088eb800 0 0x800>, 34980c9dde0dSJonathan Marek <0 0x088eb600 0 0x200>; 34997178d4ccSJonathan Marek #clock-cells = <0>; 35000c9dde0dSJonathan Marek #phy-cells = <0>; 35010c9dde0dSJonathan Marek clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 35020c9dde0dSJonathan Marek clock-names = "pipe0"; 35030c9dde0dSJonathan Marek clock-output-names = "usb3_uni_phy_pipe_clk_src"; 35040c9dde0dSJonathan Marek }; 35050c9dde0dSJonathan Marek }; 35060c9dde0dSJonathan Marek 350796bb736fSBhupesh Sharma sdhc_2: mmc@8804000 { 3508876644c7SBhupesh Sharma compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3509876644c7SBhupesh Sharma reg = <0 0x08804000 0 0x1000>; 3510876644c7SBhupesh Sharma 3511876644c7SBhupesh Sharma interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3512876644c7SBhupesh Sharma <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3513876644c7SBhupesh Sharma interrupt-names = "hc_irq", "pwr_irq"; 3514876644c7SBhupesh Sharma 3515876644c7SBhupesh Sharma clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3516876644c7SBhupesh Sharma <&gcc GCC_SDCC2_APPS_CLK>, 3517876644c7SBhupesh Sharma <&rpmhcc RPMH_CXO_CLK>; 3518876644c7SBhupesh Sharma clock-names = "iface", "core", "xo"; 351995830090SBhupesh Sharma iommus = <&apps_smmu 0x6a0 0x0>; 3520876644c7SBhupesh Sharma qcom,dll-config = <0x0007642c>; 3521876644c7SBhupesh Sharma qcom,ddr-config = <0x80040868>; 3522876644c7SBhupesh Sharma power-domains = <&rpmhpd 0>; 3523876644c7SBhupesh Sharma operating-points-v2 = <&sdhc2_opp_table>; 3524876644c7SBhupesh Sharma 3525876644c7SBhupesh Sharma status = "disabled"; 3526876644c7SBhupesh Sharma 35270e3e6546SKrzysztof Kozlowski sdhc2_opp_table: opp-table { 3528876644c7SBhupesh Sharma compatible = "operating-points-v2"; 3529876644c7SBhupesh Sharma 3530876644c7SBhupesh Sharma opp-19200000 { 3531876644c7SBhupesh Sharma opp-hz = /bits/ 64 <19200000>; 3532876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_min_svs>; 3533876644c7SBhupesh Sharma }; 3534876644c7SBhupesh Sharma 3535876644c7SBhupesh Sharma opp-50000000 { 3536876644c7SBhupesh Sharma opp-hz = /bits/ 64 <50000000>; 3537876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_low_svs>; 3538876644c7SBhupesh Sharma }; 3539876644c7SBhupesh Sharma 3540876644c7SBhupesh Sharma opp-100000000 { 3541876644c7SBhupesh Sharma opp-hz = /bits/ 64 <100000000>; 3542876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs>; 3543876644c7SBhupesh Sharma }; 3544876644c7SBhupesh Sharma 3545876644c7SBhupesh Sharma opp-202000000 { 3546876644c7SBhupesh Sharma opp-hz = /bits/ 64 <202000000>; 3547876644c7SBhupesh Sharma required-opps = <&rpmhpd_opp_svs_l1>; 3548876644c7SBhupesh Sharma }; 3549876644c7SBhupesh Sharma }; 3550876644c7SBhupesh Sharma }; 3551876644c7SBhupesh Sharma 35525dc43d3bSBhupesh Sharma dc_noc: interconnect@9160000 { 35535dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-dc-noc"; 35545dc43d3bSBhupesh Sharma reg = <0 0x09160000 0 0x3200>; 355597c28902SAbel Vesa #interconnect-cells = <2>; 35565dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 35575dc43d3bSBhupesh Sharma }; 35585dc43d3bSBhupesh Sharma 35595dc43d3bSBhupesh Sharma gem_noc: interconnect@9680000 { 35605dc43d3bSBhupesh Sharma compatible = "qcom,sm8150-gem-noc"; 35615dc43d3bSBhupesh Sharma reg = <0 0x09680000 0 0x3e200>; 356297c28902SAbel Vesa #interconnect-cells = <2>; 35635dc43d3bSBhupesh Sharma qcom,bcm-voters = <&apps_bcm_voter>; 35645dc43d3bSBhupesh Sharma }; 35655dc43d3bSBhupesh Sharma 3566b33d2868SJack Pham usb_1: usb@a6f8800 { 3567b33d2868SJack Pham compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3568b33d2868SJack Pham reg = <0 0x0a6f8800 0 0x400>; 3569b33d2868SJack Pham status = "disabled"; 3570b33d2868SJack Pham #address-cells = <2>; 3571b33d2868SJack Pham #size-cells = <2>; 3572b33d2868SJack Pham ranges; 3573b33d2868SJack Pham dma-ranges; 3574b33d2868SJack Pham 3575b33d2868SJack Pham clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3576b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3577b33d2868SJack Pham <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3578b33d2868SJack Pham <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 35798d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3580b33d2868SJack Pham <&gcc GCC_USB3_SEC_CLKREF_CLK>; 35818d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 35828d5fd4e4SKrzysztof Kozlowski "core", 35838d5fd4e4SKrzysztof Kozlowski "iface", 35848d5fd4e4SKrzysztof Kozlowski "sleep", 35858d5fd4e4SKrzysztof Kozlowski "mock_utmi", 35868d5fd4e4SKrzysztof Kozlowski "xo"; 3587b33d2868SJack Pham 3588b33d2868SJack Pham assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3589b33d2868SJack Pham <&gcc GCC_USB30_PRIM_MASTER_CLK>; 359079493db5SJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 3591b33d2868SJack Pham 3592b0a9aec3SJohan Hovold interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 359300804fabSJohan Hovold <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3594b0a9aec3SJohan Hovold <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3595b0a9aec3SJohan Hovold <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 3596b33d2868SJack Pham interrupt-names = "hs_phy_irq", "ss_phy_irq", 3597b33d2868SJack Pham "dm_hs_phy_irq", "dp_hs_phy_irq"; 3598b33d2868SJack Pham 3599b33d2868SJack Pham power-domains = <&gcc USB30_PRIM_GDSC>; 3600b33d2868SJack Pham 3601b33d2868SJack Pham resets = <&gcc GCC_USB30_PRIM_BCR>; 3602b33d2868SJack Pham 3603c2998e9aSAbel Vesa interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3604c2998e9aSAbel Vesa <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3605c2998e9aSAbel Vesa interconnect-names = "usb-ddr", "apps-usb"; 3606c2998e9aSAbel Vesa 3607b77a1c4dSKrzysztof Kozlowski usb_1_dwc3: usb@a600000 { 3608b33d2868SJack Pham compatible = "snps,dwc3"; 3609b33d2868SJack Pham reg = <0 0x0a600000 0 0xcd00>; 3610b33d2868SJack Pham interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 361148156232SJonathan Marek iommus = <&apps_smmu 0x140 0>; 3612b33d2868SJack Pham snps,dis_u2_susphy_quirk; 3613b33d2868SJack Pham snps,dis_enblslpm_quirk; 3614b33d2868SJack Pham phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3615b33d2868SJack Pham phy-names = "usb2-phy", "usb3-phy"; 3616b33d2868SJack Pham }; 3617b33d2868SJack Pham }; 3618b33d2868SJack Pham 36190c9dde0dSJonathan Marek usb_2: usb@a8f8800 { 36200c9dde0dSJonathan Marek compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 36210c9dde0dSJonathan Marek reg = <0 0x0a8f8800 0 0x400>; 36220c9dde0dSJonathan Marek status = "disabled"; 36230c9dde0dSJonathan Marek #address-cells = <2>; 36240c9dde0dSJonathan Marek #size-cells = <2>; 36250c9dde0dSJonathan Marek ranges; 36260c9dde0dSJonathan Marek dma-ranges; 36270c9dde0dSJonathan Marek 36280c9dde0dSJonathan Marek clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 36290c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>, 36300c9dde0dSJonathan Marek <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 36310c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_SLEEP_CLK>, 36328d5fd4e4SKrzysztof Kozlowski <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 36330c9dde0dSJonathan Marek <&gcc GCC_USB3_SEC_CLKREF_CLK>; 36348d5fd4e4SKrzysztof Kozlowski clock-names = "cfg_noc", 36358d5fd4e4SKrzysztof Kozlowski "core", 36368d5fd4e4SKrzysztof Kozlowski "iface", 36378d5fd4e4SKrzysztof Kozlowski "sleep", 36388d5fd4e4SKrzysztof Kozlowski "mock_utmi", 36398d5fd4e4SKrzysztof Kozlowski "xo"; 36400c9dde0dSJonathan Marek 36410c9dde0dSJonathan Marek assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 36420c9dde0dSJonathan Marek <&gcc GCC_USB30_SEC_MASTER_CLK>; 36430c9dde0dSJonathan Marek assigned-clock-rates = <19200000>, <200000000>; 36440c9dde0dSJonathan Marek 3645b0a9aec3SJohan Hovold interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 364600804fabSJohan Hovold <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 3647b0a9aec3SJohan Hovold <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3648b0a9aec3SJohan Hovold <&pdc 11 IRQ_TYPE_EDGE_BOTH>; 36490c9dde0dSJonathan Marek interrupt-names = "hs_phy_irq", "ss_phy_irq", 36500c9dde0dSJonathan Marek "dm_hs_phy_irq", "dp_hs_phy_irq"; 36510c9dde0dSJonathan Marek 36520c9dde0dSJonathan Marek power-domains = <&gcc USB30_SEC_GDSC>; 36530c9dde0dSJonathan Marek 36540c9dde0dSJonathan Marek resets = <&gcc GCC_USB30_SEC_BCR>; 36550c9dde0dSJonathan Marek 3656c2998e9aSAbel Vesa interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3657c2998e9aSAbel Vesa <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3658c2998e9aSAbel Vesa interconnect-names = "usb-ddr", "apps-usb"; 3659c2998e9aSAbel Vesa 36602aa2b50dSBhupesh Sharma usb_2_dwc3: usb@a800000 { 36610c9dde0dSJonathan Marek compatible = "snps,dwc3"; 36620c9dde0dSJonathan Marek reg = <0 0x0a800000 0 0xcd00>; 36630c9dde0dSJonathan Marek interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 36640c9dde0dSJonathan Marek iommus = <&apps_smmu 0x160 0>; 36650c9dde0dSJonathan Marek snps,dis_u2_susphy_quirk; 36660c9dde0dSJonathan Marek snps,dis_enblslpm_quirk; 36670c9dde0dSJonathan Marek phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 36680c9dde0dSJonathan Marek phy-names = "usb2-phy", "usb3-phy"; 36690c9dde0dSJonathan Marek }; 36700c9dde0dSJonathan Marek }; 36710c9dde0dSJonathan Marek 36726acb71fdSJonathan Marek camnoc_virt: interconnect@ac00000 { 36736acb71fdSJonathan Marek compatible = "qcom,sm8150-camnoc-virt"; 36746acb71fdSJonathan Marek reg = <0 0x0ac00000 0 0x1000>; 367597c28902SAbel Vesa #interconnect-cells = <2>; 36766acb71fdSJonathan Marek qcom,bcm-voters = <&apps_bcm_voter>; 36776acb71fdSJonathan Marek }; 36786acb71fdSJonathan Marek 367998874a46SKonrad Dybcio mdss: display-subsystem@ae00000 { 368098874a46SKonrad Dybcio compatible = "qcom,sm8150-mdss"; 368198874a46SKonrad Dybcio reg = <0 0x0ae00000 0 0x1000>; 368298874a46SKonrad Dybcio reg-names = "mdss"; 368398874a46SKonrad Dybcio 368497c28902SAbel Vesa interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 368597c28902SAbel Vesa <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 368698874a46SKonrad Dybcio interconnect-names = "mdp0-mem", "mdp1-mem"; 368798874a46SKonrad Dybcio 368898874a46SKonrad Dybcio power-domains = <&dispcc MDSS_GDSC>; 368998874a46SKonrad Dybcio 369098874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 369198874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>, 369298874a46SKonrad Dybcio <&gcc GCC_DISP_SF_AXI_CLK>, 369398874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>; 369498874a46SKonrad Dybcio clock-names = "iface", "bus", "nrt_bus", "core"; 369598874a46SKonrad Dybcio 369698874a46SKonrad Dybcio interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 369798874a46SKonrad Dybcio interrupt-controller; 369898874a46SKonrad Dybcio #interrupt-cells = <1>; 369998874a46SKonrad Dybcio 370098874a46SKonrad Dybcio iommus = <&apps_smmu 0x800 0x420>; 370198874a46SKonrad Dybcio 370298874a46SKonrad Dybcio status = "disabled"; 370398874a46SKonrad Dybcio 370498874a46SKonrad Dybcio #address-cells = <2>; 370598874a46SKonrad Dybcio #size-cells = <2>; 370698874a46SKonrad Dybcio ranges; 370798874a46SKonrad Dybcio 370898874a46SKonrad Dybcio mdss_mdp: display-controller@ae01000 { 370998874a46SKonrad Dybcio compatible = "qcom,sm8150-dpu"; 371098874a46SKonrad Dybcio reg = <0 0x0ae01000 0 0x8f000>, 371198874a46SKonrad Dybcio <0 0x0aeb0000 0 0x2008>; 371298874a46SKonrad Dybcio reg-names = "mdp", "vbif"; 371398874a46SKonrad Dybcio 371498874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 371598874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>, 371698874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_MDP_CLK>, 371798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 371898874a46SKonrad Dybcio clock-names = "iface", "bus", "core", "vsync"; 371998874a46SKonrad Dybcio 372098874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 372198874a46SKonrad Dybcio assigned-clock-rates = <19200000>; 372298874a46SKonrad Dybcio 372398874a46SKonrad Dybcio operating-points-v2 = <&mdp_opp_table>; 372498874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 372598874a46SKonrad Dybcio 372698874a46SKonrad Dybcio interrupt-parent = <&mdss>; 372798874a46SKonrad Dybcio interrupts = <0>; 372898874a46SKonrad Dybcio 372998874a46SKonrad Dybcio ports { 373098874a46SKonrad Dybcio #address-cells = <1>; 373198874a46SKonrad Dybcio #size-cells = <0>; 373298874a46SKonrad Dybcio 373398874a46SKonrad Dybcio port@0 { 373498874a46SKonrad Dybcio reg = <0>; 373598874a46SKonrad Dybcio dpu_intf1_out: endpoint { 373698874a46SKonrad Dybcio remote-endpoint = <&mdss_dsi0_in>; 373798874a46SKonrad Dybcio }; 373898874a46SKonrad Dybcio }; 373998874a46SKonrad Dybcio 374098874a46SKonrad Dybcio port@1 { 374198874a46SKonrad Dybcio reg = <1>; 374298874a46SKonrad Dybcio dpu_intf2_out: endpoint { 374398874a46SKonrad Dybcio remote-endpoint = <&mdss_dsi1_in>; 374498874a46SKonrad Dybcio }; 374598874a46SKonrad Dybcio }; 374698874a46SKonrad Dybcio }; 374798874a46SKonrad Dybcio 374898874a46SKonrad Dybcio mdp_opp_table: opp-table { 374998874a46SKonrad Dybcio compatible = "operating-points-v2"; 375098874a46SKonrad Dybcio 375198874a46SKonrad Dybcio opp-171428571 { 375298874a46SKonrad Dybcio opp-hz = /bits/ 64 <171428571>; 375398874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 375498874a46SKonrad Dybcio }; 375598874a46SKonrad Dybcio 375698874a46SKonrad Dybcio opp-300000000 { 375798874a46SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 375898874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 375998874a46SKonrad Dybcio }; 376098874a46SKonrad Dybcio 376198874a46SKonrad Dybcio opp-345000000 { 376298874a46SKonrad Dybcio opp-hz = /bits/ 64 <345000000>; 376398874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 376498874a46SKonrad Dybcio }; 376598874a46SKonrad Dybcio 376698874a46SKonrad Dybcio opp-460000000 { 376798874a46SKonrad Dybcio opp-hz = /bits/ 64 <460000000>; 376898874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_nom>; 376998874a46SKonrad Dybcio }; 377098874a46SKonrad Dybcio }; 377198874a46SKonrad Dybcio }; 377298874a46SKonrad Dybcio 377398874a46SKonrad Dybcio mdss_dsi0: dsi@ae94000 { 3774b0b8b34aSDmitry Baryshkov compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 377598874a46SKonrad Dybcio reg = <0 0x0ae94000 0 0x400>; 377698874a46SKonrad Dybcio reg-names = "dsi_ctrl"; 377798874a46SKonrad Dybcio 377898874a46SKonrad Dybcio interrupt-parent = <&mdss>; 377998874a46SKonrad Dybcio interrupts = <4>; 378098874a46SKonrad Dybcio 378198874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 378298874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 378398874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 378498874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC0_CLK>, 378598874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 378698874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 378798874a46SKonrad Dybcio clock-names = "byte", 378898874a46SKonrad Dybcio "byte_intf", 378998874a46SKonrad Dybcio "pixel", 379098874a46SKonrad Dybcio "core", 379198874a46SKonrad Dybcio "iface", 379298874a46SKonrad Dybcio "bus"; 379398874a46SKonrad Dybcio 379498874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 379598874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 379698874a46SKonrad Dybcio assigned-clock-parents = <&mdss_dsi0_phy 0>, 379798874a46SKonrad Dybcio <&mdss_dsi0_phy 1>; 379898874a46SKonrad Dybcio 379998874a46SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 380098874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 380198874a46SKonrad Dybcio 380298874a46SKonrad Dybcio phys = <&mdss_dsi0_phy>; 380398874a46SKonrad Dybcio 380498874a46SKonrad Dybcio status = "disabled"; 380598874a46SKonrad Dybcio 380698874a46SKonrad Dybcio #address-cells = <1>; 380798874a46SKonrad Dybcio #size-cells = <0>; 380898874a46SKonrad Dybcio 380998874a46SKonrad Dybcio ports { 381098874a46SKonrad Dybcio #address-cells = <1>; 381198874a46SKonrad Dybcio #size-cells = <0>; 381298874a46SKonrad Dybcio 381398874a46SKonrad Dybcio port@0 { 381498874a46SKonrad Dybcio reg = <0>; 381598874a46SKonrad Dybcio mdss_dsi0_in: endpoint { 381698874a46SKonrad Dybcio remote-endpoint = <&dpu_intf1_out>; 381798874a46SKonrad Dybcio }; 381898874a46SKonrad Dybcio }; 381998874a46SKonrad Dybcio 382098874a46SKonrad Dybcio port@1 { 382198874a46SKonrad Dybcio reg = <1>; 382298874a46SKonrad Dybcio mdss_dsi0_out: endpoint { 382398874a46SKonrad Dybcio }; 382498874a46SKonrad Dybcio }; 382598874a46SKonrad Dybcio }; 382698874a46SKonrad Dybcio 382798874a46SKonrad Dybcio dsi_opp_table: opp-table { 382898874a46SKonrad Dybcio compatible = "operating-points-v2"; 382998874a46SKonrad Dybcio 383098874a46SKonrad Dybcio opp-187500000 { 383198874a46SKonrad Dybcio opp-hz = /bits/ 64 <187500000>; 383298874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_low_svs>; 383398874a46SKonrad Dybcio }; 383498874a46SKonrad Dybcio 383598874a46SKonrad Dybcio opp-300000000 { 383698874a46SKonrad Dybcio opp-hz = /bits/ 64 <300000000>; 383798874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs>; 383898874a46SKonrad Dybcio }; 383998874a46SKonrad Dybcio 384098874a46SKonrad Dybcio opp-358000000 { 384198874a46SKonrad Dybcio opp-hz = /bits/ 64 <358000000>; 384298874a46SKonrad Dybcio required-opps = <&rpmhpd_opp_svs_l1>; 384398874a46SKonrad Dybcio }; 384498874a46SKonrad Dybcio }; 384598874a46SKonrad Dybcio }; 384698874a46SKonrad Dybcio 384798874a46SKonrad Dybcio mdss_dsi0_phy: phy@ae94400 { 38483091e582SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm-8150"; 384998874a46SKonrad Dybcio reg = <0 0x0ae94400 0 0x200>, 385098874a46SKonrad Dybcio <0 0x0ae94600 0 0x280>, 385198874a46SKonrad Dybcio <0 0x0ae94900 0 0x260>; 385298874a46SKonrad Dybcio reg-names = "dsi_phy", 385398874a46SKonrad Dybcio "dsi_phy_lane", 385498874a46SKonrad Dybcio "dsi_pll"; 385598874a46SKonrad Dybcio 385698874a46SKonrad Dybcio #clock-cells = <1>; 385798874a46SKonrad Dybcio #phy-cells = <0>; 385898874a46SKonrad Dybcio 385998874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 386098874a46SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 386198874a46SKonrad Dybcio clock-names = "iface", "ref"; 386298874a46SKonrad Dybcio 386398874a46SKonrad Dybcio status = "disabled"; 386498874a46SKonrad Dybcio }; 386598874a46SKonrad Dybcio 386698874a46SKonrad Dybcio mdss_dsi1: dsi@ae96000 { 3867b0b8b34aSDmitry Baryshkov compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 386898874a46SKonrad Dybcio reg = <0 0x0ae96000 0 0x400>; 386998874a46SKonrad Dybcio reg-names = "dsi_ctrl"; 387098874a46SKonrad Dybcio 387198874a46SKonrad Dybcio interrupt-parent = <&mdss>; 387298874a46SKonrad Dybcio interrupts = <5>; 387398874a46SKonrad Dybcio 387498874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 387598874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 387698874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 387798874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_ESC1_CLK>, 387898874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_AHB_CLK>, 387998874a46SKonrad Dybcio <&gcc GCC_DISP_HF_AXI_CLK>; 388098874a46SKonrad Dybcio clock-names = "byte", 388198874a46SKonrad Dybcio "byte_intf", 388298874a46SKonrad Dybcio "pixel", 388398874a46SKonrad Dybcio "core", 388498874a46SKonrad Dybcio "iface", 388598874a46SKonrad Dybcio "bus"; 388698874a46SKonrad Dybcio 388798874a46SKonrad Dybcio assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 388898874a46SKonrad Dybcio <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 388998874a46SKonrad Dybcio assigned-clock-parents = <&mdss_dsi1_phy 0>, 389098874a46SKonrad Dybcio <&mdss_dsi1_phy 1>; 389198874a46SKonrad Dybcio 389298874a46SKonrad Dybcio operating-points-v2 = <&dsi_opp_table>; 389398874a46SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 389498874a46SKonrad Dybcio 389598874a46SKonrad Dybcio phys = <&mdss_dsi1_phy>; 389698874a46SKonrad Dybcio 389798874a46SKonrad Dybcio status = "disabled"; 389898874a46SKonrad Dybcio 389998874a46SKonrad Dybcio #address-cells = <1>; 390098874a46SKonrad Dybcio #size-cells = <0>; 390198874a46SKonrad Dybcio 390298874a46SKonrad Dybcio ports { 390398874a46SKonrad Dybcio #address-cells = <1>; 390498874a46SKonrad Dybcio #size-cells = <0>; 390598874a46SKonrad Dybcio 390698874a46SKonrad Dybcio port@0 { 390798874a46SKonrad Dybcio reg = <0>; 390898874a46SKonrad Dybcio mdss_dsi1_in: endpoint { 390998874a46SKonrad Dybcio remote-endpoint = <&dpu_intf2_out>; 391098874a46SKonrad Dybcio }; 391198874a46SKonrad Dybcio }; 391298874a46SKonrad Dybcio 391398874a46SKonrad Dybcio port@1 { 391498874a46SKonrad Dybcio reg = <1>; 391598874a46SKonrad Dybcio mdss_dsi1_out: endpoint { 391698874a46SKonrad Dybcio }; 391798874a46SKonrad Dybcio }; 391898874a46SKonrad Dybcio }; 391998874a46SKonrad Dybcio }; 392098874a46SKonrad Dybcio 392198874a46SKonrad Dybcio mdss_dsi1_phy: phy@ae96400 { 39223091e582SDmitry Baryshkov compatible = "qcom,dsi-phy-7nm-8150"; 392398874a46SKonrad Dybcio reg = <0 0x0ae96400 0 0x200>, 392498874a46SKonrad Dybcio <0 0x0ae96600 0 0x280>, 392598874a46SKonrad Dybcio <0 0x0ae96900 0 0x260>; 392698874a46SKonrad Dybcio reg-names = "dsi_phy", 392798874a46SKonrad Dybcio "dsi_phy_lane", 392898874a46SKonrad Dybcio "dsi_pll"; 392998874a46SKonrad Dybcio 393098874a46SKonrad Dybcio #clock-cells = <1>; 393198874a46SKonrad Dybcio #phy-cells = <0>; 393298874a46SKonrad Dybcio 393398874a46SKonrad Dybcio clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 393498874a46SKonrad Dybcio <&rpmhcc RPMH_CXO_CLK>; 393598874a46SKonrad Dybcio clock-names = "iface", "ref"; 393698874a46SKonrad Dybcio 393798874a46SKonrad Dybcio status = "disabled"; 393898874a46SKonrad Dybcio }; 393998874a46SKonrad Dybcio }; 394098874a46SKonrad Dybcio 39412ef3bb17SKonrad Dybcio dispcc: clock-controller@af00000 { 39422ef3bb17SKonrad Dybcio compatible = "qcom,sm8150-dispcc"; 39432ef3bb17SKonrad Dybcio reg = <0 0x0af00000 0 0x10000>; 39442ef3bb17SKonrad Dybcio clocks = <&rpmhcc RPMH_CXO_CLK>, 394598874a46SKonrad Dybcio <&mdss_dsi0_phy 0>, 394698874a46SKonrad Dybcio <&mdss_dsi0_phy 1>, 394798874a46SKonrad Dybcio <&mdss_dsi1_phy 0>, 394898874a46SKonrad Dybcio <&mdss_dsi1_phy 1>, 39492ef3bb17SKonrad Dybcio <0>, 39502ef3bb17SKonrad Dybcio <0>; 39512ef3bb17SKonrad Dybcio clock-names = "bi_tcxo", 39522ef3bb17SKonrad Dybcio "dsi0_phy_pll_out_byteclk", 39532ef3bb17SKonrad Dybcio "dsi0_phy_pll_out_dsiclk", 39542ef3bb17SKonrad Dybcio "dsi1_phy_pll_out_byteclk", 39552ef3bb17SKonrad Dybcio "dsi1_phy_pll_out_dsiclk", 39562ef3bb17SKonrad Dybcio "dp_phy_pll_link_clk", 39572ef3bb17SKonrad Dybcio "dp_phy_pll_vco_div_clk"; 39582ef3bb17SKonrad Dybcio power-domains = <&rpmhpd SM8150_MMCX>; 39592d1cd59aSDmitry Baryshkov required-opps = <&rpmhpd_opp_low_svs>; 39602ef3bb17SKonrad Dybcio #clock-cells = <1>; 39612ef3bb17SKonrad Dybcio #reset-cells = <1>; 39622ef3bb17SKonrad Dybcio #power-domain-cells = <1>; 39632ef3bb17SKonrad Dybcio }; 39642ef3bb17SKonrad Dybcio 3965397ad946SBhupesh Sharma pdc: interrupt-controller@b220000 { 3966397ad946SBhupesh Sharma compatible = "qcom,sm8150-pdc", "qcom,pdc"; 3967cf5716acSDmitry Baryshkov reg = <0 0x0b220000 0 0x30000>; 3968397ad946SBhupesh Sharma qcom,pdc-ranges = <0 480 94>, <94 609 31>, 3969397ad946SBhupesh Sharma <125 63 1>; 3970397ad946SBhupesh Sharma #interrupt-cells = <2>; 3971397ad946SBhupesh Sharma interrupt-parent = <&intc>; 3972397ad946SBhupesh Sharma interrupt-controller; 3973397ad946SBhupesh Sharma }; 3974397ad946SBhupesh Sharma 3975bb99820dSKrzysztof Kozlowski aoss_qmp: power-management@c300000 { 39766ba93ba9SKrzysztof Kozlowski compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 397747cb6a06SMaulik Shah reg = <0x0 0x0c300000 0x0 0x400>; 3978d8cf9372SVinod Koul interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3979d8cf9372SVinod Koul mboxes = <&apss_shared 0>; 3980d8cf9372SVinod Koul 3981d8cf9372SVinod Koul #clock-cells = <0>; 3982d8cf9372SVinod Koul }; 3983d8cf9372SVinod Koul 398447cb6a06SMaulik Shah sram@c3f0000 { 398547cb6a06SMaulik Shah compatible = "qcom,rpmh-stats"; 398647cb6a06SMaulik Shah reg = <0 0x0c3f0000 0 0x400>; 398747cb6a06SMaulik Shah }; 398847cb6a06SMaulik Shah 3989d2fa630cSAmit Kucheria tsens0: thermal-sensor@c263000 { 3990d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 3991d2fa630cSAmit Kucheria reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3992d2fa630cSAmit Kucheria <0 0x0c222000 0 0x1ff>; /* SROT */ 3993d2fa630cSAmit Kucheria #qcom,sensors = <16>; 3994d2fa630cSAmit Kucheria interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3995d2fa630cSAmit Kucheria <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3996d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 3997d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 3998d2fa630cSAmit Kucheria }; 3999d2fa630cSAmit Kucheria 4000d2fa630cSAmit Kucheria tsens1: thermal-sensor@c265000 { 4001d2fa630cSAmit Kucheria compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4002d2fa630cSAmit Kucheria reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4003d2fa630cSAmit Kucheria <0 0x0c223000 0 0x1ff>; /* SROT */ 4004d2fa630cSAmit Kucheria #qcom,sensors = <8>; 4005d2fa630cSAmit Kucheria interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4006d2fa630cSAmit Kucheria <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4007d2fa630cSAmit Kucheria interrupt-names = "uplow", "critical"; 4008d2fa630cSAmit Kucheria #thermal-sensor-cells = <1>; 4009d2fa630cSAmit Kucheria }; 4010d2fa630cSAmit Kucheria 4011e13c6d14SVinod Koul spmi_bus: spmi@c440000 { 4012e13c6d14SVinod Koul compatible = "qcom,spmi-pmic-arb"; 4013e13c6d14SVinod Koul reg = <0x0 0x0c440000 0x0 0x0001100>, 4014e13c6d14SVinod Koul <0x0 0x0c600000 0x0 0x2000000>, 4015e13c6d14SVinod Koul <0x0 0x0e600000 0x0 0x0100000>, 4016e13c6d14SVinod Koul <0x0 0x0e700000 0x0 0x00a0000>, 4017e13c6d14SVinod Koul <0x0 0x0c40a000 0x0 0x0026000>; 4018e13c6d14SVinod Koul reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4019e13c6d14SVinod Koul interrupt-names = "periph_irq"; 4020e13c6d14SVinod Koul interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4021e13c6d14SVinod Koul qcom,ee = <0>; 4022e13c6d14SVinod Koul qcom,channel = <0>; 4023e13c6d14SVinod Koul #address-cells = <2>; 4024e13c6d14SVinod Koul #size-cells = <0>; 4025e13c6d14SVinod Koul interrupt-controller; 4026e13c6d14SVinod Koul #interrupt-cells = <4>; 4027e13c6d14SVinod Koul }; 4028e13c6d14SVinod Koul 402948156232SJonathan Marek apps_smmu: iommu@15000000 { 403083254172SKrzysztof Kozlowski compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 403148156232SJonathan Marek reg = <0 0x15000000 0 0x100000>; 403248156232SJonathan Marek #iommu-cells = <2>; 403348156232SJonathan Marek #global-interrupts = <1>; 403448156232SJonathan Marek interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 403548156232SJonathan Marek <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 403648156232SJonathan Marek <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 403748156232SJonathan Marek <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 403848156232SJonathan Marek <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 403948156232SJonathan Marek <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 404048156232SJonathan Marek <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 404148156232SJonathan Marek <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 404248156232SJonathan Marek <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 404348156232SJonathan Marek <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 404448156232SJonathan Marek <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 404548156232SJonathan Marek <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 404648156232SJonathan Marek <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 404748156232SJonathan Marek <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 404848156232SJonathan Marek <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 404948156232SJonathan Marek <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 405048156232SJonathan Marek <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 405148156232SJonathan Marek <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 405248156232SJonathan Marek <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 405348156232SJonathan Marek <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 405448156232SJonathan Marek <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 405548156232SJonathan Marek <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 405648156232SJonathan Marek <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 405748156232SJonathan Marek <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 405848156232SJonathan Marek <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 405948156232SJonathan Marek <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 406048156232SJonathan Marek <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 406148156232SJonathan Marek <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 406248156232SJonathan Marek <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 406348156232SJonathan Marek <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 406448156232SJonathan Marek <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 406548156232SJonathan Marek <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 406648156232SJonathan Marek <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 406748156232SJonathan Marek <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 406848156232SJonathan Marek <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 406948156232SJonathan Marek <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 407048156232SJonathan Marek <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 407148156232SJonathan Marek <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 407248156232SJonathan Marek <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 407348156232SJonathan Marek <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 407448156232SJonathan Marek <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 407548156232SJonathan Marek <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 407648156232SJonathan Marek <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 407748156232SJonathan Marek <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 407848156232SJonathan Marek <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 407948156232SJonathan Marek <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 408048156232SJonathan Marek <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 408148156232SJonathan Marek <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 408248156232SJonathan Marek <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 408348156232SJonathan Marek <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 408448156232SJonathan Marek <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 408548156232SJonathan Marek <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 408648156232SJonathan Marek <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 408748156232SJonathan Marek <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 408848156232SJonathan Marek <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 408948156232SJonathan Marek <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 409048156232SJonathan Marek <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 409148156232SJonathan Marek <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 409248156232SJonathan Marek <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 409348156232SJonathan Marek <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 409448156232SJonathan Marek <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 409548156232SJonathan Marek <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 409648156232SJonathan Marek <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 409748156232SJonathan Marek <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 409848156232SJonathan Marek <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 409948156232SJonathan Marek <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 410048156232SJonathan Marek <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 410148156232SJonathan Marek <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 410248156232SJonathan Marek <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 410348156232SJonathan Marek <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 410448156232SJonathan Marek <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 410548156232SJonathan Marek <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 410648156232SJonathan Marek <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 410748156232SJonathan Marek <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 410848156232SJonathan Marek <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 410948156232SJonathan Marek <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 411048156232SJonathan Marek <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 411148156232SJonathan Marek <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 411248156232SJonathan Marek <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 411348156232SJonathan Marek <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 411448156232SJonathan Marek <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 411548156232SJonathan Marek }; 411648156232SJonathan Marek 411749076351SSibi Sankar remoteproc_adsp: remoteproc@17300000 { 411849076351SSibi Sankar compatible = "qcom,sm8150-adsp-pas"; 411949076351SSibi Sankar reg = <0x0 0x17300000 0x0 0x4040>; 412049076351SSibi Sankar 412149076351SSibi Sankar interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 412249076351SSibi Sankar <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 412349076351SSibi Sankar <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 412449076351SSibi Sankar <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 412549076351SSibi Sankar <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 412649076351SSibi Sankar interrupt-names = "wdog", "fatal", "ready", 412749076351SSibi Sankar "handover", "stop-ack"; 412849076351SSibi Sankar 412949076351SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>; 413049076351SSibi Sankar clock-names = "xo"; 413149076351SSibi Sankar 4132a94ed9f3SKonrad Dybcio power-domains = <&rpmhpd SM8150_CX>; 413349076351SSibi Sankar 413449076351SSibi Sankar memory-region = <&adsp_mem>; 413549076351SSibi Sankar 4136d9d327f6SSibi Sankar qcom,qmp = <&aoss_qmp>; 4137d9d327f6SSibi Sankar 413849076351SSibi Sankar qcom,smem-states = <&adsp_smp2p_out 0>; 413949076351SSibi Sankar qcom,smem-state-names = "stop"; 414049076351SSibi Sankar 414149076351SSibi Sankar status = "disabled"; 414249076351SSibi Sankar 414349076351SSibi Sankar glink-edge { 414449076351SSibi Sankar interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 414549076351SSibi Sankar label = "lpass"; 414649076351SSibi Sankar qcom,remote-pid = <2>; 414749076351SSibi Sankar mboxes = <&apss_shared 8>; 414881729330SBhupesh Sharma 414981729330SBhupesh Sharma fastrpc { 415081729330SBhupesh Sharma compatible = "qcom,fastrpc"; 415181729330SBhupesh Sharma qcom,glink-channels = "fastrpcglink-apps-dsp"; 415281729330SBhupesh Sharma label = "adsp"; 41538c8ce95bSJeya R qcom,non-secure-domain; 415481729330SBhupesh Sharma #address-cells = <1>; 415581729330SBhupesh Sharma #size-cells = <0>; 415681729330SBhupesh Sharma 415781729330SBhupesh Sharma compute-cb@3 { 415881729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 415981729330SBhupesh Sharma reg = <3>; 416081729330SBhupesh Sharma iommus = <&apps_smmu 0x1b23 0x0>; 416181729330SBhupesh Sharma }; 416281729330SBhupesh Sharma 416381729330SBhupesh Sharma compute-cb@4 { 416481729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 416581729330SBhupesh Sharma reg = <4>; 416681729330SBhupesh Sharma iommus = <&apps_smmu 0x1b24 0x0>; 416781729330SBhupesh Sharma }; 416881729330SBhupesh Sharma 416981729330SBhupesh Sharma compute-cb@5 { 417081729330SBhupesh Sharma compatible = "qcom,fastrpc-compute-cb"; 417181729330SBhupesh Sharma reg = <5>; 417281729330SBhupesh Sharma iommus = <&apps_smmu 0x1b25 0x0>; 417381729330SBhupesh Sharma }; 417481729330SBhupesh Sharma }; 417549076351SSibi Sankar }; 417649076351SSibi Sankar }; 417749076351SSibi Sankar 4178e13c6d14SVinod Koul intc: interrupt-controller@17a00000 { 4179e13c6d14SVinod Koul compatible = "arm,gic-v3"; 4180e13c6d14SVinod Koul interrupt-controller; 4181e13c6d14SVinod Koul #interrupt-cells = <3>; 4182e13c6d14SVinod Koul reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4183e13c6d14SVinod Koul <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4184e13c6d14SVinod Koul interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4185e13c6d14SVinod Koul }; 4186e13c6d14SVinod Koul 4187d8cf9372SVinod Koul apss_shared: mailbox@17c00000 { 41889b2e284aSKrzysztof Kozlowski compatible = "qcom,sm8150-apss-shared", 41899b2e284aSKrzysztof Kozlowski "qcom,sdm845-apss-shared"; 4190d8cf9372SVinod Koul reg = <0x0 0x17c00000 0x0 0x1000>; 4191d8cf9372SVinod Koul #mbox-cells = <1>; 4192d8cf9372SVinod Koul }; 4193d8cf9372SVinod Koul 4194fb2d8150SSai Prakash Ranjan watchdog@17c10000 { 4195fb2d8150SSai Prakash Ranjan compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4196fb2d8150SSai Prakash Ranjan reg = <0 0x17c10000 0 0x1000>; 4197fb2d8150SSai Prakash Ranjan clocks = <&sleep_clk>; 419870d0d1bfSDouglas Anderson interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4199fb2d8150SSai Prakash Ranjan }; 4200fb2d8150SSai Prakash Ranjan 4201e13c6d14SVinod Koul timer@17c20000 { 4202458ebdbbSDavid Heidelberg #address-cells = <1>; 4203458ebdbbSDavid Heidelberg #size-cells = <1>; 4204458ebdbbSDavid Heidelberg ranges = <0 0 0 0x20000000>; 4205e13c6d14SVinod Koul compatible = "arm,armv7-timer-mem"; 4206e13c6d14SVinod Koul reg = <0x0 0x17c20000 0x0 0x1000>; 4207e13c6d14SVinod Koul clock-frequency = <19200000>; 4208e13c6d14SVinod Koul 4209e13c6d14SVinod Koul frame@17c21000 { 4210e13c6d14SVinod Koul frame-number = <0>; 4211e13c6d14SVinod Koul interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4212e13c6d14SVinod Koul <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4213458ebdbbSDavid Heidelberg reg = <0x17c21000 0x1000>, 4214458ebdbbSDavid Heidelberg <0x17c22000 0x1000>; 4215e13c6d14SVinod Koul }; 4216e13c6d14SVinod Koul 4217e13c6d14SVinod Koul frame@17c23000 { 4218e13c6d14SVinod Koul frame-number = <1>; 4219e13c6d14SVinod Koul interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4220458ebdbbSDavid Heidelberg reg = <0x17c23000 0x1000>; 4221e13c6d14SVinod Koul status = "disabled"; 4222e13c6d14SVinod Koul }; 4223e13c6d14SVinod Koul 4224e13c6d14SVinod Koul frame@17c25000 { 4225e13c6d14SVinod Koul frame-number = <2>; 4226e13c6d14SVinod Koul interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4227458ebdbbSDavid Heidelberg reg = <0x17c25000 0x1000>; 4228e13c6d14SVinod Koul status = "disabled"; 4229e13c6d14SVinod Koul }; 4230e13c6d14SVinod Koul 4231e13c6d14SVinod Koul frame@17c27000 { 4232e13c6d14SVinod Koul frame-number = <3>; 4233e13c6d14SVinod Koul interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4234458ebdbbSDavid Heidelberg reg = <0x17c26000 0x1000>; 4235e13c6d14SVinod Koul status = "disabled"; 4236e13c6d14SVinod Koul }; 4237e13c6d14SVinod Koul 4238e13c6d14SVinod Koul frame@17c29000 { 4239e13c6d14SVinod Koul frame-number = <4>; 4240e13c6d14SVinod Koul interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4241458ebdbbSDavid Heidelberg reg = <0x17c29000 0x1000>; 4242e13c6d14SVinod Koul status = "disabled"; 4243e13c6d14SVinod Koul }; 4244e13c6d14SVinod Koul 4245e13c6d14SVinod Koul frame@17c2b000 { 4246e13c6d14SVinod Koul frame-number = <5>; 4247e13c6d14SVinod Koul interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4248458ebdbbSDavid Heidelberg reg = <0x17c2b000 0x1000>; 4249e13c6d14SVinod Koul status = "disabled"; 4250e13c6d14SVinod Koul }; 4251e13c6d14SVinod Koul 4252e13c6d14SVinod Koul frame@17c2d000 { 4253e13c6d14SVinod Koul frame-number = <6>; 4254e13c6d14SVinod Koul interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4255458ebdbbSDavid Heidelberg reg = <0x17c2d000 0x1000>; 4256e13c6d14SVinod Koul status = "disabled"; 4257e13c6d14SVinod Koul }; 4258e13c6d14SVinod Koul }; 4259d8cf9372SVinod Koul 4260d8cf9372SVinod Koul apps_rsc: rsc@18200000 { 4261d8cf9372SVinod Koul label = "apps_rsc"; 4262d8cf9372SVinod Koul compatible = "qcom,rpmh-rsc"; 4263d8cf9372SVinod Koul reg = <0x0 0x18200000 0x0 0x10000>, 4264d8cf9372SVinod Koul <0x0 0x18210000 0x0 0x10000>, 4265d8cf9372SVinod Koul <0x0 0x18220000 0x0 0x10000>; 4266d8cf9372SVinod Koul reg-names = "drv-0", "drv-1", "drv-2"; 4267d8cf9372SVinod Koul interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4268d8cf9372SVinod Koul <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4269d8cf9372SVinod Koul <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4270d8cf9372SVinod Koul qcom,tcs-offset = <0xd00>; 4271d8cf9372SVinod Koul qcom,drv-id = <2>; 4272d8cf9372SVinod Koul qcom,tcs-config = <ACTIVE_TCS 2>, 427317ac8af6SMaulik Shah <SLEEP_TCS 3>, 427417ac8af6SMaulik Shah <WAKE_TCS 3>, 427517ac8af6SMaulik Shah <CONTROL_TCS 1>; 42762ffa0ca4SMaulik Shah power-domains = <&CLUSTER_PD>; 4277d8cf9372SVinod Koul 4278d8cf9372SVinod Koul rpmhcc: clock-controller { 4279d8cf9372SVinod Koul compatible = "qcom,sm8150-rpmh-clk"; 4280d8cf9372SVinod Koul #clock-cells = <1>; 4281d8cf9372SVinod Koul clock-names = "xo"; 4282d8cf9372SVinod Koul clocks = <&xo_board>; 4283d8cf9372SVinod Koul }; 4284017e7856SSibi Sankar 4285017e7856SSibi Sankar rpmhpd: power-controller { 4286017e7856SSibi Sankar compatible = "qcom,sm8150-rpmhpd"; 4287017e7856SSibi Sankar #power-domain-cells = <1>; 4288017e7856SSibi Sankar operating-points-v2 = <&rpmhpd_opp_table>; 4289017e7856SSibi Sankar 4290017e7856SSibi Sankar rpmhpd_opp_table: opp-table { 4291017e7856SSibi Sankar compatible = "operating-points-v2"; 4292017e7856SSibi Sankar 4293017e7856SSibi Sankar rpmhpd_opp_ret: opp1 { 4294017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4295017e7856SSibi Sankar }; 4296017e7856SSibi Sankar 4297017e7856SSibi Sankar rpmhpd_opp_min_svs: opp2 { 4298017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4299017e7856SSibi Sankar }; 4300017e7856SSibi Sankar 4301017e7856SSibi Sankar rpmhpd_opp_low_svs: opp3 { 4302017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4303017e7856SSibi Sankar }; 4304017e7856SSibi Sankar 4305017e7856SSibi Sankar rpmhpd_opp_svs: opp4 { 4306017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4307017e7856SSibi Sankar }; 4308017e7856SSibi Sankar 4309017e7856SSibi Sankar rpmhpd_opp_svs_l1: opp5 { 4310017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4311017e7856SSibi Sankar }; 4312017e7856SSibi Sankar 4313017e7856SSibi Sankar rpmhpd_opp_svs_l2: opp6 { 4314017e7856SSibi Sankar opp-level = <224>; 4315017e7856SSibi Sankar }; 4316017e7856SSibi Sankar 4317017e7856SSibi Sankar rpmhpd_opp_nom: opp7 { 4318017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4319017e7856SSibi Sankar }; 4320017e7856SSibi Sankar 4321017e7856SSibi Sankar rpmhpd_opp_nom_l1: opp8 { 4322017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4323017e7856SSibi Sankar }; 4324017e7856SSibi Sankar 4325017e7856SSibi Sankar rpmhpd_opp_nom_l2: opp9 { 4326017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4327017e7856SSibi Sankar }; 4328017e7856SSibi Sankar 4329017e7856SSibi Sankar rpmhpd_opp_turbo: opp10 { 4330017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4331017e7856SSibi Sankar }; 4332017e7856SSibi Sankar 4333017e7856SSibi Sankar rpmhpd_opp_turbo_l1: opp11 { 4334017e7856SSibi Sankar opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4335017e7856SSibi Sankar }; 4336017e7856SSibi Sankar }; 4337017e7856SSibi Sankar }; 433871a2fc6eSJonathan Marek 4339fc0e7dd6SKrzysztof Kozlowski apps_bcm_voter: bcm-voter { 434071a2fc6eSJonathan Marek compatible = "qcom,bcm-voter"; 434171a2fc6eSJonathan Marek }; 4342d8cf9372SVinod Koul }; 4343fea8930bSSibi Sankar 4344a6d435c1SSibi Sankar osm_l3: interconnect@18321000 { 4345a0289a10SBjorn Andersson compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4346a6d435c1SSibi Sankar reg = <0 0x18321000 0 0x1400>; 4347a6d435c1SSibi Sankar 4348a6d435c1SSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4349a6d435c1SSibi Sankar clock-names = "xo", "alternate"; 4350a6d435c1SSibi Sankar 43518713c5e1SKrzysztof Kozlowski #interconnect-cells = <1>; 4352a6d435c1SSibi Sankar }; 4353a6d435c1SSibi Sankar 4354fea8930bSSibi Sankar cpufreq_hw: cpufreq@18323000 { 4355b2e1f870SKonrad Dybcio compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4356fea8930bSSibi Sankar reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4357fea8930bSSibi Sankar <0 0x18327800 0 0x1400>; 4358fea8930bSSibi Sankar reg-names = "freq-domain0", "freq-domain1", 4359fea8930bSSibi Sankar "freq-domain2"; 4360fea8930bSSibi Sankar 4361fea8930bSSibi Sankar clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4362fea8930bSSibi Sankar clock-names = "xo", "alternate"; 4363fea8930bSSibi Sankar 4364fea8930bSSibi Sankar #freq-domain-cells = <1>; 4365fc725894SManivannan Sadhasivam #clock-cells = <1>; 4366fea8930bSSibi Sankar }; 436705090bb9SJonathan Marek 43682ffcfe79SThara Gopinath lmh_cluster1: lmh@18350800 { 43692ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 43702ffcfe79SThara Gopinath reg = <0 0x18350800 0 0x400>; 43712ffcfe79SThara Gopinath interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 43722ffcfe79SThara Gopinath cpus = <&CPU4>; 43732ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 43742ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 43752ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 43762ffcfe79SThara Gopinath interrupt-controller; 43772ffcfe79SThara Gopinath #interrupt-cells = <1>; 43782ffcfe79SThara Gopinath }; 43792ffcfe79SThara Gopinath 43802ffcfe79SThara Gopinath lmh_cluster0: lmh@18358800 { 43812ffcfe79SThara Gopinath compatible = "qcom,sm8150-lmh"; 43822ffcfe79SThara Gopinath reg = <0 0x18358800 0 0x400>; 43832ffcfe79SThara Gopinath interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 43842ffcfe79SThara Gopinath cpus = <&CPU0>; 43852ffcfe79SThara Gopinath qcom,lmh-temp-arm-millicelsius = <60000>; 43862ffcfe79SThara Gopinath qcom,lmh-temp-low-millicelsius = <84500>; 43872ffcfe79SThara Gopinath qcom,lmh-temp-high-millicelsius = <85000>; 43882ffcfe79SThara Gopinath interrupt-controller; 43892ffcfe79SThara Gopinath #interrupt-cells = <1>; 43902ffcfe79SThara Gopinath }; 43912ffcfe79SThara Gopinath 439205090bb9SJonathan Marek wifi: wifi@18800000 { 439305090bb9SJonathan Marek compatible = "qcom,wcn3990-wifi"; 439405090bb9SJonathan Marek reg = <0 0x18800000 0 0x800000>; 439505090bb9SJonathan Marek reg-names = "membase"; 439605090bb9SJonathan Marek memory-region = <&wlan_mem>; 439705090bb9SJonathan Marek clock-names = "cxo_ref_clk_pin", "qdss"; 439805090bb9SJonathan Marek clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 439905090bb9SJonathan Marek interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 440005090bb9SJonathan Marek <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 440105090bb9SJonathan Marek <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 440205090bb9SJonathan Marek <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 440305090bb9SJonathan Marek <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 440405090bb9SJonathan Marek <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 440505090bb9SJonathan Marek <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 440605090bb9SJonathan Marek <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 440705090bb9SJonathan Marek <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 440805090bb9SJonathan Marek <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 440905090bb9SJonathan Marek <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 441005090bb9SJonathan Marek <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 441105090bb9SJonathan Marek iommus = <&apps_smmu 0x0640 0x1>; 441205090bb9SJonathan Marek status = "disabled"; 441305090bb9SJonathan Marek }; 4414e13c6d14SVinod Koul }; 4415e13c6d14SVinod Koul 4416e13c6d14SVinod Koul timer { 4417e13c6d14SVinod Koul compatible = "arm,armv8-timer"; 4418e13c6d14SVinod Koul interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4419e13c6d14SVinod Koul <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4420e13c6d14SVinod Koul <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4421e13c6d14SVinod Koul <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4422e13c6d14SVinod Koul }; 4423d2fa630cSAmit Kucheria 4424d2fa630cSAmit Kucheria thermal-zones { 4425d2fa630cSAmit Kucheria cpu0-thermal { 4426d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4427d2fa630cSAmit Kucheria polling-delay = <1000>; 4428d2fa630cSAmit Kucheria 4429d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 1>; 4430d2fa630cSAmit Kucheria 4431d2fa630cSAmit Kucheria trips { 4432d2fa630cSAmit Kucheria cpu0_alert0: trip-point0 { 4433d2fa630cSAmit Kucheria temperature = <90000>; 4434d2fa630cSAmit Kucheria hysteresis = <2000>; 4435d2fa630cSAmit Kucheria type = "passive"; 4436d2fa630cSAmit Kucheria }; 4437d2fa630cSAmit Kucheria 4438d2fa630cSAmit Kucheria cpu0_alert1: trip-point1 { 4439d2fa630cSAmit Kucheria temperature = <95000>; 4440d2fa630cSAmit Kucheria hysteresis = <2000>; 4441d2fa630cSAmit Kucheria type = "passive"; 4442d2fa630cSAmit Kucheria }; 4443d2fa630cSAmit Kucheria 44441364acc3SKrzysztof Kozlowski cpu0_crit: cpu-crit { 4445d2fa630cSAmit Kucheria temperature = <110000>; 4446d2fa630cSAmit Kucheria hysteresis = <1000>; 4447d2fa630cSAmit Kucheria type = "critical"; 4448d2fa630cSAmit Kucheria }; 4449d2fa630cSAmit Kucheria }; 4450d2fa630cSAmit Kucheria 4451d2fa630cSAmit Kucheria cooling-maps { 4452d2fa630cSAmit Kucheria map0 { 4453d2fa630cSAmit Kucheria trip = <&cpu0_alert0>; 4454d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4455d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4456d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4457d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4458d2fa630cSAmit Kucheria }; 4459d2fa630cSAmit Kucheria map1 { 4460d2fa630cSAmit Kucheria trip = <&cpu0_alert1>; 4461d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4462d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4463d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4464d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4465d2fa630cSAmit Kucheria }; 4466d2fa630cSAmit Kucheria }; 4467d2fa630cSAmit Kucheria }; 4468d2fa630cSAmit Kucheria 4469d2fa630cSAmit Kucheria cpu1-thermal { 4470d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4471d2fa630cSAmit Kucheria polling-delay = <1000>; 4472d2fa630cSAmit Kucheria 4473d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 2>; 4474d2fa630cSAmit Kucheria 4475d2fa630cSAmit Kucheria trips { 4476d2fa630cSAmit Kucheria cpu1_alert0: trip-point0 { 4477d2fa630cSAmit Kucheria temperature = <90000>; 4478d2fa630cSAmit Kucheria hysteresis = <2000>; 4479d2fa630cSAmit Kucheria type = "passive"; 4480d2fa630cSAmit Kucheria }; 4481d2fa630cSAmit Kucheria 4482d2fa630cSAmit Kucheria cpu1_alert1: trip-point1 { 4483d2fa630cSAmit Kucheria temperature = <95000>; 4484d2fa630cSAmit Kucheria hysteresis = <2000>; 4485d2fa630cSAmit Kucheria type = "passive"; 4486d2fa630cSAmit Kucheria }; 4487d2fa630cSAmit Kucheria 44881364acc3SKrzysztof Kozlowski cpu1_crit: cpu-crit { 4489d2fa630cSAmit Kucheria temperature = <110000>; 4490d2fa630cSAmit Kucheria hysteresis = <1000>; 4491d2fa630cSAmit Kucheria type = "critical"; 4492d2fa630cSAmit Kucheria }; 4493d2fa630cSAmit Kucheria }; 4494d2fa630cSAmit Kucheria 4495d2fa630cSAmit Kucheria cooling-maps { 4496d2fa630cSAmit Kucheria map0 { 4497d2fa630cSAmit Kucheria trip = <&cpu1_alert0>; 4498d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4499d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4500d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4501d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4502d2fa630cSAmit Kucheria }; 4503d2fa630cSAmit Kucheria map1 { 4504d2fa630cSAmit Kucheria trip = <&cpu1_alert1>; 4505d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4506d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4507d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4508d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4509d2fa630cSAmit Kucheria }; 4510d2fa630cSAmit Kucheria }; 4511d2fa630cSAmit Kucheria }; 4512d2fa630cSAmit Kucheria 4513d2fa630cSAmit Kucheria cpu2-thermal { 4514d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4515d2fa630cSAmit Kucheria polling-delay = <1000>; 4516d2fa630cSAmit Kucheria 4517d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 3>; 4518d2fa630cSAmit Kucheria 4519d2fa630cSAmit Kucheria trips { 4520d2fa630cSAmit Kucheria cpu2_alert0: trip-point0 { 4521d2fa630cSAmit Kucheria temperature = <90000>; 4522d2fa630cSAmit Kucheria hysteresis = <2000>; 4523d2fa630cSAmit Kucheria type = "passive"; 4524d2fa630cSAmit Kucheria }; 4525d2fa630cSAmit Kucheria 4526d2fa630cSAmit Kucheria cpu2_alert1: trip-point1 { 4527d2fa630cSAmit Kucheria temperature = <95000>; 4528d2fa630cSAmit Kucheria hysteresis = <2000>; 4529d2fa630cSAmit Kucheria type = "passive"; 4530d2fa630cSAmit Kucheria }; 4531d2fa630cSAmit Kucheria 45321364acc3SKrzysztof Kozlowski cpu2_crit: cpu-crit { 4533d2fa630cSAmit Kucheria temperature = <110000>; 4534d2fa630cSAmit Kucheria hysteresis = <1000>; 4535d2fa630cSAmit Kucheria type = "critical"; 4536d2fa630cSAmit Kucheria }; 4537d2fa630cSAmit Kucheria }; 4538d2fa630cSAmit Kucheria 4539d2fa630cSAmit Kucheria cooling-maps { 4540d2fa630cSAmit Kucheria map0 { 4541d2fa630cSAmit Kucheria trip = <&cpu2_alert0>; 4542d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4543d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4544d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4545d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4546d2fa630cSAmit Kucheria }; 4547d2fa630cSAmit Kucheria map1 { 4548d2fa630cSAmit Kucheria trip = <&cpu2_alert1>; 4549d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4550d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4551d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4552d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4553d2fa630cSAmit Kucheria }; 4554d2fa630cSAmit Kucheria }; 4555d2fa630cSAmit Kucheria }; 4556d2fa630cSAmit Kucheria 4557d2fa630cSAmit Kucheria cpu3-thermal { 4558d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4559d2fa630cSAmit Kucheria polling-delay = <1000>; 4560d2fa630cSAmit Kucheria 4561d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 4>; 4562d2fa630cSAmit Kucheria 4563d2fa630cSAmit Kucheria trips { 4564d2fa630cSAmit Kucheria cpu3_alert0: trip-point0 { 4565d2fa630cSAmit Kucheria temperature = <90000>; 4566d2fa630cSAmit Kucheria hysteresis = <2000>; 4567d2fa630cSAmit Kucheria type = "passive"; 4568d2fa630cSAmit Kucheria }; 4569d2fa630cSAmit Kucheria 4570d2fa630cSAmit Kucheria cpu3_alert1: trip-point1 { 4571d2fa630cSAmit Kucheria temperature = <95000>; 4572d2fa630cSAmit Kucheria hysteresis = <2000>; 4573d2fa630cSAmit Kucheria type = "passive"; 4574d2fa630cSAmit Kucheria }; 4575d2fa630cSAmit Kucheria 45761364acc3SKrzysztof Kozlowski cpu3_crit: cpu-crit { 4577d2fa630cSAmit Kucheria temperature = <110000>; 4578d2fa630cSAmit Kucheria hysteresis = <1000>; 4579d2fa630cSAmit Kucheria type = "critical"; 4580d2fa630cSAmit Kucheria }; 4581d2fa630cSAmit Kucheria }; 4582d2fa630cSAmit Kucheria 4583d2fa630cSAmit Kucheria cooling-maps { 4584d2fa630cSAmit Kucheria map0 { 4585d2fa630cSAmit Kucheria trip = <&cpu3_alert0>; 4586d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4587d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4588d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4589d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4590d2fa630cSAmit Kucheria }; 4591d2fa630cSAmit Kucheria map1 { 4592d2fa630cSAmit Kucheria trip = <&cpu3_alert1>; 4593d2fa630cSAmit Kucheria cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4594d2fa630cSAmit Kucheria <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4595d2fa630cSAmit Kucheria <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4596d2fa630cSAmit Kucheria <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4597d2fa630cSAmit Kucheria }; 4598d2fa630cSAmit Kucheria }; 4599d2fa630cSAmit Kucheria }; 4600d2fa630cSAmit Kucheria 4601d2fa630cSAmit Kucheria cpu4-top-thermal { 4602d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4603d2fa630cSAmit Kucheria polling-delay = <1000>; 4604d2fa630cSAmit Kucheria 4605d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 7>; 4606d2fa630cSAmit Kucheria 4607d2fa630cSAmit Kucheria trips { 4608d2fa630cSAmit Kucheria cpu4_top_alert0: trip-point0 { 4609d2fa630cSAmit Kucheria temperature = <90000>; 4610d2fa630cSAmit Kucheria hysteresis = <2000>; 4611d2fa630cSAmit Kucheria type = "passive"; 4612d2fa630cSAmit Kucheria }; 4613d2fa630cSAmit Kucheria 4614d2fa630cSAmit Kucheria cpu4_top_alert1: trip-point1 { 4615d2fa630cSAmit Kucheria temperature = <95000>; 4616d2fa630cSAmit Kucheria hysteresis = <2000>; 4617d2fa630cSAmit Kucheria type = "passive"; 4618d2fa630cSAmit Kucheria }; 4619d2fa630cSAmit Kucheria 46201364acc3SKrzysztof Kozlowski cpu4_top_crit: cpu-crit { 4621d2fa630cSAmit Kucheria temperature = <110000>; 4622d2fa630cSAmit Kucheria hysteresis = <1000>; 4623d2fa630cSAmit Kucheria type = "critical"; 4624d2fa630cSAmit Kucheria }; 4625d2fa630cSAmit Kucheria }; 4626d2fa630cSAmit Kucheria 4627d2fa630cSAmit Kucheria cooling-maps { 4628d2fa630cSAmit Kucheria map0 { 4629d2fa630cSAmit Kucheria trip = <&cpu4_top_alert0>; 4630d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4631d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4632d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4633d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4634d2fa630cSAmit Kucheria }; 4635d2fa630cSAmit Kucheria map1 { 4636d2fa630cSAmit Kucheria trip = <&cpu4_top_alert1>; 4637d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4638d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4639d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4640d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4641d2fa630cSAmit Kucheria }; 4642d2fa630cSAmit Kucheria }; 4643d2fa630cSAmit Kucheria }; 4644d2fa630cSAmit Kucheria 4645d2fa630cSAmit Kucheria cpu5-top-thermal { 4646d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4647d2fa630cSAmit Kucheria polling-delay = <1000>; 4648d2fa630cSAmit Kucheria 4649d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 8>; 4650d2fa630cSAmit Kucheria 4651d2fa630cSAmit Kucheria trips { 4652d2fa630cSAmit Kucheria cpu5_top_alert0: trip-point0 { 4653d2fa630cSAmit Kucheria temperature = <90000>; 4654d2fa630cSAmit Kucheria hysteresis = <2000>; 4655d2fa630cSAmit Kucheria type = "passive"; 4656d2fa630cSAmit Kucheria }; 4657d2fa630cSAmit Kucheria 4658d2fa630cSAmit Kucheria cpu5_top_alert1: trip-point1 { 4659d2fa630cSAmit Kucheria temperature = <95000>; 4660d2fa630cSAmit Kucheria hysteresis = <2000>; 4661d2fa630cSAmit Kucheria type = "passive"; 4662d2fa630cSAmit Kucheria }; 4663d2fa630cSAmit Kucheria 46641364acc3SKrzysztof Kozlowski cpu5_top_crit: cpu-crit { 4665d2fa630cSAmit Kucheria temperature = <110000>; 4666d2fa630cSAmit Kucheria hysteresis = <1000>; 4667d2fa630cSAmit Kucheria type = "critical"; 4668d2fa630cSAmit Kucheria }; 4669d2fa630cSAmit Kucheria }; 4670d2fa630cSAmit Kucheria 4671d2fa630cSAmit Kucheria cooling-maps { 4672d2fa630cSAmit Kucheria map0 { 4673d2fa630cSAmit Kucheria trip = <&cpu5_top_alert0>; 4674d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4676d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4677d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4678d2fa630cSAmit Kucheria }; 4679d2fa630cSAmit Kucheria map1 { 4680d2fa630cSAmit Kucheria trip = <&cpu5_top_alert1>; 4681d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4682d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4683d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4684d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4685d2fa630cSAmit Kucheria }; 4686d2fa630cSAmit Kucheria }; 4687d2fa630cSAmit Kucheria }; 4688d2fa630cSAmit Kucheria 4689d2fa630cSAmit Kucheria cpu6-top-thermal { 4690d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4691d2fa630cSAmit Kucheria polling-delay = <1000>; 4692d2fa630cSAmit Kucheria 4693d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 9>; 4694d2fa630cSAmit Kucheria 4695d2fa630cSAmit Kucheria trips { 4696d2fa630cSAmit Kucheria cpu6_top_alert0: trip-point0 { 4697d2fa630cSAmit Kucheria temperature = <90000>; 4698d2fa630cSAmit Kucheria hysteresis = <2000>; 4699d2fa630cSAmit Kucheria type = "passive"; 4700d2fa630cSAmit Kucheria }; 4701d2fa630cSAmit Kucheria 4702d2fa630cSAmit Kucheria cpu6_top_alert1: trip-point1 { 4703d2fa630cSAmit Kucheria temperature = <95000>; 4704d2fa630cSAmit Kucheria hysteresis = <2000>; 4705d2fa630cSAmit Kucheria type = "passive"; 4706d2fa630cSAmit Kucheria }; 4707d2fa630cSAmit Kucheria 47081364acc3SKrzysztof Kozlowski cpu6_top_crit: cpu-crit { 4709d2fa630cSAmit Kucheria temperature = <110000>; 4710d2fa630cSAmit Kucheria hysteresis = <1000>; 4711d2fa630cSAmit Kucheria type = "critical"; 4712d2fa630cSAmit Kucheria }; 4713d2fa630cSAmit Kucheria }; 4714d2fa630cSAmit Kucheria 4715d2fa630cSAmit Kucheria cooling-maps { 4716d2fa630cSAmit Kucheria map0 { 4717d2fa630cSAmit Kucheria trip = <&cpu6_top_alert0>; 4718d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4719d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4720d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4721d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4722d2fa630cSAmit Kucheria }; 4723d2fa630cSAmit Kucheria map1 { 4724d2fa630cSAmit Kucheria trip = <&cpu6_top_alert1>; 4725d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4726d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4727d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4728d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4729d2fa630cSAmit Kucheria }; 4730d2fa630cSAmit Kucheria }; 4731d2fa630cSAmit Kucheria }; 4732d2fa630cSAmit Kucheria 4733d2fa630cSAmit Kucheria cpu7-top-thermal { 4734d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4735d2fa630cSAmit Kucheria polling-delay = <1000>; 4736d2fa630cSAmit Kucheria 4737d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 10>; 4738d2fa630cSAmit Kucheria 4739d2fa630cSAmit Kucheria trips { 4740d2fa630cSAmit Kucheria cpu7_top_alert0: trip-point0 { 4741d2fa630cSAmit Kucheria temperature = <90000>; 4742d2fa630cSAmit Kucheria hysteresis = <2000>; 4743d2fa630cSAmit Kucheria type = "passive"; 4744d2fa630cSAmit Kucheria }; 4745d2fa630cSAmit Kucheria 4746d2fa630cSAmit Kucheria cpu7_top_alert1: trip-point1 { 4747d2fa630cSAmit Kucheria temperature = <95000>; 4748d2fa630cSAmit Kucheria hysteresis = <2000>; 4749d2fa630cSAmit Kucheria type = "passive"; 4750d2fa630cSAmit Kucheria }; 4751d2fa630cSAmit Kucheria 47521364acc3SKrzysztof Kozlowski cpu7_top_crit: cpu-crit { 4753d2fa630cSAmit Kucheria temperature = <110000>; 4754d2fa630cSAmit Kucheria hysteresis = <1000>; 4755d2fa630cSAmit Kucheria type = "critical"; 4756d2fa630cSAmit Kucheria }; 4757d2fa630cSAmit Kucheria }; 4758d2fa630cSAmit Kucheria 4759d2fa630cSAmit Kucheria cooling-maps { 4760d2fa630cSAmit Kucheria map0 { 4761d2fa630cSAmit Kucheria trip = <&cpu7_top_alert0>; 4762d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4763d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4764d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4766d2fa630cSAmit Kucheria }; 4767d2fa630cSAmit Kucheria map1 { 4768d2fa630cSAmit Kucheria trip = <&cpu7_top_alert1>; 4769d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4770d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4771d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4772d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4773d2fa630cSAmit Kucheria }; 4774d2fa630cSAmit Kucheria }; 4775d2fa630cSAmit Kucheria }; 4776d2fa630cSAmit Kucheria 4777d2fa630cSAmit Kucheria cpu4-bottom-thermal { 4778d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4779d2fa630cSAmit Kucheria polling-delay = <1000>; 4780d2fa630cSAmit Kucheria 4781d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 11>; 4782d2fa630cSAmit Kucheria 4783d2fa630cSAmit Kucheria trips { 4784d2fa630cSAmit Kucheria cpu4_bottom_alert0: trip-point0 { 4785d2fa630cSAmit Kucheria temperature = <90000>; 4786d2fa630cSAmit Kucheria hysteresis = <2000>; 4787d2fa630cSAmit Kucheria type = "passive"; 4788d2fa630cSAmit Kucheria }; 4789d2fa630cSAmit Kucheria 4790d2fa630cSAmit Kucheria cpu4_bottom_alert1: trip-point1 { 4791d2fa630cSAmit Kucheria temperature = <95000>; 4792d2fa630cSAmit Kucheria hysteresis = <2000>; 4793d2fa630cSAmit Kucheria type = "passive"; 4794d2fa630cSAmit Kucheria }; 4795d2fa630cSAmit Kucheria 47961364acc3SKrzysztof Kozlowski cpu4_bottom_crit: cpu-crit { 4797d2fa630cSAmit Kucheria temperature = <110000>; 4798d2fa630cSAmit Kucheria hysteresis = <1000>; 4799d2fa630cSAmit Kucheria type = "critical"; 4800d2fa630cSAmit Kucheria }; 4801d2fa630cSAmit Kucheria }; 4802d2fa630cSAmit Kucheria 4803d2fa630cSAmit Kucheria cooling-maps { 4804d2fa630cSAmit Kucheria map0 { 4805d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert0>; 4806d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4807d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4808d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4809d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4810d2fa630cSAmit Kucheria }; 4811d2fa630cSAmit Kucheria map1 { 4812d2fa630cSAmit Kucheria trip = <&cpu4_bottom_alert1>; 4813d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4814d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4816d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4817d2fa630cSAmit Kucheria }; 4818d2fa630cSAmit Kucheria }; 4819d2fa630cSAmit Kucheria }; 4820d2fa630cSAmit Kucheria 4821d2fa630cSAmit Kucheria cpu5-bottom-thermal { 4822d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4823d2fa630cSAmit Kucheria polling-delay = <1000>; 4824d2fa630cSAmit Kucheria 4825d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 12>; 4826d2fa630cSAmit Kucheria 4827d2fa630cSAmit Kucheria trips { 4828d2fa630cSAmit Kucheria cpu5_bottom_alert0: trip-point0 { 4829d2fa630cSAmit Kucheria temperature = <90000>; 4830d2fa630cSAmit Kucheria hysteresis = <2000>; 4831d2fa630cSAmit Kucheria type = "passive"; 4832d2fa630cSAmit Kucheria }; 4833d2fa630cSAmit Kucheria 4834d2fa630cSAmit Kucheria cpu5_bottom_alert1: trip-point1 { 4835d2fa630cSAmit Kucheria temperature = <95000>; 4836d2fa630cSAmit Kucheria hysteresis = <2000>; 4837d2fa630cSAmit Kucheria type = "passive"; 4838d2fa630cSAmit Kucheria }; 4839d2fa630cSAmit Kucheria 48401364acc3SKrzysztof Kozlowski cpu5_bottom_crit: cpu-crit { 4841d2fa630cSAmit Kucheria temperature = <110000>; 4842d2fa630cSAmit Kucheria hysteresis = <1000>; 4843d2fa630cSAmit Kucheria type = "critical"; 4844d2fa630cSAmit Kucheria }; 4845d2fa630cSAmit Kucheria }; 4846d2fa630cSAmit Kucheria 4847d2fa630cSAmit Kucheria cooling-maps { 4848d2fa630cSAmit Kucheria map0 { 4849d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert0>; 4850d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4851d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4852d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4853d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4854d2fa630cSAmit Kucheria }; 4855d2fa630cSAmit Kucheria map1 { 4856d2fa630cSAmit Kucheria trip = <&cpu5_bottom_alert1>; 4857d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4858d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4859d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4860d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4861d2fa630cSAmit Kucheria }; 4862d2fa630cSAmit Kucheria }; 4863d2fa630cSAmit Kucheria }; 4864d2fa630cSAmit Kucheria 4865d2fa630cSAmit Kucheria cpu6-bottom-thermal { 4866d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4867d2fa630cSAmit Kucheria polling-delay = <1000>; 4868d2fa630cSAmit Kucheria 4869d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 13>; 4870d2fa630cSAmit Kucheria 4871d2fa630cSAmit Kucheria trips { 4872d2fa630cSAmit Kucheria cpu6_bottom_alert0: trip-point0 { 4873d2fa630cSAmit Kucheria temperature = <90000>; 4874d2fa630cSAmit Kucheria hysteresis = <2000>; 4875d2fa630cSAmit Kucheria type = "passive"; 4876d2fa630cSAmit Kucheria }; 4877d2fa630cSAmit Kucheria 4878d2fa630cSAmit Kucheria cpu6_bottom_alert1: trip-point1 { 4879d2fa630cSAmit Kucheria temperature = <95000>; 4880d2fa630cSAmit Kucheria hysteresis = <2000>; 4881d2fa630cSAmit Kucheria type = "passive"; 4882d2fa630cSAmit Kucheria }; 4883d2fa630cSAmit Kucheria 48841364acc3SKrzysztof Kozlowski cpu6_bottom_crit: cpu-crit { 4885d2fa630cSAmit Kucheria temperature = <110000>; 4886d2fa630cSAmit Kucheria hysteresis = <1000>; 4887d2fa630cSAmit Kucheria type = "critical"; 4888d2fa630cSAmit Kucheria }; 4889d2fa630cSAmit Kucheria }; 4890d2fa630cSAmit Kucheria 4891d2fa630cSAmit Kucheria cooling-maps { 4892d2fa630cSAmit Kucheria map0 { 4893d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert0>; 4894d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4895d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4896d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4897d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4898d2fa630cSAmit Kucheria }; 4899d2fa630cSAmit Kucheria map1 { 4900d2fa630cSAmit Kucheria trip = <&cpu6_bottom_alert1>; 4901d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4902d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4903d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4904d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4905d2fa630cSAmit Kucheria }; 4906d2fa630cSAmit Kucheria }; 4907d2fa630cSAmit Kucheria }; 4908d2fa630cSAmit Kucheria 4909d2fa630cSAmit Kucheria cpu7-bottom-thermal { 4910d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4911d2fa630cSAmit Kucheria polling-delay = <1000>; 4912d2fa630cSAmit Kucheria 4913d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 14>; 4914d2fa630cSAmit Kucheria 4915d2fa630cSAmit Kucheria trips { 4916d2fa630cSAmit Kucheria cpu7_bottom_alert0: trip-point0 { 4917d2fa630cSAmit Kucheria temperature = <90000>; 4918d2fa630cSAmit Kucheria hysteresis = <2000>; 4919d2fa630cSAmit Kucheria type = "passive"; 4920d2fa630cSAmit Kucheria }; 4921d2fa630cSAmit Kucheria 4922d2fa630cSAmit Kucheria cpu7_bottom_alert1: trip-point1 { 4923d2fa630cSAmit Kucheria temperature = <95000>; 4924d2fa630cSAmit Kucheria hysteresis = <2000>; 4925d2fa630cSAmit Kucheria type = "passive"; 4926d2fa630cSAmit Kucheria }; 4927d2fa630cSAmit Kucheria 49281364acc3SKrzysztof Kozlowski cpu7_bottom_crit: cpu-crit { 4929d2fa630cSAmit Kucheria temperature = <110000>; 4930d2fa630cSAmit Kucheria hysteresis = <1000>; 4931d2fa630cSAmit Kucheria type = "critical"; 4932d2fa630cSAmit Kucheria }; 4933d2fa630cSAmit Kucheria }; 4934d2fa630cSAmit Kucheria 4935d2fa630cSAmit Kucheria cooling-maps { 4936d2fa630cSAmit Kucheria map0 { 4937d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert0>; 4938d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4939d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4940d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4941d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4942d2fa630cSAmit Kucheria }; 4943d2fa630cSAmit Kucheria map1 { 4944d2fa630cSAmit Kucheria trip = <&cpu7_bottom_alert1>; 4945d2fa630cSAmit Kucheria cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4946d2fa630cSAmit Kucheria <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4947d2fa630cSAmit Kucheria <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4948d2fa630cSAmit Kucheria <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4949d2fa630cSAmit Kucheria }; 4950d2fa630cSAmit Kucheria }; 4951d2fa630cSAmit Kucheria }; 4952d2fa630cSAmit Kucheria 4953d2fa630cSAmit Kucheria aoss0-thermal { 4954d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4955d2fa630cSAmit Kucheria polling-delay = <1000>; 4956d2fa630cSAmit Kucheria 4957d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 0>; 4958d2fa630cSAmit Kucheria 4959d2fa630cSAmit Kucheria trips { 4960d2fa630cSAmit Kucheria aoss0_alert0: trip-point0 { 4961d2fa630cSAmit Kucheria temperature = <90000>; 4962d2fa630cSAmit Kucheria hysteresis = <2000>; 4963d2fa630cSAmit Kucheria type = "hot"; 4964d2fa630cSAmit Kucheria }; 4965d2fa630cSAmit Kucheria }; 4966d2fa630cSAmit Kucheria }; 4967d2fa630cSAmit Kucheria 4968d2fa630cSAmit Kucheria cluster0-thermal { 4969d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4970d2fa630cSAmit Kucheria polling-delay = <1000>; 4971d2fa630cSAmit Kucheria 4972d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 5>; 4973d2fa630cSAmit Kucheria 4974d2fa630cSAmit Kucheria trips { 4975d2fa630cSAmit Kucheria cluster0_alert0: trip-point0 { 4976d2fa630cSAmit Kucheria temperature = <90000>; 4977d2fa630cSAmit Kucheria hysteresis = <2000>; 4978d2fa630cSAmit Kucheria type = "hot"; 4979d2fa630cSAmit Kucheria }; 4980d2fa630cSAmit Kucheria cluster0_crit: cluster0_crit { 4981d2fa630cSAmit Kucheria temperature = <110000>; 4982d2fa630cSAmit Kucheria hysteresis = <2000>; 4983d2fa630cSAmit Kucheria type = "critical"; 4984d2fa630cSAmit Kucheria }; 4985d2fa630cSAmit Kucheria }; 4986d2fa630cSAmit Kucheria }; 4987d2fa630cSAmit Kucheria 4988d2fa630cSAmit Kucheria cluster1-thermal { 4989d2fa630cSAmit Kucheria polling-delay-passive = <250>; 4990d2fa630cSAmit Kucheria polling-delay = <1000>; 4991d2fa630cSAmit Kucheria 4992d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 6>; 4993d2fa630cSAmit Kucheria 4994d2fa630cSAmit Kucheria trips { 4995d2fa630cSAmit Kucheria cluster1_alert0: trip-point0 { 4996d2fa630cSAmit Kucheria temperature = <90000>; 4997d2fa630cSAmit Kucheria hysteresis = <2000>; 4998d2fa630cSAmit Kucheria type = "hot"; 4999d2fa630cSAmit Kucheria }; 5000d2fa630cSAmit Kucheria cluster1_crit: cluster1_crit { 5001d2fa630cSAmit Kucheria temperature = <110000>; 5002d2fa630cSAmit Kucheria hysteresis = <2000>; 5003d2fa630cSAmit Kucheria type = "critical"; 5004d2fa630cSAmit Kucheria }; 5005d2fa630cSAmit Kucheria }; 5006d2fa630cSAmit Kucheria }; 5007d2fa630cSAmit Kucheria 50087be1c395SDavid Heidelberg gpu-top-thermal { 5009d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5010d2fa630cSAmit Kucheria polling-delay = <1000>; 5011d2fa630cSAmit Kucheria 5012d2fa630cSAmit Kucheria thermal-sensors = <&tsens0 15>; 5013d2fa630cSAmit Kucheria 5014d2fa630cSAmit Kucheria trips { 5015d2fa630cSAmit Kucheria gpu1_alert0: trip-point0 { 5016d2fa630cSAmit Kucheria temperature = <90000>; 5017d2fa630cSAmit Kucheria hysteresis = <2000>; 5018d2fa630cSAmit Kucheria type = "hot"; 5019d2fa630cSAmit Kucheria }; 5020d2fa630cSAmit Kucheria }; 5021d2fa630cSAmit Kucheria }; 5022d2fa630cSAmit Kucheria 5023d2fa630cSAmit Kucheria aoss1-thermal { 5024d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5025d2fa630cSAmit Kucheria polling-delay = <1000>; 5026d2fa630cSAmit Kucheria 5027d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 0>; 5028d2fa630cSAmit Kucheria 5029d2fa630cSAmit Kucheria trips { 5030d2fa630cSAmit Kucheria aoss1_alert0: trip-point0 { 5031d2fa630cSAmit Kucheria temperature = <90000>; 5032d2fa630cSAmit Kucheria hysteresis = <2000>; 5033d2fa630cSAmit Kucheria type = "hot"; 5034d2fa630cSAmit Kucheria }; 5035d2fa630cSAmit Kucheria }; 5036d2fa630cSAmit Kucheria }; 5037d2fa630cSAmit Kucheria 5038d2fa630cSAmit Kucheria wlan-thermal { 5039d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5040d2fa630cSAmit Kucheria polling-delay = <1000>; 5041d2fa630cSAmit Kucheria 5042d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 1>; 5043d2fa630cSAmit Kucheria 5044d2fa630cSAmit Kucheria trips { 5045d2fa630cSAmit Kucheria wlan_alert0: trip-point0 { 5046d2fa630cSAmit Kucheria temperature = <90000>; 5047d2fa630cSAmit Kucheria hysteresis = <2000>; 5048d2fa630cSAmit Kucheria type = "hot"; 5049d2fa630cSAmit Kucheria }; 5050d2fa630cSAmit Kucheria }; 5051d2fa630cSAmit Kucheria }; 5052d2fa630cSAmit Kucheria 5053d2fa630cSAmit Kucheria video-thermal { 5054d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5055d2fa630cSAmit Kucheria polling-delay = <1000>; 5056d2fa630cSAmit Kucheria 5057d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 2>; 5058d2fa630cSAmit Kucheria 5059d2fa630cSAmit Kucheria trips { 5060d2fa630cSAmit Kucheria video_alert0: trip-point0 { 5061d2fa630cSAmit Kucheria temperature = <90000>; 5062d2fa630cSAmit Kucheria hysteresis = <2000>; 5063d2fa630cSAmit Kucheria type = "hot"; 5064d2fa630cSAmit Kucheria }; 5065d2fa630cSAmit Kucheria }; 5066d2fa630cSAmit Kucheria }; 5067d2fa630cSAmit Kucheria 5068d2fa630cSAmit Kucheria mem-thermal { 5069d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5070d2fa630cSAmit Kucheria polling-delay = <1000>; 5071d2fa630cSAmit Kucheria 5072d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 3>; 5073d2fa630cSAmit Kucheria 5074d2fa630cSAmit Kucheria trips { 5075d2fa630cSAmit Kucheria mem_alert0: trip-point0 { 5076d2fa630cSAmit Kucheria temperature = <90000>; 5077d2fa630cSAmit Kucheria hysteresis = <2000>; 5078d2fa630cSAmit Kucheria type = "hot"; 5079d2fa630cSAmit Kucheria }; 5080d2fa630cSAmit Kucheria }; 5081d2fa630cSAmit Kucheria }; 5082d2fa630cSAmit Kucheria 5083d2fa630cSAmit Kucheria q6-hvx-thermal { 5084d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5085d2fa630cSAmit Kucheria polling-delay = <1000>; 5086d2fa630cSAmit Kucheria 5087d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 4>; 5088d2fa630cSAmit Kucheria 5089d2fa630cSAmit Kucheria trips { 5090d2fa630cSAmit Kucheria q6_hvx_alert0: trip-point0 { 5091d2fa630cSAmit Kucheria temperature = <90000>; 5092d2fa630cSAmit Kucheria hysteresis = <2000>; 5093d2fa630cSAmit Kucheria type = "hot"; 5094d2fa630cSAmit Kucheria }; 5095d2fa630cSAmit Kucheria }; 5096d2fa630cSAmit Kucheria }; 5097d2fa630cSAmit Kucheria 5098d2fa630cSAmit Kucheria camera-thermal { 5099d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5100d2fa630cSAmit Kucheria polling-delay = <1000>; 5101d2fa630cSAmit Kucheria 5102d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 5>; 5103d2fa630cSAmit Kucheria 5104d2fa630cSAmit Kucheria trips { 5105d2fa630cSAmit Kucheria camera_alert0: trip-point0 { 5106d2fa630cSAmit Kucheria temperature = <90000>; 5107d2fa630cSAmit Kucheria hysteresis = <2000>; 5108d2fa630cSAmit Kucheria type = "hot"; 5109d2fa630cSAmit Kucheria }; 5110d2fa630cSAmit Kucheria }; 5111d2fa630cSAmit Kucheria }; 5112d2fa630cSAmit Kucheria 5113d2fa630cSAmit Kucheria compute-thermal { 5114d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5115d2fa630cSAmit Kucheria polling-delay = <1000>; 5116d2fa630cSAmit Kucheria 5117d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 6>; 5118d2fa630cSAmit Kucheria 5119d2fa630cSAmit Kucheria trips { 5120d2fa630cSAmit Kucheria compute_alert0: trip-point0 { 5121d2fa630cSAmit Kucheria temperature = <90000>; 5122d2fa630cSAmit Kucheria hysteresis = <2000>; 5123d2fa630cSAmit Kucheria type = "hot"; 5124d2fa630cSAmit Kucheria }; 5125d2fa630cSAmit Kucheria }; 5126d2fa630cSAmit Kucheria }; 5127d2fa630cSAmit Kucheria 5128d2fa630cSAmit Kucheria modem-thermal { 5129d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5130d2fa630cSAmit Kucheria polling-delay = <1000>; 5131d2fa630cSAmit Kucheria 5132d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 7>; 5133d2fa630cSAmit Kucheria 5134d2fa630cSAmit Kucheria trips { 5135d2fa630cSAmit Kucheria modem_alert0: trip-point0 { 5136d2fa630cSAmit Kucheria temperature = <90000>; 5137d2fa630cSAmit Kucheria hysteresis = <2000>; 5138d2fa630cSAmit Kucheria type = "hot"; 5139d2fa630cSAmit Kucheria }; 5140d2fa630cSAmit Kucheria }; 5141d2fa630cSAmit Kucheria }; 5142d2fa630cSAmit Kucheria 5143d2fa630cSAmit Kucheria npu-thermal { 5144d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5145d2fa630cSAmit Kucheria polling-delay = <1000>; 5146d2fa630cSAmit Kucheria 5147d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 8>; 5148d2fa630cSAmit Kucheria 5149d2fa630cSAmit Kucheria trips { 5150d2fa630cSAmit Kucheria npu_alert0: trip-point0 { 5151d2fa630cSAmit Kucheria temperature = <90000>; 5152d2fa630cSAmit Kucheria hysteresis = <2000>; 5153d2fa630cSAmit Kucheria type = "hot"; 5154d2fa630cSAmit Kucheria }; 5155d2fa630cSAmit Kucheria }; 5156d2fa630cSAmit Kucheria }; 5157d2fa630cSAmit Kucheria 5158d2fa630cSAmit Kucheria modem-vec-thermal { 5159d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5160d2fa630cSAmit Kucheria polling-delay = <1000>; 5161d2fa630cSAmit Kucheria 5162d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 9>; 5163d2fa630cSAmit Kucheria 5164d2fa630cSAmit Kucheria trips { 5165d2fa630cSAmit Kucheria modem_vec_alert0: trip-point0 { 5166d2fa630cSAmit Kucheria temperature = <90000>; 5167d2fa630cSAmit Kucheria hysteresis = <2000>; 5168d2fa630cSAmit Kucheria type = "hot"; 5169d2fa630cSAmit Kucheria }; 5170d2fa630cSAmit Kucheria }; 5171d2fa630cSAmit Kucheria }; 5172d2fa630cSAmit Kucheria 5173d2fa630cSAmit Kucheria modem-scl-thermal { 5174d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5175d2fa630cSAmit Kucheria polling-delay = <1000>; 5176d2fa630cSAmit Kucheria 5177d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 10>; 5178d2fa630cSAmit Kucheria 5179d2fa630cSAmit Kucheria trips { 5180d2fa630cSAmit Kucheria modem_scl_alert0: trip-point0 { 5181d2fa630cSAmit Kucheria temperature = <90000>; 5182d2fa630cSAmit Kucheria hysteresis = <2000>; 5183d2fa630cSAmit Kucheria type = "hot"; 5184d2fa630cSAmit Kucheria }; 5185d2fa630cSAmit Kucheria }; 5186d2fa630cSAmit Kucheria }; 5187d2fa630cSAmit Kucheria 51887be1c395SDavid Heidelberg gpu-bottom-thermal { 5189d2fa630cSAmit Kucheria polling-delay-passive = <250>; 5190d2fa630cSAmit Kucheria polling-delay = <1000>; 5191d2fa630cSAmit Kucheria 5192d2fa630cSAmit Kucheria thermal-sensors = <&tsens1 11>; 5193d2fa630cSAmit Kucheria 5194d2fa630cSAmit Kucheria trips { 5195d2fa630cSAmit Kucheria gpu2_alert0: trip-point0 { 5196d2fa630cSAmit Kucheria temperature = <90000>; 5197d2fa630cSAmit Kucheria hysteresis = <2000>; 5198d2fa630cSAmit Kucheria type = "hot"; 5199d2fa630cSAmit Kucheria }; 5200d2fa630cSAmit Kucheria }; 5201d2fa630cSAmit Kucheria }; 5202d2fa630cSAmit Kucheria }; 5203e13c6d14SVinod Koul}; 5204