14b565ca5SJordan Crouse // SPDX-License-Identifier: GPL-2.0
2e812744cSSharat Masetty /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
34b565ca5SJordan Crouse
44b565ca5SJordan Crouse #include <linux/clk.h>
5fcf9d0b7SJordan Crouse #include <linux/interconnect.h>
69325d426SJordan Crouse #include <linux/of_platform.h>
74b565ca5SJordan Crouse #include <linux/platform_device.h>
84b565ca5SJordan Crouse #include <linux/pm_domain.h>
929ac8979SJonathan Marek #include <linux/pm_opp.h>
104b565ca5SJordan Crouse #include <soc/qcom/cmd-db.h>
114b565ca5SJordan Crouse #include <drm/drm_gem.h>
124b565ca5SJordan Crouse
1329ac8979SJonathan Marek #include "a6xx_gpu.h"
1474c0a69cSRob Clark #include "a6xx_gmu.xml.h"
1529ac8979SJonathan Marek #include "msm_gem.h"
164b565ca5SJordan Crouse #include "msm_gpu_trace.h"
17e31fdb74SJordan Crouse #include "msm_mmu.h"
18e31fdb74SJordan Crouse
a6xx_gmu_fault(struct a6xx_gmu * gmu)19e31fdb74SJordan Crouse static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
20e31fdb74SJordan Crouse {
21e31fdb74SJordan Crouse struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
22e31fdb74SJordan Crouse struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
23e31fdb74SJordan Crouse struct msm_gpu *gpu = &adreno_gpu->base;
24e31fdb74SJordan Crouse
25e31fdb74SJordan Crouse /* FIXME: add a banner here */
26e31fdb74SJordan Crouse gmu->hung = true;
27e31fdb74SJordan Crouse
28e31fdb74SJordan Crouse /* Turn off the hangcheck timer while we are resetting */
29e31fdb74SJordan Crouse del_timer(&gpu->hangcheck_timer);
307e688294SRob Clark
31e31fdb74SJordan Crouse /* Queue the GPU handler because we need to treat this as a recovery */
32e31fdb74SJordan Crouse kthread_queue_work(gpu->worker, &gpu->recover_work);
334b565ca5SJordan Crouse }
344b565ca5SJordan Crouse
a6xx_gmu_irq(int irq,void * data)354b565ca5SJordan Crouse static irqreturn_t a6xx_gmu_irq(int irq, void *data)
364b565ca5SJordan Crouse {
374b565ca5SJordan Crouse struct a6xx_gmu *gmu = data;
384b565ca5SJordan Crouse u32 status;
394b565ca5SJordan Crouse
404b565ca5SJordan Crouse status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
414b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
424b565ca5SJordan Crouse
434b565ca5SJordan Crouse if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
44e31fdb74SJordan Crouse dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
454b565ca5SJordan Crouse
464b565ca5SJordan Crouse a6xx_gmu_fault(gmu);
474b565ca5SJordan Crouse }
484b565ca5SJordan Crouse
494b565ca5SJordan Crouse if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
504b565ca5SJordan Crouse dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
514b565ca5SJordan Crouse
524b565ca5SJordan Crouse if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
534b565ca5SJordan Crouse dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
544b565ca5SJordan Crouse gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
554b565ca5SJordan Crouse
564b565ca5SJordan Crouse return IRQ_HANDLED;
574b565ca5SJordan Crouse }
584b565ca5SJordan Crouse
a6xx_hfi_irq(int irq,void * data)594b565ca5SJordan Crouse static irqreturn_t a6xx_hfi_irq(int irq, void *data)
604b565ca5SJordan Crouse {
614b565ca5SJordan Crouse struct a6xx_gmu *gmu = data;
624b565ca5SJordan Crouse u32 status;
634b565ca5SJordan Crouse
644b565ca5SJordan Crouse status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
654b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
664b565ca5SJordan Crouse
674b565ca5SJordan Crouse if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
68e31fdb74SJordan Crouse dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
694b565ca5SJordan Crouse
704b565ca5SJordan Crouse a6xx_gmu_fault(gmu);
714b565ca5SJordan Crouse }
724b565ca5SJordan Crouse
734b565ca5SJordan Crouse return IRQ_HANDLED;
741707add8SJordan Crouse }
754b565ca5SJordan Crouse
a6xx_gmu_sptprac_is_on(struct a6xx_gmu * gmu)761707add8SJordan Crouse bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
771707add8SJordan Crouse {
781707add8SJordan Crouse u32 val;
79606ec90fSSean Paul
801707add8SJordan Crouse /* This can be called from gpu state code so make sure GMU is valid */
811707add8SJordan Crouse if (!gmu->initialized)
821707add8SJordan Crouse return false;
831707add8SJordan Crouse
841707add8SJordan Crouse val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
851707add8SJordan Crouse
861707add8SJordan Crouse return !(val &
871707add8SJordan Crouse (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
881707add8SJordan Crouse A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
891707add8SJordan Crouse }
901707add8SJordan Crouse
911707add8SJordan Crouse /* Check to see if the GX rail is still powered */
a6xx_gmu_gx_is_on(struct a6xx_gmu * gmu)921707add8SJordan Crouse bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
931707add8SJordan Crouse {
941707add8SJordan Crouse u32 val;
95606ec90fSSean Paul
961707add8SJordan Crouse /* This can be called from gpu state code so make sure GMU is valid */
971707add8SJordan Crouse if (!gmu->initialized)
981707add8SJordan Crouse return false;
994b565ca5SJordan Crouse
1004b565ca5SJordan Crouse val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
1014b565ca5SJordan Crouse
1024b565ca5SJordan Crouse return !(val &
1034b565ca5SJordan Crouse (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
1044b565ca5SJordan Crouse A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
1056694482aSDouglas Anderson }
1066694482aSDouglas Anderson
a6xx_gmu_set_freq(struct msm_gpu * gpu,struct dev_pm_opp * opp,bool suspended)1074b565ca5SJordan Crouse void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
1081f60d114SSharat Masetty bool suspended)
1091f60d114SSharat Masetty {
1101f60d114SSharat Masetty struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1111f60d114SSharat Masetty struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1121f60d114SSharat Masetty struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1131f60d114SSharat Masetty u32 perf_index;
1141f60d114SSharat Masetty unsigned long gpu_freq;
1151f60d114SSharat Masetty int ret = 0;
1161f60d114SSharat Masetty
1171f60d114SSharat Masetty gpu_freq = dev_pm_opp_get_freq(opp);
1181f60d114SSharat Masetty
1191f60d114SSharat Masetty if (gpu_freq == gmu->freq)
1201f60d114SSharat Masetty return;
1211f60d114SSharat Masetty
1221f60d114SSharat Masetty for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
1231f60d114SSharat Masetty if (gpu_freq == gmu->gpu_freqs[perf_index])
1241f60d114SSharat Masetty break;
1251f60d114SSharat Masetty
1261f60d114SSharat Masetty gmu->current_perf_index = perf_index;
12774c0a69cSRob Clark gmu->freq = gmu->gpu_freqs[perf_index];
12874c0a69cSRob Clark
1291f60d114SSharat Masetty trace_msm_gmu_freq_change(gmu->freq, perf_index);
1301f60d114SSharat Masetty
1316694482aSDouglas Anderson /*
1326694482aSDouglas Anderson * This can get called from devfreq while the hardware is idle. Don't
1336694482aSDouglas Anderson * bring up the power if it isn't already active. All we're doing here
1341f60d114SSharat Masetty * is updating the frequency so that when we come back online we're at
1356694482aSDouglas Anderson * the right rate.
1361f60d114SSharat Masetty */
1371f60d114SSharat Masetty if (suspended)
1381f60d114SSharat Masetty return;
1391f60d114SSharat Masetty
140920b4a67SViresh Kumar if (!gmu->legacy) {
1411f60d114SSharat Masetty a6xx_hfi_set_freq(gmu, perf_index);
1421f60d114SSharat Masetty dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
143a2c3c0a5SSharat Masetty return;
1444b565ca5SJordan Crouse }
1454b565ca5SJordan Crouse
1464b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
1471f60d114SSharat Masetty
1484b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
1494b565ca5SJordan Crouse ((3 & 0xf) << 28) | perf_index);
1504b565ca5SJordan Crouse
1514b565ca5SJordan Crouse /*
1524b565ca5SJordan Crouse * Send an invalid index as a vote for the bus bandwidth and let the
1534b565ca5SJordan Crouse * firmware decide on the right vote
1544b565ca5SJordan Crouse */
1554b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
1564b565ca5SJordan Crouse
1574b565ca5SJordan Crouse /* Set and clear the OOB for DCVS to trigger the GMU */
1584b565ca5SJordan Crouse a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
159a2c3c0a5SSharat Masetty a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
160a2c3c0a5SSharat Masetty
161a2c3c0a5SSharat Masetty ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
162a2c3c0a5SSharat Masetty if (ret)
163920b4a67SViresh Kumar dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
164a2c3c0a5SSharat Masetty
165a2c3c0a5SSharat Masetty dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
166a2c3c0a5SSharat Masetty }
167a2c3c0a5SSharat Masetty
a6xx_gmu_get_freq(struct msm_gpu * gpu)168a2c3c0a5SSharat Masetty unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
169a2c3c0a5SSharat Masetty {
170a2c3c0a5SSharat Masetty struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
171a2c3c0a5SSharat Masetty struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
172a2c3c0a5SSharat Masetty struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1734b565ca5SJordan Crouse
1744b565ca5SJordan Crouse return gmu->freq;
1754b565ca5SJordan Crouse }
1764b565ca5SJordan Crouse
a6xx_gmu_check_idle_level(struct a6xx_gmu * gmu)1774b565ca5SJordan Crouse static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
1784b565ca5SJordan Crouse {
1794b565ca5SJordan Crouse u32 val;
1804b565ca5SJordan Crouse int local = gmu->idle_level;
1814b565ca5SJordan Crouse
1824b565ca5SJordan Crouse /* SPTP and IFPC both report as IFPC */
1834b565ca5SJordan Crouse if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
1844b565ca5SJordan Crouse local = GMU_IDLE_STATE_IFPC;
1854b565ca5SJordan Crouse
1864b565ca5SJordan Crouse val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1874b565ca5SJordan Crouse
1884b565ca5SJordan Crouse if (val == local) {
1894b565ca5SJordan Crouse if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
1904b565ca5SJordan Crouse !a6xx_gmu_gx_is_on(gmu))
1914b565ca5SJordan Crouse return true;
1924b565ca5SJordan Crouse }
1934b565ca5SJordan Crouse
1944b565ca5SJordan Crouse return false;
1954b565ca5SJordan Crouse }
196e31fdb74SJordan Crouse
1974b565ca5SJordan Crouse /* Wait for the GMU to get to its most idle state */
a6xx_gmu_wait_for_idle(struct a6xx_gmu * gmu)1984b565ca5SJordan Crouse int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
1994b565ca5SJordan Crouse {
2004b565ca5SJordan Crouse return spin_until(a6xx_gmu_check_idle_level(gmu));
2014b565ca5SJordan Crouse }
2024b565ca5SJordan Crouse
a6xx_gmu_start(struct a6xx_gmu * gmu)2034b565ca5SJordan Crouse static int a6xx_gmu_start(struct a6xx_gmu *gmu)
2044b565ca5SJordan Crouse {
205f5749d61SDmitry Baryshkov int ret;
206f5749d61SDmitry Baryshkov u32 val;
207f5749d61SDmitry Baryshkov u32 mask, reset_val;
208f5749d61SDmitry Baryshkov
209f5749d61SDmitry Baryshkov val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
210f5749d61SDmitry Baryshkov if (val <= 0x20010004) {
211f5749d61SDmitry Baryshkov mask = 0xffffffff;
212f5749d61SDmitry Baryshkov reset_val = 0xbabeface;
213f5749d61SDmitry Baryshkov } else {
214f5749d61SDmitry Baryshkov mask = 0x1ff;
2154b565ca5SJordan Crouse reset_val = 0x100;
2164b565ca5SJordan Crouse }
217ad4968d5SJonathan Marek
218ad4968d5SJonathan Marek gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
219ad4968d5SJonathan Marek
220ad4968d5SJonathan Marek /* Set the log wptr index
221ad4968d5SJonathan Marek * note: downstream saves the value in poweroff and restores it here
222ad4968d5SJonathan Marek */
2234b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
2244b565ca5SJordan Crouse
2254b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
226f5749d61SDmitry Baryshkov
2274b565ca5SJordan Crouse ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
2284b565ca5SJordan Crouse (val & mask) == reset_val, 100, 10000);
2296a41da17SMamta Shukla
2304b565ca5SJordan Crouse if (ret)
2314b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
2324b565ca5SJordan Crouse
2334b565ca5SJordan Crouse return ret;
2344b565ca5SJordan Crouse }
2354b565ca5SJordan Crouse
a6xx_gmu_hfi_start(struct a6xx_gmu * gmu)2364b565ca5SJordan Crouse static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
2374b565ca5SJordan Crouse {
2384b565ca5SJordan Crouse u32 val;
2394b565ca5SJordan Crouse int ret;
2404b565ca5SJordan Crouse
2414b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
2424b565ca5SJordan Crouse
2434b565ca5SJordan Crouse ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
2446a41da17SMamta Shukla val & 1, 100, 10000);
2454b565ca5SJordan Crouse if (ret)
2464b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
2474b565ca5SJordan Crouse
2484b565ca5SJordan Crouse return ret;
249555c50a4SEric Anholt }
2502fc8a92eSAkhil P Oommen
251555c50a4SEric Anholt struct a6xx_gmu_oob_bits {
252555c50a4SEric Anholt int set, ack, set_new, ack_new, clear, clear_new;
253555c50a4SEric Anholt const char *name;
254555c50a4SEric Anholt };
255555c50a4SEric Anholt
256555c50a4SEric Anholt /* These are the interrupt / ack bits for each OOB request that are set
257555c50a4SEric Anholt * in a6xx_gmu_set_oob and a6xx_clear_oob
258555c50a4SEric Anholt */
259555c50a4SEric Anholt static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
260555c50a4SEric Anholt [GMU_OOB_GPU_SET] = {
261555c50a4SEric Anholt .name = "GPU_SET",
262555c50a4SEric Anholt .set = 16,
263555c50a4SEric Anholt .ack = 24,
2642fc8a92eSAkhil P Oommen .set_new = 30,
2652fc8a92eSAkhil P Oommen .ack_new = 31,
266555c50a4SEric Anholt .clear = 24,
267555c50a4SEric Anholt .clear_new = 31,
268555c50a4SEric Anholt },
269555c50a4SEric Anholt
270555c50a4SEric Anholt [GMU_OOB_PERFCOUNTER_SET] = {
271555c50a4SEric Anholt .name = "PERFCOUNTER",
272555c50a4SEric Anholt .set = 17,
273555c50a4SEric Anholt .ack = 25,
2742fc8a92eSAkhil P Oommen .set_new = 28,
2752fc8a92eSAkhil P Oommen .ack_new = 30,
276555c50a4SEric Anholt .clear = 25,
277555c50a4SEric Anholt .clear_new = 29,
278555c50a4SEric Anholt },
279555c50a4SEric Anholt
280555c50a4SEric Anholt [GMU_OOB_BOOT_SLUMBER] = {
281555c50a4SEric Anholt .name = "BOOT_SLUMBER",
2822fc8a92eSAkhil P Oommen .set = 22,
283555c50a4SEric Anholt .ack = 30,
284555c50a4SEric Anholt .clear = 30,
285555c50a4SEric Anholt },
286555c50a4SEric Anholt
287555c50a4SEric Anholt [GMU_OOB_DCVS_SET] = {
288555c50a4SEric Anholt .name = "GPU_DCVS",
2892fc8a92eSAkhil P Oommen .set = 23,
290555c50a4SEric Anholt .ack = 31,
291555c50a4SEric Anholt .clear = 31,
292555c50a4SEric Anholt },
2934b565ca5SJordan Crouse };
2944b565ca5SJordan Crouse
2954b565ca5SJordan Crouse /* Trigger a OOB (out of band) request to the GMU */
a6xx_gmu_set_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state)2964b565ca5SJordan Crouse int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
2974b565ca5SJordan Crouse {
2984b565ca5SJordan Crouse int ret;
2994b565ca5SJordan Crouse u32 val;
300f6f59072SRob Clark int request, ack;
301f6f59072SRob Clark
302555c50a4SEric Anholt WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
3034b565ca5SJordan Crouse
304555c50a4SEric Anholt if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
305555c50a4SEric Anholt return -EINVAL;
306555c50a4SEric Anholt
307555c50a4SEric Anholt if (gmu->legacy) {
308555c50a4SEric Anholt request = a6xx_gmu_oob_bits[state].set;
309555c50a4SEric Anholt ack = a6xx_gmu_oob_bits[state].ack;
310555c50a4SEric Anholt } else {
311555c50a4SEric Anholt request = a6xx_gmu_oob_bits[state].set_new;
312555c50a4SEric Anholt ack = a6xx_gmu_oob_bits[state].ack_new;
313555c50a4SEric Anholt if (!request || !ack) {
314555c50a4SEric Anholt DRM_DEV_ERROR(gmu->dev,
315555c50a4SEric Anholt "Invalid non-legacy GMU request %s\n",
316555c50a4SEric Anholt a6xx_gmu_oob_bits[state].name);
3174b565ca5SJordan Crouse return -EINVAL;
3184b565ca5SJordan Crouse }
3194b565ca5SJordan Crouse }
3204b565ca5SJordan Crouse
3214b565ca5SJordan Crouse /* Trigger the equested OOB operation */
3224b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
3234b565ca5SJordan Crouse
3244b565ca5SJordan Crouse /* Wait for the acknowledge interrupt */
3254b565ca5SJordan Crouse ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
3264b565ca5SJordan Crouse val & (1 << ack), 100, 10000);
3276a41da17SMamta Shukla
3284b565ca5SJordan Crouse if (ret)
329555c50a4SEric Anholt DRM_DEV_ERROR(gmu->dev,
3304b565ca5SJordan Crouse "Timeout waiting for GMU OOB set %s: 0x%x\n",
3314b565ca5SJordan Crouse a6xx_gmu_oob_bits[state].name,
3324b565ca5SJordan Crouse gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
3334b565ca5SJordan Crouse
3344b565ca5SJordan Crouse /* Clear the acknowledge interrupt */
3354b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
3364b565ca5SJordan Crouse
3374b565ca5SJordan Crouse return ret;
3384b565ca5SJordan Crouse }
3394b565ca5SJordan Crouse
3404b565ca5SJordan Crouse /* Clear a pending OOB state in the GMU */
a6xx_gmu_clear_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state)341555c50a4SEric Anholt void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
3428167e6faSJonathan Marek {
343f6f59072SRob Clark int bit;
344f6f59072SRob Clark
345555c50a4SEric Anholt WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
346555c50a4SEric Anholt
347555c50a4SEric Anholt if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
348555c50a4SEric Anholt return;
3492fc8a92eSAkhil P Oommen
350555c50a4SEric Anholt if (gmu->legacy)
3512fc8a92eSAkhil P Oommen bit = a6xx_gmu_oob_bits[state].clear;
352555c50a4SEric Anholt else
35365aee407SJonathan Marek bit = a6xx_gmu_oob_bits[state].clear_new;
3544b565ca5SJordan Crouse
3554b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
3564b565ca5SJordan Crouse }
357bd31afe0SKonrad Dybcio
3584b565ca5SJordan Crouse /* Enable CPU control of SPTP power power collapse */
a6xx_sptprac_enable(struct a6xx_gmu * gmu)3594b565ca5SJordan Crouse int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
3604b565ca5SJordan Crouse {
3614b565ca5SJordan Crouse int ret;
3628167e6faSJonathan Marek u32 val;
3638167e6faSJonathan Marek
3648167e6faSJonathan Marek if (!gmu->legacy)
3654b565ca5SJordan Crouse return 0;
3664b565ca5SJordan Crouse
3674b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
3684b565ca5SJordan Crouse
3694b565ca5SJordan Crouse ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
3704b565ca5SJordan Crouse (val & 0x38) == 0x28, 1, 100);
3716a41da17SMamta Shukla
3724b565ca5SJordan Crouse if (ret) {
3734b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
3744b565ca5SJordan Crouse gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
3754b565ca5SJordan Crouse }
3764b565ca5SJordan Crouse
3774b565ca5SJordan Crouse return 0;
3784b565ca5SJordan Crouse }
379bd31afe0SKonrad Dybcio
3804b565ca5SJordan Crouse /* Disable CPU control of SPTP power power collapse */
a6xx_sptprac_disable(struct a6xx_gmu * gmu)3814b565ca5SJordan Crouse void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
3824b565ca5SJordan Crouse {
3834b565ca5SJordan Crouse u32 val;
3848167e6faSJonathan Marek int ret;
3858167e6faSJonathan Marek
3868167e6faSJonathan Marek if (!gmu->legacy)
3874b565ca5SJordan Crouse return;
3884b565ca5SJordan Crouse
3894b565ca5SJordan Crouse /* Make sure retention is on */
3904b565ca5SJordan Crouse gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
3914b565ca5SJordan Crouse
3924b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
3934b565ca5SJordan Crouse
3944b565ca5SJordan Crouse ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
3954b565ca5SJordan Crouse (val & 0x04), 100, 10000);
3966a41da17SMamta Shukla
3974b565ca5SJordan Crouse if (ret)
3984b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
3994b565ca5SJordan Crouse gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
4004b565ca5SJordan Crouse }
4014b565ca5SJordan Crouse
4024b565ca5SJordan Crouse /* Let the GMU know we are starting a boot sequence */
a6xx_gmu_gfx_rail_on(struct a6xx_gmu * gmu)4034b565ca5SJordan Crouse static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
4044b565ca5SJordan Crouse {
4054b565ca5SJordan Crouse u32 vote;
4064b565ca5SJordan Crouse
4074b565ca5SJordan Crouse /* Let the GMU know we are getting ready for boot */
4084b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
4094b565ca5SJordan Crouse
4104b565ca5SJordan Crouse /* Choose the "default" power level as the highest available */
4114b565ca5SJordan Crouse vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
4124b565ca5SJordan Crouse
4134b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
4144b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
4154b565ca5SJordan Crouse
4164b565ca5SJordan Crouse /* Let the GMU know the boot sequence has started */
4174b565ca5SJordan Crouse return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
4184b565ca5SJordan Crouse }
4194b565ca5SJordan Crouse
4204b565ca5SJordan Crouse /* Let the GMU know that we are about to go into slumber */
a6xx_gmu_notify_slumber(struct a6xx_gmu * gmu)4214b565ca5SJordan Crouse static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
4224b565ca5SJordan Crouse {
4234b565ca5SJordan Crouse int ret;
4244b565ca5SJordan Crouse
4254b565ca5SJordan Crouse /* Disable the power counter so the GMU isn't busy */
4264b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
4274b565ca5SJordan Crouse
4284b565ca5SJordan Crouse /* Disable SPTP_PC if the CPU is responsible for it */
4294b565ca5SJordan Crouse if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
4308167e6faSJonathan Marek a6xx_sptprac_disable(gmu);
4318167e6faSJonathan Marek
4328167e6faSJonathan Marek if (!gmu->legacy) {
4338167e6faSJonathan Marek ret = a6xx_hfi_send_prep_slumber(gmu);
4348167e6faSJonathan Marek goto out;
4354b565ca5SJordan Crouse }
4364b565ca5SJordan Crouse
4374b565ca5SJordan Crouse /* Tell the GMU to get ready to slumber */
4384b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
4394b565ca5SJordan Crouse
4404b565ca5SJordan Crouse ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
4414b565ca5SJordan Crouse a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
4424b565ca5SJordan Crouse
4434b565ca5SJordan Crouse if (!ret) {
4444b565ca5SJordan Crouse /* Check to see if the GMU really did slumber */
4456a41da17SMamta Shukla if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
4464b565ca5SJordan Crouse != 0x0f) {
4474b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
4484b565ca5SJordan Crouse ret = -ETIMEDOUT;
4494b565ca5SJordan Crouse }
4508167e6faSJonathan Marek }
4514b565ca5SJordan Crouse
4524b565ca5SJordan Crouse out:
4534b565ca5SJordan Crouse /* Put fence into allow mode */
4544b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
4554b565ca5SJordan Crouse return ret;
4564b565ca5SJordan Crouse }
4574b565ca5SJordan Crouse
a6xx_rpmh_start(struct a6xx_gmu * gmu)4584b565ca5SJordan Crouse static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
4594b565ca5SJordan Crouse {
4604b565ca5SJordan Crouse int ret;
4614b565ca5SJordan Crouse u32 val;
4624b565ca5SJordan Crouse
4634b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
4644b565ca5SJordan Crouse /* Wait for the register to finish posting */
4654b565ca5SJordan Crouse wmb();
4664b565ca5SJordan Crouse
4674b565ca5SJordan Crouse ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
4686a41da17SMamta Shukla val & (1 << 1), 100, 10000);
4694b565ca5SJordan Crouse if (ret) {
4704b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
4714b565ca5SJordan Crouse return ret;
47202ef80c5SJonathan Marek }
4734b565ca5SJordan Crouse
4744b565ca5SJordan Crouse ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
47556869210SJordan Crouse !val, 100, 10000);
4766a41da17SMamta Shukla
4774b565ca5SJordan Crouse if (ret) {
4784b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
4794b565ca5SJordan Crouse return ret;
48056869210SJordan Crouse }
48156869210SJordan Crouse
48256869210SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
48356869210SJordan Crouse
48456869210SJordan Crouse return 0;
4854b565ca5SJordan Crouse }
4864b565ca5SJordan Crouse
a6xx_rpmh_stop(struct a6xx_gmu * gmu)4874b565ca5SJordan Crouse static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
4884b565ca5SJordan Crouse {
4894b565ca5SJordan Crouse int ret;
4904b565ca5SJordan Crouse u32 val;
4914b565ca5SJordan Crouse
49202ef80c5SJonathan Marek gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
4934b565ca5SJordan Crouse
4944b565ca5SJordan Crouse ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
4956a41da17SMamta Shukla val, val & (1 << 16), 100, 10000);
4964b565ca5SJordan Crouse if (ret)
4974b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
4984b565ca5SJordan Crouse
4994b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
500f8fc924eSJordan Crouse }
501f8fc924eSJordan Crouse
pdc_write(void __iomem * ptr,u32 offset,u32 value)502d7499634SGeert Uytterhoeven static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
503f8fc924eSJordan Crouse {
504f8fc924eSJordan Crouse msm_writel(value, ptr + (offset << 2));
505f8fc924eSJordan Crouse }
506f8fc924eSJordan Crouse
507f8fc924eSJordan Crouse static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
5084b565ca5SJordan Crouse const char *name);
5094b565ca5SJordan Crouse
a6xx_gmu_rpmh_init(struct a6xx_gmu * gmu)510e812744cSSharat Masetty static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
511e812744cSSharat Masetty {
512f8fc924eSJordan Crouse struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
513f8fc924eSJordan Crouse struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
5143d91e50fSDan Carpenter struct platform_device *pdev = to_platform_device(gmu->dev);
51502ef80c5SJonathan Marek void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
51664245fc5SJonathan Marek void __iomem *seqptr = NULL;
517f8fc924eSJordan Crouse uint32_t pdc_address_offset;
5183d91e50fSDan Carpenter bool pdc_in_aop = false;
519f8fc924eSJordan Crouse
520f8fc924eSJordan Crouse if (IS_ERR(pdcptr))
521192f4ee3SAkhil P Oommen goto err;
52264245fc5SJonathan Marek
523083cc3a4SRob Clark if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
52402ef80c5SJonathan Marek pdc_in_aop = true;
525b7616b5cSKonrad Dybcio else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
526b7616b5cSKonrad Dybcio pdc_address_offset = 0x30090;
52702ef80c5SJonathan Marek else if (adreno_is_a619(adreno_gpu))
52802ef80c5SJonathan Marek pdc_address_offset = 0x300a0;
52902ef80c5SJonathan Marek else
53064245fc5SJonathan Marek pdc_address_offset = 0x30080;
53164245fc5SJonathan Marek
5323d91e50fSDan Carpenter if (!pdc_in_aop) {
53364245fc5SJonathan Marek seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
53464245fc5SJonathan Marek if (IS_ERR(seqptr))
53564245fc5SJonathan Marek goto err;
5364b565ca5SJordan Crouse }
53702ef80c5SJonathan Marek
5384b565ca5SJordan Crouse /* Disable SDE clock gating */
5394b565ca5SJordan Crouse gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
54002ef80c5SJonathan Marek
54102ef80c5SJonathan Marek /* Setup RSC PDC handshake for sleep and wakeup */
54202ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
54302ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
54402ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
54502ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
54602ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
54702ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
54802ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
54902ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
55002ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
5514b565ca5SJordan Crouse gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
5524b565ca5SJordan Crouse gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
553f6d62d09SJonathan Marek
55402ef80c5SJonathan Marek /* Load RSC sequencer uCode for sleep and wakeup */
55502ef80c5SJonathan Marek if (adreno_is_a650_family(adreno_gpu)) {
55602ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
55702ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
55802ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
55902ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
56002ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
56102ef80c5SJonathan Marek } else {
56202ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
56302ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
56402ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
56502ef80c5SJonathan Marek gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
5664b565ca5SJordan Crouse gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
56764245fc5SJonathan Marek }
56864245fc5SJonathan Marek
56964245fc5SJonathan Marek if (pdc_in_aop)
5704b565ca5SJordan Crouse goto setup_pdc;
571f8fc924eSJordan Crouse
572f8fc924eSJordan Crouse /* Load PDC sequencer uCode for power up and power down sequence */
573f8fc924eSJordan Crouse pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
574f8fc924eSJordan Crouse pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
575f8fc924eSJordan Crouse pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
5764b565ca5SJordan Crouse pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
5774b565ca5SJordan Crouse pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
578f8fc924eSJordan Crouse
579f8fc924eSJordan Crouse /* Set TCS commands used by PDC sequence for low power modes */
580f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
581f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
582f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
583f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
584f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
585f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
586f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
587e812744cSSharat Masetty pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
588f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
58902ef80c5SJonathan Marek
590f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
591e812744cSSharat Masetty pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
592f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
593f8fc924eSJordan Crouse
594f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
595f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
596f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
597f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
598e812744cSSharat Masetty pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
599f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
600f8fc924eSJordan Crouse
601b7616b5cSKonrad Dybcio pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
602b7616b5cSKonrad Dybcio pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
603e812744cSSharat Masetty if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) ||
604e812744cSSharat Masetty adreno_is_a650_family(adreno_gpu))
605f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
606f8fc924eSJordan Crouse else
60702ef80c5SJonathan Marek pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
608f8fc924eSJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
6094b565ca5SJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
6104b565ca5SJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
61164245fc5SJonathan Marek
612f8fc924eSJordan Crouse /* Setup GPU PDC */
613f8fc924eSJordan Crouse setup_pdc:
6144b565ca5SJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
6154b565ca5SJordan Crouse pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
6164b565ca5SJordan Crouse
617f8fc924eSJordan Crouse /* ensure no writes happen before the uCode is fully written */
6188559da8fSRob Clark wmb();
6198559da8fSRob Clark
620f8fc924eSJordan Crouse a6xx_rpmh_stop(gmu);
6215ca4a094SSean Paul
622a62fb211SSean Paul err:
6235ca4a094SSean Paul if (!IS_ERR_OR_NULL(pdcptr))
624a62fb211SSean Paul iounmap(pdcptr);
6254b565ca5SJordan Crouse if (!IS_ERR_OR_NULL(seqptr))
6264b565ca5SJordan Crouse iounmap(seqptr);
6274b565ca5SJordan Crouse }
6284b565ca5SJordan Crouse
6294b565ca5SJordan Crouse /*
6304b565ca5SJordan Crouse * The lowest 16 bits of this value are the number of XO clock cycles for main
6314b565ca5SJordan Crouse * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
6324b565ca5SJordan Crouse * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
6334b565ca5SJordan Crouse */
6344b565ca5SJordan Crouse
6354b565ca5SJordan Crouse #define GMU_PWR_COL_HYST 0x000a1680
6364b565ca5SJordan Crouse
6374b565ca5SJordan Crouse /* Set up the idle state for the GMU */
a6xx_gmu_power_config(struct a6xx_gmu * gmu)6384b565ca5SJordan Crouse static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
6394b565ca5SJordan Crouse {
640c6ed04f8SJonathan Marek /* Disable GMU WB/RB buffer */
641c6ed04f8SJonathan Marek gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
6424b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
6434b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
6444b565ca5SJordan Crouse
6454b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
6464b565ca5SJordan Crouse
6474b565ca5SJordan Crouse switch (gmu->idle_level) {
6484b565ca5SJordan Crouse case GMU_IDLE_STATE_IFPC:
6494b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
6504b565ca5SJordan Crouse GMU_PWR_COL_HYST);
6514b565ca5SJordan Crouse gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
652df561f66SGustavo A. R. Silva A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
6534b565ca5SJordan Crouse A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
6544b565ca5SJordan Crouse fallthrough;
6554b565ca5SJordan Crouse case GMU_IDLE_STATE_SPTP:
6564b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
6574b565ca5SJordan Crouse GMU_PWR_COL_HYST);
6584b565ca5SJordan Crouse gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
6594b565ca5SJordan Crouse A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
6604b565ca5SJordan Crouse A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
6614b565ca5SJordan Crouse }
6624b565ca5SJordan Crouse
6634b565ca5SJordan Crouse /* Enable RPMh GPU client */
6644b565ca5SJordan Crouse gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
6654b565ca5SJordan Crouse A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
6664b565ca5SJordan Crouse A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
6674b565ca5SJordan Crouse A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
6684b565ca5SJordan Crouse A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
6694b565ca5SJordan Crouse A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
6704b565ca5SJordan Crouse A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
671c6ed04f8SJonathan Marek }
672c6ed04f8SJonathan Marek
673c6ed04f8SJonathan Marek struct block_header {
674c6ed04f8SJonathan Marek u32 addr;
675c6ed04f8SJonathan Marek u32 size;
676c6ed04f8SJonathan Marek u32 type;
677c6ed04f8SJonathan Marek u32 value;
678c6ed04f8SJonathan Marek u32 data[];
679c6ed04f8SJonathan Marek };
680c6ed04f8SJonathan Marek
fw_block_mem(struct a6xx_gmu_bo * bo,const struct block_header * blk)681c6ed04f8SJonathan Marek static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
682c6ed04f8SJonathan Marek {
683c6ed04f8SJonathan Marek if (!in_range(blk->addr, bo->iova, bo->size))
684c6ed04f8SJonathan Marek return false;
685c6ed04f8SJonathan Marek
686c6ed04f8SJonathan Marek memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
687c6ed04f8SJonathan Marek return true;
688c6ed04f8SJonathan Marek }
689c6ed04f8SJonathan Marek
a6xx_gmu_fw_load(struct a6xx_gmu * gmu)690c6ed04f8SJonathan Marek static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
691c6ed04f8SJonathan Marek {
692c6ed04f8SJonathan Marek struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
693c6ed04f8SJonathan Marek struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
694c6ed04f8SJonathan Marek const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
695c6ed04f8SJonathan Marek const struct block_header *blk;
696c6ed04f8SJonathan Marek u32 reg_offset;
697c6ed04f8SJonathan Marek
698c6ed04f8SJonathan Marek u32 itcm_base = 0x00000000;
699f6d62d09SJonathan Marek u32 dtcm_base = 0x00040000;
700c6ed04f8SJonathan Marek
701c6ed04f8SJonathan Marek if (adreno_is_a650_family(adreno_gpu))
702c6ed04f8SJonathan Marek dtcm_base = 0x10004000;
703c6ed04f8SJonathan Marek
704c6ed04f8SJonathan Marek if (gmu->legacy) {
705c6ed04f8SJonathan Marek /* Sanity check the size of the firmware that was loaded */
706c6ed04f8SJonathan Marek if (fw_image->size > 0x8000) {
707c6ed04f8SJonathan Marek DRM_DEV_ERROR(gmu->dev,
708c6ed04f8SJonathan Marek "GMU firmware is bigger than the available region\n");
709c6ed04f8SJonathan Marek return -EINVAL;
710c6ed04f8SJonathan Marek }
711c6ed04f8SJonathan Marek
712c6ed04f8SJonathan Marek gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
713c6ed04f8SJonathan Marek (u32*) fw_image->data, fw_image->size);
714c6ed04f8SJonathan Marek return 0;
715c6ed04f8SJonathan Marek }
716c6ed04f8SJonathan Marek
717c6ed04f8SJonathan Marek
718c6ed04f8SJonathan Marek for (blk = (const struct block_header *) fw_image->data;
719c6ed04f8SJonathan Marek (const u8*) blk < fw_image->data + fw_image->size;
720c6ed04f8SJonathan Marek blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
721c6ed04f8SJonathan Marek if (blk->size == 0)
722c6ed04f8SJonathan Marek continue;
723c6ed04f8SJonathan Marek
724c6ed04f8SJonathan Marek if (in_range(blk->addr, itcm_base, SZ_16K)) {
725c6ed04f8SJonathan Marek reg_offset = (blk->addr - itcm_base) >> 2;
726c6ed04f8SJonathan Marek gmu_write_bulk(gmu,
727c6ed04f8SJonathan Marek REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
728c6ed04f8SJonathan Marek blk->data, blk->size);
729c6ed04f8SJonathan Marek } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
730c6ed04f8SJonathan Marek reg_offset = (blk->addr - dtcm_base) >> 2;
731c6ed04f8SJonathan Marek gmu_write_bulk(gmu,
732c6ed04f8SJonathan Marek REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
733c6ed04f8SJonathan Marek blk->data, blk->size);
734c6ed04f8SJonathan Marek } else if (!fw_block_mem(&gmu->icache, blk) &&
735c6ed04f8SJonathan Marek !fw_block_mem(&gmu->dcache, blk) &&
736c6ed04f8SJonathan Marek !fw_block_mem(&gmu->dummy, blk)) {
737c6ed04f8SJonathan Marek DRM_DEV_ERROR(gmu->dev,
738c6ed04f8SJonathan Marek "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
739c6ed04f8SJonathan Marek blk->addr, blk->size, blk->data[0]);
740c6ed04f8SJonathan Marek }
741c6ed04f8SJonathan Marek }
742c6ed04f8SJonathan Marek
743c6ed04f8SJonathan Marek return 0;
7444b565ca5SJordan Crouse }
7454b565ca5SJordan Crouse
a6xx_gmu_fw_start(struct a6xx_gmu * gmu,unsigned int state)7464b565ca5SJordan Crouse static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
7474b565ca5SJordan Crouse {
748c6ed04f8SJonathan Marek struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
7494b565ca5SJordan Crouse struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
750c6ed04f8SJonathan Marek int ret;
751f6d62d09SJonathan Marek u32 chipid;
75258e933e3SJonathan Marek
753c6ed04f8SJonathan Marek if (adreno_is_a650_family(adreno_gpu)) {
75458e933e3SJonathan Marek gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
7554b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
7564b565ca5SJordan Crouse }
7574b565ca5SJordan Crouse
7584b565ca5SJordan Crouse if (state == GMU_WARM_BOOT) {
7594b565ca5SJordan Crouse ret = a6xx_rpmh_start(gmu);
7604b565ca5SJordan Crouse if (ret)
7614b565ca5SJordan Crouse return ret;
7624b565ca5SJordan Crouse } else {
7634b565ca5SJordan Crouse if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
7644b565ca5SJordan Crouse "GMU firmware is not loaded\n"))
7654b565ca5SJordan Crouse return -ENOENT;
7664b565ca5SJordan Crouse
7674b565ca5SJordan Crouse /* Turn on register retention */
7684b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
7694b565ca5SJordan Crouse
7704b565ca5SJordan Crouse ret = a6xx_rpmh_start(gmu);
7714b565ca5SJordan Crouse if (ret)
772c6ed04f8SJonathan Marek return ret;
773c6ed04f8SJonathan Marek
774c6ed04f8SJonathan Marek ret = a6xx_gmu_fw_load(gmu);
7754b565ca5SJordan Crouse if (ret)
7764b565ca5SJordan Crouse return ret;
7774b565ca5SJordan Crouse }
7784b565ca5SJordan Crouse
7794b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
7804b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
78129ac8979SJonathan Marek
7824b565ca5SJordan Crouse /* Write the iova of the HFI table */
7834b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
7844b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
7854b565ca5SJordan Crouse
7864b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
7874b565ca5SJordan Crouse (1 << 31) | (0xa << 18) | (0xa0));
7884b565ca5SJordan Crouse
7894b565ca5SJordan Crouse /*
7904b565ca5SJordan Crouse * Snapshots toggle the NMI bit which will result in a jump to the NMI
7914b565ca5SJordan Crouse * handler instead of __main. Set the M3 config value to avoid that.
7924b565ca5SJordan Crouse */
7934b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_CM3_CFG, 0x4052);
794ad4968d5SJonathan Marek
795ad4968d5SJonathan Marek /*
796ad4968d5SJonathan Marek * Note that the GMU has a slightly different layout for
7974b565ca5SJordan Crouse * chip_id, for whatever reason, so a bit of massaging
7984b565ca5SJordan Crouse * is needed. The upper 16b are the same, but minor and
7994b565ca5SJordan Crouse * patchid are packed in four bits each with the lower
8004b565ca5SJordan Crouse * 8b unused:
8014b565ca5SJordan Crouse */
8024b565ca5SJordan Crouse chipid = adreno_gpu->chip_id & 0xffff0000;
8034b565ca5SJordan Crouse chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */
8048167e6faSJonathan Marek chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */
8054b565ca5SJordan Crouse
8064b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
8074b565ca5SJordan Crouse
8088167e6faSJonathan Marek gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
8094b565ca5SJordan Crouse gmu->log.iova | (gmu->log.size / SZ_4K - 1));
8104b565ca5SJordan Crouse
8114b565ca5SJordan Crouse /* Set up the lowest idle level on the GMU */
8124b565ca5SJordan Crouse a6xx_gmu_power_config(gmu);
8134b565ca5SJordan Crouse
8144b565ca5SJordan Crouse ret = a6xx_gmu_start(gmu);
8154b565ca5SJordan Crouse if (ret)
8164b565ca5SJordan Crouse return ret;
8174b565ca5SJordan Crouse
8184b565ca5SJordan Crouse if (gmu->legacy) {
8194b565ca5SJordan Crouse ret = a6xx_gmu_gfx_rail_on(gmu);
8204b565ca5SJordan Crouse if (ret)
8214b565ca5SJordan Crouse return ret;
8224b565ca5SJordan Crouse }
8234b565ca5SJordan Crouse
8244b565ca5SJordan Crouse /* Enable SPTP_PC if the CPU is responsible for it */
8254b565ca5SJordan Crouse if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
8264b565ca5SJordan Crouse ret = a6xx_sptprac_enable(gmu);
8274b565ca5SJordan Crouse if (ret)
828df0dff13SJordan Crouse return ret;
8294b565ca5SJordan Crouse }
8304b565ca5SJordan Crouse
8314b565ca5SJordan Crouse ret = a6xx_gmu_hfi_start(gmu);
8324b565ca5SJordan Crouse if (ret)
8334b565ca5SJordan Crouse return ret;
8344b565ca5SJordan Crouse
8354b565ca5SJordan Crouse /* FIXME: Do we need this wmb() here? */
8364b565ca5SJordan Crouse wmb();
8374b565ca5SJordan Crouse
8384b565ca5SJordan Crouse return 0;
8394b565ca5SJordan Crouse }
8404b565ca5SJordan Crouse
8414b565ca5SJordan Crouse #define A6XX_HFI_IRQ_MASK \
8424b565ca5SJordan Crouse (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
8434b565ca5SJordan Crouse
84441570b74SJordan Crouse #define A6XX_GMU_IRQ_MASK \
8454b565ca5SJordan Crouse (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
8464b565ca5SJordan Crouse A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
8474b565ca5SJordan Crouse A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
8484b565ca5SJordan Crouse
a6xx_gmu_irq_disable(struct a6xx_gmu * gmu)84902ef80c5SJonathan Marek static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
8504b565ca5SJordan Crouse {
85102ef80c5SJonathan Marek disable_irq(gmu->gmu_irq);
8524b565ca5SJordan Crouse disable_irq(gmu->hfi_irq);
85302ef80c5SJonathan Marek
8544b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
85502ef80c5SJonathan Marek gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
8564b565ca5SJordan Crouse }
8574b565ca5SJordan Crouse
a6xx_gmu_rpmh_off(struct a6xx_gmu * gmu)8584b565ca5SJordan Crouse static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
85941570b74SJordan Crouse {
86041570b74SJordan Crouse u32 val;
86141570b74SJordan Crouse
8623a9dd708SAkhil P Oommen /* Make sure there are no outstanding RPMh votes */
8633a9dd708SAkhil P Oommen gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
8643a9dd708SAkhil P Oommen (val & 1), 100, 10000);
8653a9dd708SAkhil P Oommen gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
866ce8f1381SKonrad Dybcio (val & 1), 100, 10000);
867ce8f1381SKonrad Dybcio gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
868ce8f1381SKonrad Dybcio (val & 1), 100, 10000);
869ce8f1381SKonrad Dybcio gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
870ce8f1381SKonrad Dybcio (val & 1), 100, 1000);
871ce8f1381SKonrad Dybcio }
87241570b74SJordan Crouse
87341570b74SJordan Crouse /* Force the GMU off in case it isn't responsive */
a6xx_gmu_force_off(struct a6xx_gmu * gmu)87441570b74SJordan Crouse static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
87541570b74SJordan Crouse {
87641570b74SJordan Crouse struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
87741570b74SJordan Crouse struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
87841570b74SJordan Crouse struct msm_gpu *gpu = &adreno_gpu->base;
87941570b74SJordan Crouse
88041570b74SJordan Crouse /*
88141570b74SJordan Crouse * Turn off keep alive that might have been enabled by the hang
88241570b74SJordan Crouse * interrupt
8833a9dd708SAkhil P Oommen */
8843a9dd708SAkhil P Oommen gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
8853a9dd708SAkhil P Oommen
8863a9dd708SAkhil P Oommen /* Flush all the queues */
887f4a75b59SAkhil P Oommen a6xx_hfi_stop(gmu);
8883a9dd708SAkhil P Oommen
8893a9dd708SAkhil P Oommen /* Stop the interrupts */
890277b9678SKonrad Dybcio a6xx_gmu_irq_disable(gmu);
89141570b74SJordan Crouse
89241570b74SJordan Crouse /* Force off SPTP in case the GMU is managing it */
8931f60d114SSharat Masetty a6xx_sptprac_disable(gmu);
8941f60d114SSharat Masetty
8951f60d114SSharat Masetty /* Make sure there are no outstanding RPMh votes */
8961f60d114SSharat Masetty a6xx_gmu_rpmh_off(gmu);
8971f60d114SSharat Masetty
8981f60d114SSharat Masetty /* Clear the WRITEDROPPED fields and put fence into allow mode */
89939b14bb5SWang Qing gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS_CLR, 0x7);
9001f60d114SSharat Masetty gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
9011f60d114SSharat Masetty
9025e0c22d4SJonathan Marek /* Make sure the above writes go through */
9036694482aSDouglas Anderson wmb();
9041f60d114SSharat Masetty
9051f60d114SSharat Masetty /* Halt the gmu cm3 core */
9061f60d114SSharat Masetty gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
90720925fe8SSharat Masetty
90820925fe8SSharat Masetty a6xx_bus_clear_pending_transactions(adreno_gpu, true);
90920925fe8SSharat Masetty
91020925fe8SSharat Masetty /* Reset GPU core blocks */
91120925fe8SSharat Masetty a6xx_gpu_sw_reset(gpu, true);
91220925fe8SSharat Masetty }
91339b14bb5SWang Qing
a6xx_gmu_set_initial_freq(struct msm_gpu * gpu,struct a6xx_gmu * gmu)91420925fe8SSharat Masetty static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
91520925fe8SSharat Masetty {
916920b4a67SViresh Kumar struct dev_pm_opp *gpu_opp;
91720925fe8SSharat Masetty unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
91820925fe8SSharat Masetty
91920925fe8SSharat Masetty gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
9204b565ca5SJordan Crouse if (IS_ERR(gpu_opp))
9214b565ca5SJordan Crouse return;
922fcf9d0b7SJordan Crouse
923fcf9d0b7SJordan Crouse gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
9244b565ca5SJordan Crouse a6xx_gmu_set_freq(gpu, gpu_opp, false);
9254b565ca5SJordan Crouse dev_pm_opp_put(gpu_opp);
9264b565ca5SJordan Crouse }
927606ec90fSSean Paul
a6xx_gmu_set_initial_bw(struct msm_gpu * gpu,struct a6xx_gmu * gmu)9284cd15a3eSDouglas Anderson static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
9294b565ca5SJordan Crouse {
930e31fdb74SJordan Crouse struct dev_pm_opp *gpu_opp;
931e31fdb74SJordan Crouse unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
9324b565ca5SJordan Crouse
9334b565ca5SJordan Crouse gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
9344b565ca5SJordan Crouse if (IS_ERR(gpu_opp))
93557c0bd51SAkhil P Oommen return;
93657c0bd51SAkhil P Oommen
93757c0bd51SAkhil P Oommen dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
93857c0bd51SAkhil P Oommen dev_pm_opp_put(gpu_opp);
93957c0bd51SAkhil P Oommen }
94057c0bd51SAkhil P Oommen
a6xx_gmu_resume(struct a6xx_gpu * a6xx_gpu)94157c0bd51SAkhil P Oommen int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
94257c0bd51SAkhil P Oommen {
9434b565ca5SJordan Crouse struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
9444b565ca5SJordan Crouse struct msm_gpu *gpu = &adreno_gpu->base;
945192f4ee3SAkhil P Oommen struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
9464b565ca5SJordan Crouse int status, ret;
94741570b74SJordan Crouse
94857c0bd51SAkhil P Oommen if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
94941570b74SJordan Crouse return -EINVAL;
95041570b74SJordan Crouse
95141570b74SJordan Crouse gmu->hung = false;
9524b565ca5SJordan Crouse
953fcf9d0b7SJordan Crouse /* Turn on the resources */
95420925fe8SSharat Masetty pm_runtime_get_sync(gmu->dev);
955fcf9d0b7SJordan Crouse
95641570b74SJordan Crouse /*
95741570b74SJordan Crouse * "enable" the GX power domain which won't actually do anything but it
95841570b74SJordan Crouse * will make sure that the refcounting is correct in case we need to
95941570b74SJordan Crouse * bring down the GX after a GMU failure
9604b565ca5SJordan Crouse */
9614b565ca5SJordan Crouse if (!IS_ERR_OR_NULL(gmu->gxpd))
9624b565ca5SJordan Crouse pm_runtime_get_sync(gmu->gxpd);
9634b565ca5SJordan Crouse
9644b565ca5SJordan Crouse /* Use a known rate to bring up the GMU */
965c6ed04f8SJonathan Marek clk_set_rate(gmu->core_clk, 200000000);
966c6ed04f8SJonathan Marek clk_set_rate(gmu->hub_clk, 150000000);
967c6ed04f8SJonathan Marek ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
968c6ed04f8SJonathan Marek if (ret) {
969c6ed04f8SJonathan Marek pm_runtime_put(gmu->gxpd);
970c6ed04f8SJonathan Marek pm_runtime_put(gmu->dev);
971c6ed04f8SJonathan Marek return ret;
9724b565ca5SJordan Crouse }
9734b565ca5SJordan Crouse
9744b565ca5SJordan Crouse /* Set the bus quota to a reasonable value for boot */
9754b565ca5SJordan Crouse a6xx_gmu_set_initial_bw(gpu, gmu);
9764b565ca5SJordan Crouse
97741570b74SJordan Crouse /* Enable the GMU interrupt */
97841570b74SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
97941570b74SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
98041570b74SJordan Crouse enable_irq(gmu->gmu_irq);
98141570b74SJordan Crouse
98241570b74SJordan Crouse /* Check to see if we are doing a cold or warm boot */
98341570b74SJordan Crouse status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
98441570b74SJordan Crouse GMU_WARM_BOOT : GMU_COLD_BOOT;
98541570b74SJordan Crouse
98641570b74SJordan Crouse /*
9874b565ca5SJordan Crouse * Warm boot path does not work on newer GPUs
988bd3fe811SRob Clark * Presumably this is because icache/dcache regions must be restored
9891f60d114SSharat Masetty */
9904b565ca5SJordan Crouse if (!gmu->legacy)
9914b565ca5SJordan Crouse status = GMU_COLD_BOOT;
99241570b74SJordan Crouse
99341570b74SJordan Crouse ret = a6xx_gmu_fw_start(gmu, status);
99441570b74SJordan Crouse if (ret)
99541570b74SJordan Crouse goto out;
99657c0bd51SAkhil P Oommen
99741570b74SJordan Crouse ret = a6xx_hfi_start(gmu, status);
99841570b74SJordan Crouse if (ret)
9994b565ca5SJordan Crouse goto out;
10004b565ca5SJordan Crouse
10014b565ca5SJordan Crouse /*
10024b565ca5SJordan Crouse * Turn on the GMU firmware fault interrupt after we know the boot
10034b565ca5SJordan Crouse * sequence is successful
10044b565ca5SJordan Crouse */
10054b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
10064b565ca5SJordan Crouse gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
1007606ec90fSSean Paul enable_irq(gmu->hfi_irq);
10084b565ca5SJordan Crouse
10094b565ca5SJordan Crouse /* Set the GPU to the current freq */
10104b565ca5SJordan Crouse a6xx_gmu_set_initial_freq(gpu, gmu);
10114b565ca5SJordan Crouse
10124b565ca5SJordan Crouse out:
10134b565ca5SJordan Crouse /* On failure, shut down the GMU to leave it in a good state */
10144b565ca5SJordan Crouse if (ret) {
10154b565ca5SJordan Crouse disable_irq(gmu->gmu_irq);
10164b565ca5SJordan Crouse a6xx_rpmh_stop(gmu);
10174b565ca5SJordan Crouse pm_runtime_put(gmu->gxpd);
1018e31fdb74SJordan Crouse pm_runtime_put(gmu->dev);
1019e31fdb74SJordan Crouse }
10204b565ca5SJordan Crouse
102141570b74SJordan Crouse return ret;
102241570b74SJordan Crouse }
10234b565ca5SJordan Crouse
a6xx_gmu_isidle(struct a6xx_gmu * gmu)10244b565ca5SJordan Crouse bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
10254b565ca5SJordan Crouse {
10264b565ca5SJordan Crouse u32 reg;
10274b565ca5SJordan Crouse
10284b565ca5SJordan Crouse if (!gmu->initialized)
10294b565ca5SJordan Crouse return true;
10304b565ca5SJordan Crouse
10314b565ca5SJordan Crouse reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
1032e31fdb74SJordan Crouse
10334b565ca5SJordan Crouse if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
1034e31fdb74SJordan Crouse return false;
1035e31fdb74SJordan Crouse
1036e31fdb74SJordan Crouse return true;
1037e31fdb74SJordan Crouse }
1038e31fdb74SJordan Crouse
10394b565ca5SJordan Crouse /* Gracefully try to shut down the GMU and by extension the GPU */
a6xx_gmu_shutdown(struct a6xx_gmu * gmu)1040f4a75b59SAkhil P Oommen static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
104141570b74SJordan Crouse {
10424b565ca5SJordan Crouse struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1043d6463fd4SAkhil P Oommen struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1044d6463fd4SAkhil P Oommen u32 val;
1045d6463fd4SAkhil P Oommen
1046d6463fd4SAkhil P Oommen /*
1047d6463fd4SAkhil P Oommen * The GMU may still be in slumber unless the GPU started so check and
10484b565ca5SJordan Crouse * skip putting it back into slumber if so
10494b565ca5SJordan Crouse */
10504b565ca5SJordan Crouse val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
10514b565ca5SJordan Crouse
10524b565ca5SJordan Crouse if (val != 0xf) {
10534b565ca5SJordan Crouse int ret = a6xx_gmu_wait_for_idle(gmu);
10544b565ca5SJordan Crouse
10554b565ca5SJordan Crouse /* If the GMU isn't responding assume it is hung */
10564b565ca5SJordan Crouse if (ret) {
10574b565ca5SJordan Crouse a6xx_gmu_force_off(gmu);
10584b565ca5SJordan Crouse return;
10594b565ca5SJordan Crouse }
10606a41da17SMamta Shukla
10614b565ca5SJordan Crouse a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung);
10624b565ca5SJordan Crouse
10634b565ca5SJordan Crouse /* tell the GMU we want to slumber */
10644b565ca5SJordan Crouse ret = a6xx_gmu_notify_slumber(gmu);
10654b565ca5SJordan Crouse if (ret) {
10664b565ca5SJordan Crouse a6xx_gmu_force_off(gmu);
10674b565ca5SJordan Crouse return;
10684b565ca5SJordan Crouse }
10694b565ca5SJordan Crouse
10704b565ca5SJordan Crouse ret = gmu_poll_timeout(gmu,
10714b565ca5SJordan Crouse REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
10724b565ca5SJordan Crouse !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
10734b565ca5SJordan Crouse 100, 10000);
10744b565ca5SJordan Crouse
10754b565ca5SJordan Crouse /*
1076e31fdb74SJordan Crouse * Let the user know we failed to slumber but don't worry too
1077e31fdb74SJordan Crouse * much because we are powering down anyway
1078e31fdb74SJordan Crouse */
1079e31fdb74SJordan Crouse
1080e31fdb74SJordan Crouse if (ret)
1081e31fdb74SJordan Crouse DRM_DEV_ERROR(gmu->dev,
1082e31fdb74SJordan Crouse "Unable to slumber GMU: status = 0%x/0%x\n",
1083e31fdb74SJordan Crouse gmu_read(gmu,
108441570b74SJordan Crouse REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
108541570b74SJordan Crouse gmu_read(gmu,
108641570b74SJordan Crouse REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1087e31fdb74SJordan Crouse }
1088e31fdb74SJordan Crouse
1089e31fdb74SJordan Crouse /* Turn off HFI */
1090e31fdb74SJordan Crouse a6xx_hfi_stop(gmu);
1091e31fdb74SJordan Crouse
1092e31fdb74SJordan Crouse /* Stop the interrupts and mask the hardware */
1093e31fdb74SJordan Crouse a6xx_gmu_irq_disable(gmu);
1094e31fdb74SJordan Crouse
10954b565ca5SJordan Crouse /* Tell RPMh to power off the GPU */
1096fcf9d0b7SJordan Crouse a6xx_rpmh_stop(gmu);
1097920b4a67SViresh Kumar }
1098fcf9d0b7SJordan Crouse
10999325d426SJordan Crouse
a6xx_gmu_stop(struct a6xx_gpu * a6xx_gpu)1100e31fdb74SJordan Crouse int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1101e31fdb74SJordan Crouse {
1102e31fdb74SJordan Crouse struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
11039325d426SJordan Crouse struct msm_gpu *gpu = &a6xx_gpu->base.base;
11042b117451SSean Paul
11059325d426SJordan Crouse if (!pm_runtime_active(gmu->dev))
11069325d426SJordan Crouse return 0;
11074b565ca5SJordan Crouse
11084b565ca5SJordan Crouse /*
11094b565ca5SJordan Crouse * Force the GMU off if we detected a hang, otherwise try to shut it
11104b565ca5SJordan Crouse * down gracefully
11114b565ca5SJordan Crouse */
11124b565ca5SJordan Crouse if (gmu->hung)
11134b565ca5SJordan Crouse a6xx_gmu_force_off(gmu);
111429ac8979SJonathan Marek else
11154b565ca5SJordan Crouse a6xx_gmu_shutdown(gmu);
1116030af2b0SRob Clark
1117030af2b0SRob Clark /* Remove the bus vote */
1118030af2b0SRob Clark dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1119030af2b0SRob Clark
1120030af2b0SRob Clark /*
1121030af2b0SRob Clark * Make sure the GX domain is off before turning off the GMU (CX)
11224b565ca5SJordan Crouse * domain. Usually the GMU does this but only if the shutdown sequence
112329ac8979SJonathan Marek * was successful
112429ac8979SJonathan Marek */
11254b565ca5SJordan Crouse if (!IS_ERR_OR_NULL(gmu->gxpd))
11264b565ca5SJordan Crouse pm_runtime_put_sync(gmu->gxpd);
112729ac8979SJonathan Marek
1128a630ac68SRob Clark clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
11294b565ca5SJordan Crouse
113029ac8979SJonathan Marek pm_runtime_put_sync(gmu->dev);
113129ac8979SJonathan Marek
113229ac8979SJonathan Marek return 0;
113329ac8979SJonathan Marek }
113429ac8979SJonathan Marek
a6xx_gmu_memory_free(struct a6xx_gmu * gmu)11354b565ca5SJordan Crouse static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
113629ac8979SJonathan Marek {
113729ac8979SJonathan Marek msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace);
113829ac8979SJonathan Marek msm_gem_kernel_put(gmu->debug.obj, gmu->aspace);
1139c6ed04f8SJonathan Marek msm_gem_kernel_put(gmu->icache.obj, gmu->aspace);
114029ac8979SJonathan Marek msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace);
114129ac8979SJonathan Marek msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace);
114229ac8979SJonathan Marek msm_gem_kernel_put(gmu->log.obj, gmu->aspace);
114329ac8979SJonathan Marek
114429ac8979SJonathan Marek gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1145c6ed04f8SJonathan Marek msm_gem_address_space_put(gmu->aspace);
1146c6ed04f8SJonathan Marek }
11474b565ca5SJordan Crouse
a6xx_gmu_memory_alloc(struct a6xx_gmu * gmu,struct a6xx_gmu_bo * bo,size_t size,u64 iova,const char * name)11484b565ca5SJordan Crouse static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
114929ac8979SJonathan Marek size_t size, u64 iova, const char *name)
115029ac8979SJonathan Marek {
115129ac8979SJonathan Marek struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
115229ac8979SJonathan Marek struct drm_device *dev = a6xx_gpu->base.base.dev;
115329ac8979SJonathan Marek uint32_t flags = MSM_BO_WC;
11542ee4b5d2SRob Clark u64 range_start, range_end;
115529ac8979SJonathan Marek int ret;
115629ac8979SJonathan Marek
115729ac8979SJonathan Marek size = PAGE_ALIGN(size);
115829ac8979SJonathan Marek if (!iova) {
115929ac8979SJonathan Marek /* no fixed address - use GMU's uncached range */
116029ac8979SJonathan Marek range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
116129ac8979SJonathan Marek range_end = 0x80000000;
116229ac8979SJonathan Marek } else {
1163a630ac68SRob Clark /* range for fixed address */
1164a630ac68SRob Clark range_start = iova;
116529ac8979SJonathan Marek range_end = iova + size;
116629ac8979SJonathan Marek /* use IOMMU_PRIV for icache/dcache */
116729ac8979SJonathan Marek flags |= MSM_BO_MAP_PRIV;
116829ac8979SJonathan Marek }
116929ac8979SJonathan Marek
1170ccac7ce3SJordan Crouse bo->obj = msm_gem_new(dev, size, flags);
117129ac8979SJonathan Marek if (IS_ERR(bo->obj))
11723236130bSDmitry Baryshkov return PTR_ERR(bo->obj);
11733236130bSDmitry Baryshkov
117429ac8979SJonathan Marek ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
11753236130bSDmitry Baryshkov range_start, range_end);
11763236130bSDmitry Baryshkov if (ret) {
117729ac8979SJonathan Marek drm_gem_object_put(bo->obj);
117830480e6eSJordan Crouse return ret;
11793236130bSDmitry Baryshkov }
118029ac8979SJonathan Marek
118129ac8979SJonathan Marek bo->virt = msm_gem_get_vaddr(bo->obj);
118229ac8979SJonathan Marek bo->size = size;
11834b565ca5SJordan Crouse
11844b565ca5SJordan Crouse msm_gem_object_set_name(bo->obj, name);
11854b565ca5SJordan Crouse
1186e1505f62SDouglas Anderson return 0;
1187e1505f62SDouglas Anderson }
11884b565ca5SJordan Crouse
a6xx_gmu_memory_probe(struct a6xx_gmu * gmu)11894b565ca5SJordan Crouse static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1190e1505f62SDouglas Anderson {
11914b565ca5SJordan Crouse struct msm_mmu *mmu;
11924b565ca5SJordan Crouse
11934b565ca5SJordan Crouse mmu = msm_iommu_new(gmu->dev, 0);
11944b565ca5SJordan Crouse if (!mmu)
11954b565ca5SJordan Crouse return -ENODEV;
11964b565ca5SJordan Crouse if (IS_ERR(mmu))
11974b565ca5SJordan Crouse return PTR_ERR(mmu);
11984b565ca5SJordan Crouse
1199e1505f62SDouglas Anderson gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
12004b565ca5SJordan Crouse if (IS_ERR(gmu->aspace))
12014b565ca5SJordan Crouse return PTR_ERR(gmu->aspace);
12024b565ca5SJordan Crouse
12034b565ca5SJordan Crouse return 0;
12044b565ca5SJordan Crouse }
12054b565ca5SJordan Crouse
12064b565ca5SJordan Crouse /* Return the 'arc-level' for the given frequency */
a6xx_gmu_get_arc_level(struct device * dev,unsigned long freq)1207ed3cafa7SStephen Boyd static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
12084b565ca5SJordan Crouse unsigned long freq)
12094b565ca5SJordan Crouse {
1210ed3cafa7SStephen Boyd struct dev_pm_opp *opp;
1211ed3cafa7SStephen Boyd unsigned int val;
1212ed3cafa7SStephen Boyd
1213ed3cafa7SStephen Boyd if (!freq)
1214b601f731SStephen Boyd return 0;
1215b601f731SStephen Boyd
1216ed3cafa7SStephen Boyd opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1217ed3cafa7SStephen Boyd if (IS_ERR(opp))
1218ed3cafa7SStephen Boyd return 0;
1219ed3cafa7SStephen Boyd
1220ed3cafa7SStephen Boyd val = dev_pm_opp_get_level(opp);
1221ed3cafa7SStephen Boyd
1222ed3cafa7SStephen Boyd dev_pm_opp_put(opp);
1223ed3cafa7SStephen Boyd
1224ed3cafa7SStephen Boyd return val;
1225b601f731SStephen Boyd }
1226b601f731SStephen Boyd
a6xx_gmu_rpmh_arc_votes_init(struct device * dev,u32 * votes,unsigned long * freqs,int freqs_count,const char * id)1227b601f731SStephen Boyd static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1228ed3cafa7SStephen Boyd unsigned long *freqs, int freqs_count, const char *id)
1229ed3cafa7SStephen Boyd {
1230ed3cafa7SStephen Boyd int i, j;
12314b565ca5SJordan Crouse const u16 *pri, *sec;
12324b565ca5SJordan Crouse size_t pri_count, sec_count;
12334b565ca5SJordan Crouse
12344b565ca5SJordan Crouse pri = cmd_db_read_aux_data(id, &pri_count);
1235e1505f62SDouglas Anderson if (IS_ERR(pri))
12364b565ca5SJordan Crouse return PTR_ERR(pri);
12374b565ca5SJordan Crouse /*
12384b565ca5SJordan Crouse * The data comes back as an array of unsigned shorts so adjust the
12394b565ca5SJordan Crouse * count accordingly
12404b565ca5SJordan Crouse */
12414b565ca5SJordan Crouse pri_count >>= 1;
12424b565ca5SJordan Crouse if (!pri_count)
12434b565ca5SJordan Crouse return -EINVAL;
12444b565ca5SJordan Crouse
12454b565ca5SJordan Crouse sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
12466a41da17SMamta Shukla if (IS_ERR(sec))
124709b4138eSChristophe JAILLET return PTR_ERR(sec);
12484b565ca5SJordan Crouse
12496a41da17SMamta Shukla sec_count >>= 1;
12504b565ca5SJordan Crouse if (!sec_count)
12516a41da17SMamta Shukla return -EINVAL;
12524b565ca5SJordan Crouse
12534b565ca5SJordan Crouse /* Construct a vote for each frequency */
12544b565ca5SJordan Crouse for (i = 0; i < freqs_count; i++) {
12554b565ca5SJordan Crouse u8 pindex = 0, sindex = 0;
12564b565ca5SJordan Crouse unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
12574b565ca5SJordan Crouse
12584b565ca5SJordan Crouse /* Get the primary index that matches the arc level */
12594b565ca5SJordan Crouse for (j = 0; j < pri_count; j++) {
12604b565ca5SJordan Crouse if (pri[j] >= level) {
12614b565ca5SJordan Crouse pindex = j;
12624b565ca5SJordan Crouse break;
12634b565ca5SJordan Crouse }
12644b565ca5SJordan Crouse }
12654b565ca5SJordan Crouse
12664b565ca5SJordan Crouse if (j == pri_count) {
12674b565ca5SJordan Crouse DRM_DEV_ERROR(dev,
12684b565ca5SJordan Crouse "Level %u not found in the RPMh list\n",
12694b565ca5SJordan Crouse level);
12704b565ca5SJordan Crouse DRM_DEV_ERROR(dev, "Available levels:\n");
12714b565ca5SJordan Crouse for (j = 0; j < pri_count; j++)
12724b565ca5SJordan Crouse DRM_DEV_ERROR(dev, " %u\n", pri[j]);
12734b565ca5SJordan Crouse
12744b565ca5SJordan Crouse return -EINVAL;
12754b565ca5SJordan Crouse }
12764b565ca5SJordan Crouse
12774b565ca5SJordan Crouse /*
12784b565ca5SJordan Crouse * Look for a level in in the secondary list that matches. If
12794b565ca5SJordan Crouse * nothing fits, use the maximum non zero vote
12804b565ca5SJordan Crouse */
12814b565ca5SJordan Crouse
12824b565ca5SJordan Crouse for (j = 0; j < sec_count; j++) {
12834b565ca5SJordan Crouse if (sec[j] >= level) {
12844b565ca5SJordan Crouse sindex = j;
12854b565ca5SJordan Crouse break;
12864b565ca5SJordan Crouse } else if (sec[j]) {
12874b565ca5SJordan Crouse sindex = j;
12884b565ca5SJordan Crouse }
12894b565ca5SJordan Crouse }
12904b565ca5SJordan Crouse
12914b565ca5SJordan Crouse /* Construct the vote */
12924b565ca5SJordan Crouse votes[i] = ((pri[pindex] & 0xffff) << 16) |
1293ed3cafa7SStephen Boyd (sindex << 8) | pindex;
12944b565ca5SJordan Crouse }
12954b565ca5SJordan Crouse
12964b565ca5SJordan Crouse return 0;
1297ed3cafa7SStephen Boyd }
12984b565ca5SJordan Crouse
12994b565ca5SJordan Crouse /*
13004b565ca5SJordan Crouse * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
13014b565ca5SJordan Crouse * to construct the list of votes on the CPU and send it over. Query the RPMh
13024b565ca5SJordan Crouse * voltage levels and build the votes
13034b565ca5SJordan Crouse */
13044b565ca5SJordan Crouse
a6xx_gmu_rpmh_votes_init(struct a6xx_gmu * gmu)13054b565ca5SJordan Crouse static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
13064b565ca5SJordan Crouse {
13074b565ca5SJordan Crouse struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
13084b565ca5SJordan Crouse struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
13094b565ca5SJordan Crouse struct msm_gpu *gpu = &adreno_gpu->base;
13104b565ca5SJordan Crouse int ret;
13114b565ca5SJordan Crouse
13124b565ca5SJordan Crouse /* Build the GX votes */
13134b565ca5SJordan Crouse ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
13144b565ca5SJordan Crouse gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
13154b565ca5SJordan Crouse
13164b565ca5SJordan Crouse /* Build the CX votes */
13174b565ca5SJordan Crouse ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
13184b565ca5SJordan Crouse gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
13194b565ca5SJordan Crouse
13204b565ca5SJordan Crouse return ret;
13214b565ca5SJordan Crouse }
13224b565ca5SJordan Crouse
a6xx_gmu_build_freq_table(struct device * dev,unsigned long * freqs,u32 size)13234b565ca5SJordan Crouse static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
13244b565ca5SJordan Crouse u32 size)
13254b565ca5SJordan Crouse {
13264b565ca5SJordan Crouse int count = dev_pm_opp_get_opp_count(dev);
13274b565ca5SJordan Crouse struct dev_pm_opp *opp;
13284b565ca5SJordan Crouse int i, index = 0;
13294b565ca5SJordan Crouse unsigned long freq = 1;
13304b565ca5SJordan Crouse
13314b565ca5SJordan Crouse /*
13324b565ca5SJordan Crouse * The OPP table doesn't contain the "off" frequency level so we need to
13334b565ca5SJordan Crouse * add 1 to the table size to account for it
13344b565ca5SJordan Crouse */
13354b565ca5SJordan Crouse
13364b565ca5SJordan Crouse if (WARN(count + 1 > size,
13374b565ca5SJordan Crouse "The GMU frequency table is being truncated\n"))
13384b565ca5SJordan Crouse count = size - 1;
13394b565ca5SJordan Crouse
13404b565ca5SJordan Crouse /* Set the "off" frequency */
13414b565ca5SJordan Crouse freqs[index++] = 0;
13424b565ca5SJordan Crouse
13434b565ca5SJordan Crouse for (i = 0; i < count; i++) {
1344546907deSColin Ian King opp = dev_pm_opp_find_freq_ceil(dev, &freq);
13454b565ca5SJordan Crouse if (IS_ERR(opp))
134611120e93SYangtao Li break;
13474b565ca5SJordan Crouse
13486a41da17SMamta Shukla dev_pm_opp_put(opp);
13494b565ca5SJordan Crouse freqs[index++] = freq++;
13504b565ca5SJordan Crouse }
13514b565ca5SJordan Crouse
13524b565ca5SJordan Crouse return index;
13534b565ca5SJordan Crouse }
13544b565ca5SJordan Crouse
a6xx_gmu_pwrlevels_probe(struct a6xx_gmu * gmu)13554b565ca5SJordan Crouse static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
13564b565ca5SJordan Crouse {
13574b565ca5SJordan Crouse struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
13584b565ca5SJordan Crouse struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
13594b565ca5SJordan Crouse struct msm_gpu *gpu = &adreno_gpu->base;
13604b565ca5SJordan Crouse
13614b565ca5SJordan Crouse int ret = 0;
1362bd3fe811SRob Clark
1363bd3fe811SRob Clark /*
13644b565ca5SJordan Crouse * The GMU handles its own frequency switching so build a list of
13654b565ca5SJordan Crouse * available frequencies to send during initialization
13664b565ca5SJordan Crouse */
13674b565ca5SJordan Crouse ret = devm_pm_opp_of_add_table(gmu->dev);
13684b565ca5SJordan Crouse if (ret) {
13694b565ca5SJordan Crouse DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
13708e3e791dSJordan Crouse return ret;
13714b565ca5SJordan Crouse }
13724b565ca5SJordan Crouse
13734b565ca5SJordan Crouse gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
13744b565ca5SJordan Crouse gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
13754b565ca5SJordan Crouse
13764b565ca5SJordan Crouse /*
13774b565ca5SJordan Crouse * The GMU also handles GPU frequency switching so build a list
13784b565ca5SJordan Crouse * from the GPU OPP table
13794b565ca5SJordan Crouse */
1380192f4ee3SAkhil P Oommen gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1381192f4ee3SAkhil P Oommen gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1382192f4ee3SAkhil P Oommen
13834b565ca5SJordan Crouse gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
13844b565ca5SJordan Crouse
13854b565ca5SJordan Crouse /* Build the list of RPMh votes that we'll send to the GMU */
13864b565ca5SJordan Crouse return a6xx_gmu_rpmh_votes_init(gmu);
13874b565ca5SJordan Crouse }
13884b565ca5SJordan Crouse
a6xx_gmu_clocks_probe(struct a6xx_gmu * gmu)13894b565ca5SJordan Crouse static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
13904b565ca5SJordan Crouse {
13914b565ca5SJordan Crouse int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
13924b565ca5SJordan Crouse
13934b565ca5SJordan Crouse if (ret < 1)
13946a41da17SMamta Shukla return ret;
13954b565ca5SJordan Crouse
13964b565ca5SJordan Crouse gmu->nr_clocks = ret;
13974b565ca5SJordan Crouse
1398a62fb211SSean Paul gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
13994b565ca5SJordan Crouse gmu->nr_clocks, "gmu");
14006a41da17SMamta Shukla
14014b565ca5SJordan Crouse gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks,
14024b565ca5SJordan Crouse gmu->nr_clocks, "hub");
14034b565ca5SJordan Crouse
14044b565ca5SJordan Crouse return 0;
14054b565ca5SJordan Crouse }
14064b565ca5SJordan Crouse
a6xx_gmu_get_mmio(struct platform_device * pdev,const char * name)14074b565ca5SJordan Crouse static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
14084b565ca5SJordan Crouse const char *name)
14094b565ca5SJordan Crouse {
14104b565ca5SJordan Crouse void __iomem *ret;
14114b565ca5SJordan Crouse struct resource *res = platform_get_resource_byname(pdev,
14124b565ca5SJordan Crouse IORESOURCE_MEM, name);
14134b565ca5SJordan Crouse
1414a62fb211SSean Paul if (!res) {
14154b565ca5SJordan Crouse DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1416a62fb211SSean Paul return ERR_PTR(-EINVAL);
1417a62fb211SSean Paul }
14184b565ca5SJordan Crouse
14194b565ca5SJordan Crouse ret = ioremap(res->start, resource_size(res));
14204b565ca5SJordan Crouse if (!ret) {
14214b565ca5SJordan Crouse DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
14224b565ca5SJordan Crouse return ERR_PTR(-EINVAL);
14234b565ca5SJordan Crouse }
14244b565ca5SJordan Crouse
14254b565ca5SJordan Crouse return ret;
14264b565ca5SJordan Crouse }
14274b565ca5SJordan Crouse
a6xx_gmu_get_irq(struct a6xx_gmu * gmu,struct platform_device * pdev,const char * name,irq_handler_t handler)1428*5a903a44SKonrad Dybcio static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
14294b565ca5SJordan Crouse const char *name, irq_handler_t handler)
143002ef80c5SJonathan Marek {
14314b565ca5SJordan Crouse int irq, ret;
1432606ec90fSSean Paul
14334b565ca5SJordan Crouse irq = platform_get_irq_byname(pdev, name);
14344b565ca5SJordan Crouse
143503b7af1eSJordan Crouse ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
14369325d426SJordan Crouse if (ret) {
1437ead5d3e5SAkhil P Oommen DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1438ead5d3e5SAkhil P Oommen name, ret);
1439ead5d3e5SAkhil P Oommen return ret;
1440ead5d3e5SAkhil P Oommen }
1441ead5d3e5SAkhil P Oommen
1442ead5d3e5SAkhil P Oommen disable_irq(irq);
14432b117451SSean Paul
14449325d426SJordan Crouse return irq;
14459325d426SJordan Crouse }
14469325d426SJordan Crouse
a6xx_gmu_remove(struct a6xx_gpu * a6xx_gpu)14479325d426SJordan Crouse void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1448a62fb211SSean Paul {
144902ef80c5SJonathan Marek struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
145002ef80c5SJonathan Marek struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1451a62fb211SSean Paul struct platform_device *pdev = to_platform_device(gmu->dev);
145202ef80c5SJonathan Marek
1453a62fb211SSean Paul mutex_lock(&gmu->lock);
1454*5a903a44SKonrad Dybcio if (!gmu->initialized) {
145529ac8979SJonathan Marek mutex_unlock(&gmu->lock);
14564b565ca5SJordan Crouse return;
1457a62fb211SSean Paul }
1458a62fb211SSean Paul
1459*5a903a44SKonrad Dybcio gmu->initialized = false;
1460a62fb211SSean Paul
1461998efc74SSean Paul mutex_unlock(&gmu->lock);
1462998efc74SSean Paul
1463998efc74SSean Paul pm_runtime_force_suspend(gmu->dev);
1464606ec90fSSean Paul
14654b565ca5SJordan Crouse /*
14664b565ca5SJordan Crouse * Since cxpd is a virt device, the devlink with gmu-dev will be removed
1467c11fa120SAkhil P Oommen * automatically when we do detach
1468c11fa120SAkhil P Oommen */
1469c11fa120SAkhil P Oommen dev_pm_domain_detach(gmu->cxpd, false);
1470c11fa120SAkhil P Oommen
1471c11fa120SAkhil P Oommen if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1472c11fa120SAkhil P Oommen pm_runtime_disable(gmu->gxpd);
1473c11fa120SAkhil P Oommen dev_pm_domain_detach(gmu->gxpd, false);
1474c11fa120SAkhil P Oommen }
1475c11fa120SAkhil P Oommen
1476c11fa120SAkhil P Oommen iounmap(gmu->mmio);
1477c11fa120SAkhil P Oommen if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1478*5a903a44SKonrad Dybcio iounmap(gmu->rscc);
1479*5a903a44SKonrad Dybcio gmu->mmio = NULL;
1480*5a903a44SKonrad Dybcio gmu->rscc = NULL;
1481*5a903a44SKonrad Dybcio
1482*5a903a44SKonrad Dybcio if (!adreno_has_gmu_wrapper(adreno_gpu)) {
1483*5a903a44SKonrad Dybcio a6xx_gmu_memory_free(gmu);
1484*5a903a44SKonrad Dybcio
1485*5a903a44SKonrad Dybcio free_irq(gmu->gmu_irq, gmu);
1486*5a903a44SKonrad Dybcio free_irq(gmu->hfi_irq, gmu);
1487*5a903a44SKonrad Dybcio }
1488*5a903a44SKonrad Dybcio
1489*5a903a44SKonrad Dybcio /* Drop reference taken in of_find_device_by_node */
1490*5a903a44SKonrad Dybcio put_device(gmu->dev);
1491*5a903a44SKonrad Dybcio }
1492*5a903a44SKonrad Dybcio
cxpd_notifier_cb(struct notifier_block * nb,unsigned long action,void * data)1493*5a903a44SKonrad Dybcio static int cxpd_notifier_cb(struct notifier_block *nb,
1494*5a903a44SKonrad Dybcio unsigned long action, void *data)
1495*5a903a44SKonrad Dybcio {
1496*5a903a44SKonrad Dybcio struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb);
1497*5a903a44SKonrad Dybcio
1498*5a903a44SKonrad Dybcio if (action == GENPD_NOTIFY_OFF)
1499*5a903a44SKonrad Dybcio complete_all(&gmu->pd_gate);
1500*5a903a44SKonrad Dybcio
1501*5a903a44SKonrad Dybcio return 0;
1502*5a903a44SKonrad Dybcio }
1503*5a903a44SKonrad Dybcio
a6xx_gmu_wrapper_init(struct a6xx_gpu * a6xx_gpu,struct device_node * node)1504*5a903a44SKonrad Dybcio int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1505*5a903a44SKonrad Dybcio {
1506*5a903a44SKonrad Dybcio struct platform_device *pdev = of_find_device_by_node(node);
1507*5a903a44SKonrad Dybcio struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1508*5a903a44SKonrad Dybcio int ret;
1509*5a903a44SKonrad Dybcio
1510*5a903a44SKonrad Dybcio if (!pdev)
1511*5a903a44SKonrad Dybcio return -ENODEV;
1512*5a903a44SKonrad Dybcio
1513*5a903a44SKonrad Dybcio gmu->dev = &pdev->dev;
1514*5a903a44SKonrad Dybcio
1515*5a903a44SKonrad Dybcio of_dma_configure(gmu->dev, node, true);
1516*5a903a44SKonrad Dybcio
1517*5a903a44SKonrad Dybcio pm_runtime_enable(gmu->dev);
1518*5a903a44SKonrad Dybcio
1519*5a903a44SKonrad Dybcio /* Mark legacy for manual SPTPRAC control */
1520*5a903a44SKonrad Dybcio gmu->legacy = true;
1521*5a903a44SKonrad Dybcio
1522*5a903a44SKonrad Dybcio /* Map the GMU registers */
1523*5a903a44SKonrad Dybcio gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1524*5a903a44SKonrad Dybcio if (IS_ERR(gmu->mmio)) {
1525*5a903a44SKonrad Dybcio ret = PTR_ERR(gmu->mmio);
1526*5a903a44SKonrad Dybcio goto err_mmio;
1527*5a903a44SKonrad Dybcio }
1528*5a903a44SKonrad Dybcio
1529*5a903a44SKonrad Dybcio gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
1530*5a903a44SKonrad Dybcio if (IS_ERR(gmu->cxpd)) {
1531*5a903a44SKonrad Dybcio ret = PTR_ERR(gmu->cxpd);
1532*5a903a44SKonrad Dybcio goto err_mmio;
1533*5a903a44SKonrad Dybcio }
1534*5a903a44SKonrad Dybcio
1535*5a903a44SKonrad Dybcio if (!device_link_add(gmu->dev, gmu->cxpd, DL_FLAG_PM_RUNTIME)) {
1536*5a903a44SKonrad Dybcio ret = -ENODEV;
1537*5a903a44SKonrad Dybcio goto detach_cxpd;
1538*5a903a44SKonrad Dybcio }
1539*5a903a44SKonrad Dybcio
1540*5a903a44SKonrad Dybcio init_completion(&gmu->pd_gate);
1541981f2aabSSean Paul complete_all(&gmu->pd_gate);
15424b565ca5SJordan Crouse gmu->pd_nb.notifier_call = cxpd_notifier_cb;
15438167e6faSJonathan Marek
15444b565ca5SJordan Crouse /* Get a link to the GX power domain to reset the GPU */
15454b565ca5SJordan Crouse gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
15464b565ca5SJordan Crouse if (IS_ERR(gmu->gxpd)) {
15474b565ca5SJordan Crouse ret = PTR_ERR(gmu->gxpd);
15484b565ca5SJordan Crouse goto err_mmio;
15494b565ca5SJordan Crouse }
15504b565ca5SJordan Crouse
15514b565ca5SJordan Crouse gmu->initialized = true;
15524b565ca5SJordan Crouse
155329ac8979SJonathan Marek return 0;
15544b565ca5SJordan Crouse
15554b565ca5SJordan Crouse detach_cxpd:
15564b565ca5SJordan Crouse dev_pm_domain_detach(gmu->cxpd, false);
15574b565ca5SJordan Crouse
15584b565ca5SJordan Crouse err_mmio:
15594b565ca5SJordan Crouse iounmap(gmu->mmio);
15604b565ca5SJordan Crouse
15614b565ca5SJordan Crouse /* Drop reference taken in of_find_device_by_node */
15624b565ca5SJordan Crouse put_device(gmu->dev);
1563998efc74SSean Paul
15644b565ca5SJordan Crouse return ret;
156529ac8979SJonathan Marek }
156629ac8979SJonathan Marek
a6xx_gmu_init(struct a6xx_gpu * a6xx_gpu,struct device_node * node)156729ac8979SJonathan Marek int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
156829ac8979SJonathan Marek {
1569f6d62d09SJonathan Marek struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1570f6d62d09SJonathan Marek struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1571f6d62d09SJonathan Marek struct platform_device *pdev = of_find_device_by_node(node);
1572f6d62d09SJonathan Marek int ret;
1573f6d62d09SJonathan Marek
1574f6d62d09SJonathan Marek if (!pdev)
1575f6d62d09SJonathan Marek return -ENODEV;
1576f6d62d09SJonathan Marek
1577192f4ee3SAkhil P Oommen gmu->dev = &pdev->dev;
1578a630ac68SRob Clark
1579a630ac68SRob Clark of_dma_configure(gmu->dev, node, true);
1580c6ed04f8SJonathan Marek
1581c6ed04f8SJonathan Marek /* Fow now, don't do anything fancy until we get our feet under us */
1582c6ed04f8SJonathan Marek gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1583f6d62d09SJonathan Marek
1584f6d62d09SJonathan Marek pm_runtime_enable(gmu->dev);
1585f6d62d09SJonathan Marek
1586f6d62d09SJonathan Marek /* Get the list of clocks */
1587a630ac68SRob Clark ret = a6xx_gmu_clocks_probe(gmu);
1588a630ac68SRob Clark if (ret)
1589f6d62d09SJonathan Marek goto err_put_device;
1590f6d62d09SJonathan Marek
1591f6d62d09SJonathan Marek ret = a6xx_gmu_memory_probe(gmu);
1592f4f6dfdeSRob Clark if (ret)
1593f6d62d09SJonathan Marek goto err_put_device;
1594c6ed04f8SJonathan Marek
1595a630ac68SRob Clark
1596c6ed04f8SJonathan Marek /* A660 now requires handling "prealloc requests" in GMU firmware
1597c6ed04f8SJonathan Marek * For now just hardcode allocations based on the known firmware.
1598b7616b5cSKonrad Dybcio * note: there is no indication that these correspond to "dummy" or
1599b7616b5cSKonrad Dybcio * "debug" regions, but this "guess" allows reusing these BOs which
1600b7616b5cSKonrad Dybcio * are otherwise unused by a660.
1601b7616b5cSKonrad Dybcio */
1602b7616b5cSKonrad Dybcio gmu->dummy.size = SZ_4K;
1603b7616b5cSKonrad Dybcio if (adreno_is_a660_family(adreno_gpu)) {
1604083cc3a4SRob Clark ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7,
1605c6ed04f8SJonathan Marek 0x60400000, "debug");
1606a630ac68SRob Clark if (ret)
1607c6ed04f8SJonathan Marek goto err_memory;
1608c6ed04f8SJonathan Marek
1609c6ed04f8SJonathan Marek gmu->dummy.size = SZ_8K;
1610c6ed04f8SJonathan Marek }
1611a630ac68SRob Clark
1612c6ed04f8SJonathan Marek /* Allocate memory for the GMU dummy page */
1613c6ed04f8SJonathan Marek ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size,
1614b7616b5cSKonrad Dybcio 0x60000000, "dummy");
16158167e6faSJonathan Marek if (ret)
16168167e6faSJonathan Marek goto err_memory;
16174b565ca5SJordan Crouse
16184b565ca5SJordan Crouse /* Note that a650 family also includes a660 family: */
1619a630ac68SRob Clark if (adreno_is_a650_family(adreno_gpu)) {
162029ac8979SJonathan Marek ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1621a62fb211SSean Paul SZ_16M - SZ_16K, 0x04000, "icache");
16228167e6faSJonathan Marek if (ret)
16238167e6faSJonathan Marek goto err_memory;
16248167e6faSJonathan Marek /*
1625a630ac68SRob Clark * NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition
16268167e6faSJonathan Marek * to allocate icache/dcache here, as per downstream code flow, but it may not actually be
16278167e6faSJonathan Marek * necessary. If you omit this step and you don't get random pagefaults, you are likely
16284b565ca5SJordan Crouse * good to go without this!
1629ad4968d5SJonathan Marek */
1630a630ac68SRob Clark } else if (adreno_is_a640_family(adreno_gpu)) {
1631ad4968d5SJonathan Marek ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1632ad4968d5SJonathan Marek SZ_256K - SZ_16K, 0x04000, "icache");
1633ad4968d5SJonathan Marek if (ret)
16344b565ca5SJordan Crouse goto err_memory;
16354b565ca5SJordan Crouse
163629ac8979SJonathan Marek ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
163729ac8979SJonathan Marek SZ_256K - SZ_16K, 0x44000, "dcache");
1638a62fb211SSean Paul if (ret)
163929ac8979SJonathan Marek goto err_memory;
16404b565ca5SJordan Crouse } else if (adreno_is_a630_family(adreno_gpu)) {
1641f6d62d09SJonathan Marek /* HFI v1, has sptprac */
164202ef80c5SJonathan Marek gmu->legacy = true;
1643ead5d3e5SAkhil P Oommen
1644ead5d3e5SAkhil P Oommen /* Allocate memory for the GMU debug region */
164502ef80c5SJonathan Marek ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug");
1646ead5d3e5SAkhil P Oommen if (ret)
164702ef80c5SJonathan Marek goto err_memory;
164802ef80c5SJonathan Marek }
164902ef80c5SJonathan Marek
165002ef80c5SJonathan Marek /* Allocate memory for the GMU log region */
16514b565ca5SJordan Crouse ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_16K, 0, "log");
16524b565ca5SJordan Crouse if (ret)
16534b565ca5SJordan Crouse goto err_memory;
16544b565ca5SJordan Crouse
1655ead5d3e5SAkhil P Oommen /* Allocate memory for for the HFI queues */
1656ead5d3e5SAkhil P Oommen ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");
1657a62fb211SSean Paul if (ret)
1658ead5d3e5SAkhil P Oommen goto err_memory;
1659ead5d3e5SAkhil P Oommen
1660ead5d3e5SAkhil P Oommen /* Map the GMU registers */
1661ead5d3e5SAkhil P Oommen gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1662ead5d3e5SAkhil P Oommen if (IS_ERR(gmu->mmio)) {
1663ead5d3e5SAkhil P Oommen ret = PTR_ERR(gmu->mmio);
1664ead5d3e5SAkhil P Oommen goto err_memory;
1665ead5d3e5SAkhil P Oommen }
1666ead5d3e5SAkhil P Oommen
1667ead5d3e5SAkhil P Oommen if (adreno_is_a650_family(adreno_gpu)) {
1668ead5d3e5SAkhil P Oommen gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1669ead5d3e5SAkhil P Oommen if (IS_ERR(gmu->rscc)) {
1670ead5d3e5SAkhil P Oommen ret = -ENODEV;
16714b565ca5SJordan Crouse goto err_mmio;
1672c11fa120SAkhil P Oommen }
1673c11fa120SAkhil P Oommen } else {
1674c11fa120SAkhil P Oommen gmu->rscc = gmu->mmio + 0x23000;
1675c11fa120SAkhil P Oommen }
16769325d426SJordan Crouse
16779325d426SJordan Crouse /* Get the HFI and GMU interrupts */
16789325d426SJordan Crouse gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
16799325d426SJordan Crouse gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
16809325d426SJordan Crouse
16819325d426SJordan Crouse if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) {
16824b565ca5SJordan Crouse ret = -ENODEV;
16834b565ca5SJordan Crouse goto err_mmio;
16844b565ca5SJordan Crouse }
16854b565ca5SJordan Crouse
16864b565ca5SJordan Crouse gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
16874b565ca5SJordan Crouse if (IS_ERR(gmu->cxpd)) {
16888559da8fSRob Clark ret = PTR_ERR(gmu->cxpd);
16898559da8fSRob Clark goto err_mmio;
16908559da8fSRob Clark }
1691606ec90fSSean Paul
1692606ec90fSSean Paul if (!device_link_add(gmu->dev, gmu->cxpd,
16934b565ca5SJordan Crouse DL_FLAG_PM_RUNTIME)) {
1694a62fb211SSean Paul ret = -ENODEV;
1695ead5d3e5SAkhil P Oommen goto detach_cxpd;
1696ead5d3e5SAkhil P Oommen }
1697ead5d3e5SAkhil P Oommen
1698a62fb211SSean Paul init_completion(&gmu->pd_gate);
1699a62fb211SSean Paul complete_all(&gmu->pd_gate);
170002ef80c5SJonathan Marek gmu->pd_nb.notifier_call = cxpd_notifier_cb;
170102ef80c5SJonathan Marek
1702a62fb211SSean Paul /*
1703a62fb211SSean Paul * Get a link to the GX power domain to reset the GPU in case of GMU
17044b565ca5SJordan Crouse * crash
170529ac8979SJonathan Marek */
170629ac8979SJonathan Marek gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1707998efc74SSean Paul
1708998efc74SSean Paul /* Get the power levels for the GMU and GPU */
1709998efc74SSean Paul a6xx_gmu_pwrlevels_probe(gmu);
1710998efc74SSean Paul
1711998efc74SSean Paul /* Set up the HFI queues */
17124b565ca5SJordan Crouse a6xx_hfi_init(gmu);
1713
1714 /* Initialize RPMh */
1715 a6xx_gmu_rpmh_init(gmu);
1716
1717 gmu->initialized = true;
1718
1719 return 0;
1720
1721 detach_cxpd:
1722 dev_pm_domain_detach(gmu->cxpd, false);
1723
1724 err_mmio:
1725 iounmap(gmu->mmio);
1726 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1727 iounmap(gmu->rscc);
1728 free_irq(gmu->gmu_irq, gmu);
1729 free_irq(gmu->hfi_irq, gmu);
1730
1731 err_memory:
1732 a6xx_gmu_memory_free(gmu);
1733 err_put_device:
1734 /* Drop reference taken in of_find_device_by_node */
1735 put_device(gmu->dev);
1736
1737 return ret;
1738 }
1739