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Searched refs:clk_type (Results 1 – 25 of 51) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_services_types.h82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument
83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \
84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \
85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \
86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \
87 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \
88 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \
89 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \
91 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \
92 (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \
[all …]
H A Ddm_services.h192 enum dm_pp_clock_type clk_type,
197 enum dm_pp_clock_type clk_type,
202 enum dm_pp_clock_type clk_type,
/openbmc/linux/sound/soc/intel/skylake/
H A Dskl-ssp-clk.c59 switch (clk_type) { in skl_get_vbus_id()
84 if (clk_type == SKL_SCLK_FS) { in skl_fill_clk_ipc()
107 u32 vbus_id, u8 clk_type, in skl_send_clk_dma_control() argument
125 if (clk_type == SKL_SCLK_FS) { in skl_send_clk_dma_control()
132 if (clk_type == SKL_SCLK) in skl_send_clk_dma_control()
181 int vbus_id, clk_type; in skl_clk_change_status() local
184 if (clk_type < 0) in skl_clk_change_status()
185 return clk_type; in skl_clk_change_status()
219 int clk_type; in skl_clk_set_rate() local
230 if (clk_type < 0) in skl_clk_set_rate()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c592 switch (clk_type) { in smu_v13_0_5_get_current_clk_freq()
623 switch (clk_type) { in smu_v13_0_5_get_dpm_level_count()
656 switch (clk_type) { in smu_v13_0_5_get_dpm_freq_by_index()
695 switch (clk_type) { in smu_v13_0_5_clk_dpm_is_enabled()
730 switch (clk_type) { in smu_v13_0_5_get_dpm_ultimate_freq()
788 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v13_0_5_get_dpm_ultimate_freq()
818 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v13_0_5_get_dpm_ultimate_freq()
842 switch (clk_type) { in smu_v13_0_5_set_soft_freq_limited_range()
883 switch (clk_type) { in smu_v13_0_5_print_clk_levels()
958 switch (clk_type) { in smu_v13_0_5_force_clk_levels()
[all …]
H A Dsmu_v13_0_4_ppt.c394 switch (clk_type) { in smu_v13_0_4_get_current_clk_freq()
434 switch (clk_type) { in smu_v13_0_4_get_dpm_freq_by_index()
474 switch (clk_type) { in smu_v13_0_4_get_dpm_level_count()
506 switch (clk_type) { in smu_v13_0_4_print_clk_levels()
720 switch (clk_type) { in smu_v13_0_4_clk_dpm_is_enabled()
755 switch (clk_type) { in smu_v13_0_4_get_dpm_ultimate_freq()
812 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v13_0_4_get_dpm_ultimate_freq()
843 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in smu_v13_0_4_get_dpm_ultimate_freq()
866 switch (clk_type) { in smu_v13_0_4_set_soft_freq_limited_range()
913 switch (clk_type) { in smu_v13_0_4_force_clk_levels()
[all …]
H A Dyellow_carp_ppt.c723 switch (clk_type) { in yellow_carp_get_current_clk_freq()
757 switch (clk_type) { in yellow_carp_get_dpm_level_count()
790 switch (clk_type) { in yellow_carp_get_dpm_freq_by_index()
829 switch (clk_type) { in yellow_carp_clk_dpm_is_enabled()
922 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in yellow_carp_get_dpm_ultimate_freq()
952 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in yellow_carp_get_dpm_ultimate_freq()
977 switch (clk_type) { in yellow_carp_set_soft_freq_limited_range()
1024 switch (clk_type) { in yellow_carp_get_umd_pstate_clk_default()
1064 switch (clk_type) { in yellow_carp_print_clk_levels()
1140 switch (clk_type) { in yellow_carp_force_clk_levels()
[all …]
H A Dsmu_v13_0.c1089 switch (clk_type) { in smu_v13_0_display_clock_voltage_request()
1556 switch (clk_type) { in smu_v13_0_get_dpm_ultimate_freq()
1584 clk_type); in smu_v13_0_get_dpm_ultimate_freq()
1629 clk_type); in smu_v13_0_set_soft_freq_limited_range()
1669 clk_type); in smu_v13_0_set_hard_freq_limited_range()
1906 clk_type); in smu_v13_0_get_dpm_freq_by_index()
1925 enum smu_clk_type clk_type, in smu_v13_0_get_dpm_level_count() argument
1954 clk_type); in smu_v13_0_get_fine_grained_status()
1985 clk_type, in smu_v13_0_set_single_dpm_table()
1994 clk_type, in smu_v13_0_set_single_dpm_table()
[all …]
H A Dsmu_v13_0_6_ppt.c212 enum smu_clk_type clk_type; member
386 enum smu_clk_type clk_type, in smu_v13_0_6_get_dpm_ultimate_freq() argument
396 switch (clk_type) { in smu_v13_0_6_get_dpm_ultimate_freq()
436 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) { in smu_v13_0_6_get_dpm_ultimate_freq()
447 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) in smu_v13_0_6_get_dpm_ultimate_freq()
458 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK) in smu_v13_0_6_get_dpm_ultimate_freq()
471 enum smu_clk_type clk_type, in smu_v13_0_6_get_dpm_level_count() argument
751 enum smu_clk_type clk_type, in smu_v13_0_6_get_current_clk_freq_by_table() argument
759 switch (clk_type) { in smu_v13_0_6_get_current_clk_freq_by_table()
1477 enum smu_clk_type clk_type, in smu_v13_0_6_set_soft_freq_limited_range() argument
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-scu.h34 int num_parents, u32 rsrc_id, u8 clk_type);
38 u32 rsrc_id, u8 clk_type);
52 u8 clk_type) in imx_clk_scu() argument
54 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu()
58 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument
60 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
H A Dclk-scu.c31 u8 clk_type; member
50 u8 clk_type; member
241 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate()
332 msg.clk = clk->clk_type; in clk_scu_set_rate()
377 msg.clk = clk->clk_type; in clk_scu_set_parent()
481 clk->clk_type = clk_type; in __imx_clk_scu()
527 if (clk->clk_type == idx) in imx_scu_of_clk_src_get()
557 clk->rsrc, clk->clk_type); in imx_clk_scu_probe()
573 clk->clk_type); in imx_clk_scu_probe()
680 .clk_type = clk_type, in imx_clk_scu_alloc_dev()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c139 clk_type, in smu_set_soft_freq_range()
158 clk_type, in smu_get_dpm_freq_range()
391 enum smu_clk_type clk_type; in smu_restore_dpm_user_profile() local
393 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { in smu_restore_dpm_user_profile()
2054 enum smu_clk_type clk_type; in smu_force_ppclk_levels() local
2442 enum smu_clk_type clk_type; in smu_convert_to_smuclk() local
2481 return clk_type; in smu_convert_to_smuclk()
2796 clk_type = SMU_GFXCLK; in smu_get_clock_by_type_with_latency()
2799 clk_type = SMU_MCLK; in smu_get_clock_by_type_with_latency()
2802 clk_type = SMU_DCEFCLK; in smu_get_clock_by_type_with_latency()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c210 switch (clk_type) { in renoir_get_dpm_clk_limited()
290 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
325 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
353 switch (clk_type) { in renoir_get_dpm_ultimate_freq()
511 switch (clk_type) { in renoir_print_clk_levels()
587 switch (clk_type) { in renoir_print_clk_levels()
597 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i; in renoir_print_clk_levels()
697 enum smu_clk_type clk_type; in renoir_force_dpm_limit_value() local
706 clk_type = clks[i]; in renoir_force_dpm_limit_value()
739 clk_type = clk_feature_map[i].clk_type; in renoir_unforce_dpm_levels()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c548 switch (clk_type) { in vangogh_get_dpm_clk_limited()
601 switch (clk_type) { in vangogh_print_legacy_clk_levels()
656 switch (clk_type) { in vangogh_print_legacy_clk_levels()
704 switch (clk_type) { in vangogh_print_clk_levels()
766 switch (clk_type) { in vangogh_print_clk_levels()
893 switch (clk_type) { in vangogh_clk_dpm_is_enabled()
934 switch (clk_type) { in vangogh_get_dpm_ultimate_freq()
979 switch (clk_type) { in vangogh_get_dpm_ultimate_freq()
1124 switch (clk_type) { in vangogh_set_soft_freq_limited_range()
1206 switch (clk_type) { in vangogh_force_clk_levels()
[all …]
H A Dcyan_skillfish_ppt.c260 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument
265 switch (clk_type) { in cyan_skillfish_get_current_clk_freq()
291 enum smu_clk_type clk_type, in cyan_skillfish_print_clk_levels() argument
300 switch (clk_type) { in cyan_skillfish_print_clk_levels()
327 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
334 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
536 enum smu_clk_type clk_type, in cyan_skillfish_get_dpm_ultimate_freq() argument
543 switch (clk_type) { in cyan_skillfish_get_dpm_ultimate_freq()
550 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &low); in cyan_skillfish_get_dpm_ultimate_freq()
H A Dsmu_v11_0.c1063 switch (clk_type) { in smu_v11_0_display_clock_voltage_request()
1706 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq()
1734 clk_type); in smu_v11_0_get_dpm_ultimate_freq()
1770 clk_type); in smu_v11_0_set_soft_freq_limited_range()
1810 clk_type); in smu_v11_0_set_hard_freq_limited_range()
1967 clk_type); in smu_v11_0_get_dpm_freq_by_index()
1994 clk_type, in smu_v11_0_get_dpm_level_count()
2008 clk_type, in smu_v11_0_set_single_dpm_table()
2017 clk_type, in smu_v11_0_set_single_dpm_table()
2051 clk_type, in smu_v11_0_get_dpm_level_range()
[all …]
H A Dnavi10_ppt.c1185 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table() argument
1193 clk_type); in navi10_get_current_clk_freq_by_table()
1233 clk_type); in navi10_is_support_fine_grained_dpm()
1256 enum smu_clk_type clk_type, in navi10_emit_clk_levels() argument
1275 switch (clk_type) { in navi10_emit_clk_levels()
1296 clk_type, i, &value); in navi10_emit_clk_levels()
1311 clk_type, in navi10_emit_clk_levels()
1484 switch (clk_type) { in navi10_print_clk_levels()
1663 switch (clk_type) { in navi10_force_clk_levels()
1791 enum smu_clk_type clk_type, in navi10_get_clock_by_type_with_latency() argument
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/inc/
H A Dsmu_v11_0.h254 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
257 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
261 enum smu_clk_type clk_type,
272 enum smu_clk_type clk_type,
277 enum smu_clk_type clk_type,
281 enum smu_clk_type clk_type,
285 enum smu_clk_type clk_type,
H A Dsmu_v13_0.h225 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
228 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
232 enum smu_clk_type clk_type,
243 enum smu_clk_type clk_type,
247 enum smu_clk_type clk_type, uint16_t level,
H A Damdgpu_smu.h616 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf);
629 …int (*emit_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf, int *offset…
637 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask);
660 enum smu_clk_type clk_type,
1210 …int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, u…
1216 …int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t m…
1476 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
1479 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c111 enum dm_pp_clock_type clk_type, in get_default_clock_levels() argument
120 switch (clk_type) { in get_default_clock_levels()
294 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type() argument
303 dc_to_pp_clock_type(clk_type), &pp_clks)) { in dm_pp_get_clock_levels_by_type()
305 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type()
309 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); in dm_pp_get_clock_levels_by_type()
332 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { in dm_pp_get_clock_levels_by_type()
361 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency() argument
369 dc_to_pp_clock_type(clk_type), in dm_pp_get_clock_levels_by_type_with_latency()
381 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_voltage() argument
[all …]
/openbmc/u-boot/drivers/clk/at91/
H A Dclk-peripheral.c58 enum periph_clk_type clk_type; in periph_clk_enable() local
64 clk_type = dev_get_driver_data(dev_get_parent(clk->dev)); in periph_clk_enable()
65 if (clk_type == CLK_PERIPH_AT91RM9200) { in periph_clk_enable()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
H A Ddce120_clk_mgr.c98 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks()
113 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
/openbmc/linux/drivers/input/
H A Devdev.c49 enum input_clock_type clk_type; member
146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped()
177 enum input_clock_type clk_type; in evdev_set_clk_type() local
182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type()
185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type()
188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type()
194 if (client->clk_type != clk_type) { in evdev_set_clk_type()
195 client->clk_type = clk_type; in evdev_set_clk_type()
256 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
/openbmc/linux/drivers/phy/
H A Dphy-xgene.c706 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument
719 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
729 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type()
739 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type()
760 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument
806 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core()
1137 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument
1237 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument
1254 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument
1308 xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type); in xgene_phy_hw_init_sata()
[all …]
/openbmc/linux/drivers/nfc/s3fwrn5/
H A Dnci.h44 __u8 clk_type; member

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