1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2019 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan */
22e098bc96SEvan Quan
23e098bc96SEvan Quan #include <linux/firmware.h>
24e098bc96SEvan Quan #include <linux/module.h>
25e098bc96SEvan Quan #include <linux/pci.h>
26e098bc96SEvan Quan #include <linux/reboot.h>
27e098bc96SEvan Quan
28e098bc96SEvan Quan #define SMU_11_0_PARTIAL_PPTABLE
29e098bc96SEvan Quan #define SWSMU_CODE_LAYER_L3
30e098bc96SEvan Quan
31e098bc96SEvan Quan #include "amdgpu.h"
32e098bc96SEvan Quan #include "amdgpu_smu.h"
33e098bc96SEvan Quan #include "atomfirmware.h"
34e098bc96SEvan Quan #include "amdgpu_atomfirmware.h"
35e098bc96SEvan Quan #include "amdgpu_atombios.h"
36e098bc96SEvan Quan #include "smu_v11_0.h"
37e098bc96SEvan Quan #include "soc15_common.h"
38e098bc96SEvan Quan #include "atom.h"
39e098bc96SEvan Quan #include "amdgpu_ras.h"
40e098bc96SEvan Quan #include "smu_cmn.h"
41e098bc96SEvan Quan
42e098bc96SEvan Quan #include "asic_reg/thm/thm_11_0_2_offset.h"
43e098bc96SEvan Quan #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44e098bc96SEvan Quan #include "asic_reg/mp/mp_11_0_offset.h"
45e098bc96SEvan Quan #include "asic_reg/mp/mp_11_0_sh_mask.h"
46e098bc96SEvan Quan #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47e098bc96SEvan Quan #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48e098bc96SEvan Quan
49e098bc96SEvan Quan /*
50e098bc96SEvan Quan * DO NOT use these for err/warn/info/debug messages.
51e098bc96SEvan Quan * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52e098bc96SEvan Quan * They are more MGPU friendly.
53e098bc96SEvan Quan */
54e098bc96SEvan Quan #undef pr_err
55e098bc96SEvan Quan #undef pr_warn
56e098bc96SEvan Quan #undef pr_info
57e098bc96SEvan Quan #undef pr_debug
58e098bc96SEvan Quan
59e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64e098bc96SEvan Quan MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65db1f8a8fSTao Zhou MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
664d352669SChengming Gui MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
67e098bc96SEvan Quan
68e098bc96SEvan Quan #define SMU11_VOLTAGE_SCALE 4
69e098bc96SEvan Quan
70e098bc96SEvan Quan #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
71e098bc96SEvan Quan
72e098bc96SEvan Quan #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
73e098bc96SEvan Quan #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
74e098bc96SEvan Quan #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
75e098bc96SEvan Quan #define smnPCIE_LC_SPEED_CNTL 0x11140290
76e098bc96SEvan Quan #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
77e098bc96SEvan Quan #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
78e098bc96SEvan Quan
79e9995d4aSEvan Quan #define mmTHM_BACO_CNTL_ARCT 0xA7
80e9995d4aSEvan Quan #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
81e9995d4aSEvan Quan
smu_v11_0_poll_baco_exit(struct smu_context * smu)8286a3c691SGuchun Chen static void smu_v11_0_poll_baco_exit(struct smu_context *smu)
8386a3c691SGuchun Chen {
8486a3c691SGuchun Chen struct amdgpu_device *adev = smu->adev;
8586a3c691SGuchun Chen uint32_t data, loop = 0;
8686a3c691SGuchun Chen
8786a3c691SGuchun Chen do {
8886a3c691SGuchun Chen usleep_range(1000, 1100);
8986a3c691SGuchun Chen data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
9086a3c691SGuchun Chen } while ((data & 0x100) && (++loop < 100));
9186a3c691SGuchun Chen }
9286a3c691SGuchun Chen
smu_v11_0_init_microcode(struct smu_context * smu)93e098bc96SEvan Quan int smu_v11_0_init_microcode(struct smu_context *smu)
94e098bc96SEvan Quan {
95e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
966b544962SMario Limonciello char ucode_prefix[30];
9710e0d9ebSTao Zhou char fw_name[SMU_FW_NAME_LEN];
98e098bc96SEvan Quan int err = 0;
99e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr;
100e098bc96SEvan Quan const struct common_firmware_header *header;
101e098bc96SEvan Quan struct amdgpu_firmware_info *ucode = NULL;
102e098bc96SEvan Quan
10386b6037fSStanley.Yang if (amdgpu_sriov_vf(adev) &&
1041d789535SAlex Deucher ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) ||
1051d789535SAlex Deucher (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7))))
10686b6037fSStanley.Yang return 0;
10786b6037fSStanley.Yang
1086b544962SMario Limonciello amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
109e098bc96SEvan Quan
1106b544962SMario Limonciello snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
111e098bc96SEvan Quan
112315d1716SMario Limonciello err = amdgpu_ucode_request(adev, &adev->pm.fw, fw_name);
113e098bc96SEvan Quan if (err)
114e098bc96SEvan Quan goto out;
115e098bc96SEvan Quan
116e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
117e098bc96SEvan Quan amdgpu_ucode_print_smc_hdr(&hdr->header);
118e098bc96SEvan Quan adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
119e098bc96SEvan Quan
120e098bc96SEvan Quan if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
121e098bc96SEvan Quan ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
122e098bc96SEvan Quan ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
123e098bc96SEvan Quan ucode->fw = adev->pm.fw;
124e098bc96SEvan Quan header = (const struct common_firmware_header *)ucode->fw->data;
125e098bc96SEvan Quan adev->firmware.fw_size +=
126e098bc96SEvan Quan ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
127e098bc96SEvan Quan }
128e098bc96SEvan Quan
129e098bc96SEvan Quan out:
130315d1716SMario Limonciello if (err)
131315d1716SMario Limonciello amdgpu_ucode_release(&adev->pm.fw);
132e098bc96SEvan Quan return err;
133e098bc96SEvan Quan }
134e098bc96SEvan Quan
smu_v11_0_fini_microcode(struct smu_context * smu)135e098bc96SEvan Quan void smu_v11_0_fini_microcode(struct smu_context *smu)
136e098bc96SEvan Quan {
137e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
138e098bc96SEvan Quan
139315d1716SMario Limonciello amdgpu_ucode_release(&adev->pm.fw);
140e098bc96SEvan Quan adev->pm.fw_version = 0;
141e098bc96SEvan Quan }
142e098bc96SEvan Quan
smu_v11_0_load_microcode(struct smu_context * smu)143e098bc96SEvan Quan int smu_v11_0_load_microcode(struct smu_context *smu)
144e098bc96SEvan Quan {
145e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
146e098bc96SEvan Quan const uint32_t *src;
147e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr;
148e098bc96SEvan Quan uint32_t addr_start = MP1_SRAM;
149e098bc96SEvan Quan uint32_t i;
150e098bc96SEvan Quan uint32_t smc_fw_size;
151e098bc96SEvan Quan uint32_t mp1_fw_flags;
152e098bc96SEvan Quan
153e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
154e098bc96SEvan Quan src = (const uint32_t *)(adev->pm.fw->data +
155e098bc96SEvan Quan le32_to_cpu(hdr->header.ucode_array_offset_bytes));
156e098bc96SEvan Quan smc_fw_size = hdr->header.ucode_size_bytes;
157e098bc96SEvan Quan
158e098bc96SEvan Quan for (i = 1; i < smc_fw_size/4 - 1; i++) {
159e098bc96SEvan Quan WREG32_PCIE(addr_start, src[i]);
160e098bc96SEvan Quan addr_start += 4;
161e098bc96SEvan Quan }
162e098bc96SEvan Quan
163e098bc96SEvan Quan WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
164e098bc96SEvan Quan 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
165e098bc96SEvan Quan WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
166e098bc96SEvan Quan 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
167e098bc96SEvan Quan
168e098bc96SEvan Quan for (i = 0; i < adev->usec_timeout; i++) {
169e098bc96SEvan Quan mp1_fw_flags = RREG32_PCIE(MP1_Public |
170e098bc96SEvan Quan (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
171e098bc96SEvan Quan if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
172e098bc96SEvan Quan MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
173e098bc96SEvan Quan break;
174e098bc96SEvan Quan udelay(1);
175e098bc96SEvan Quan }
176e098bc96SEvan Quan
177e098bc96SEvan Quan if (i == adev->usec_timeout)
178e098bc96SEvan Quan return -ETIME;
179e098bc96SEvan Quan
180e098bc96SEvan Quan return 0;
181e098bc96SEvan Quan }
182e098bc96SEvan Quan
smu_v11_0_check_fw_status(struct smu_context * smu)183e098bc96SEvan Quan int smu_v11_0_check_fw_status(struct smu_context *smu)
184e098bc96SEvan Quan {
185e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
186e098bc96SEvan Quan uint32_t mp1_fw_flags;
187e098bc96SEvan Quan
188e098bc96SEvan Quan mp1_fw_flags = RREG32_PCIE(MP1_Public |
189e098bc96SEvan Quan (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
190e098bc96SEvan Quan
191e098bc96SEvan Quan if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
192e098bc96SEvan Quan MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
193e098bc96SEvan Quan return 0;
194e098bc96SEvan Quan
195e098bc96SEvan Quan return -EIO;
196e098bc96SEvan Quan }
197e098bc96SEvan Quan
smu_v11_0_check_fw_version(struct smu_context * smu)198e098bc96SEvan Quan int smu_v11_0_check_fw_version(struct smu_context *smu)
199e098bc96SEvan Quan {
200dda818a0SAlex Deucher struct amdgpu_device *adev = smu->adev;
201e098bc96SEvan Quan uint32_t if_version = 0xff, smu_version = 0xff;
20282890466SMario Limonciello uint8_t smu_program, smu_major, smu_minor, smu_debug;
203e098bc96SEvan Quan int ret = 0;
204e098bc96SEvan Quan
205e098bc96SEvan Quan ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
206e098bc96SEvan Quan if (ret)
207e098bc96SEvan Quan return ret;
208e098bc96SEvan Quan
20982890466SMario Limonciello smu_program = (smu_version >> 24) & 0xff;
21082890466SMario Limonciello smu_major = (smu_version >> 16) & 0xff;
211e098bc96SEvan Quan smu_minor = (smu_version >> 8) & 0xff;
212e098bc96SEvan Quan smu_debug = (smu_version >> 0) & 0xff;
213dda818a0SAlex Deucher if (smu->is_apu)
214dda818a0SAlex Deucher adev->pm.fw_version = smu_version;
215e098bc96SEvan Quan
2161d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) {
217af3b89d3SAlex Deucher case IP_VERSION(11, 0, 0):
218e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
219e098bc96SEvan Quan break;
220af3b89d3SAlex Deucher case IP_VERSION(11, 0, 9):
221e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
222e098bc96SEvan Quan break;
223af3b89d3SAlex Deucher case IP_VERSION(11, 0, 5):
224e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
225e098bc96SEvan Quan break;
226af3b89d3SAlex Deucher case IP_VERSION(11, 0, 7):
227e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
228e098bc96SEvan Quan break;
229af3b89d3SAlex Deucher case IP_VERSION(11, 0, 11):
230e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
231e098bc96SEvan Quan break;
23276c023faSAlex Deucher case IP_VERSION(11, 5, 0):
23388779658SXiaojian Du smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
23488779658SXiaojian Du break;
235af3b89d3SAlex Deucher case IP_VERSION(11, 0, 12):
236db1f8a8fSTao Zhou smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
237db1f8a8fSTao Zhou break;
238af3b89d3SAlex Deucher case IP_VERSION(11, 0, 13):
2394d352669SChengming Gui smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
2404d352669SChengming Gui break;
241af3b89d3SAlex Deucher case IP_VERSION(11, 0, 8):
24261ad757dSLang Yu smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
24361ad757dSLang Yu break;
2446b726a0aSAlex Deucher case IP_VERSION(11, 0, 2):
245af3b89d3SAlex Deucher smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
246af3b89d3SAlex Deucher break;
2476b726a0aSAlex Deucher default:
2486b726a0aSAlex Deucher dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
2491d789535SAlex Deucher adev->ip_versions[MP1_HWIP][0]);
250e098bc96SEvan Quan smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
251e098bc96SEvan Quan break;
252e098bc96SEvan Quan }
253e098bc96SEvan Quan
254e098bc96SEvan Quan /*
255e098bc96SEvan Quan * 1. if_version mismatch is not critical as our fw is designed
256e098bc96SEvan Quan * to be backward compatible.
257e098bc96SEvan Quan * 2. New fw usually brings some optimizations. But that's visible
258e098bc96SEvan Quan * only on the paired driver.
259424b3d75SGuchun Chen * Considering above, we just leave user a verbal message instead
260e098bc96SEvan Quan * of halt driver loading.
261e098bc96SEvan Quan */
262e098bc96SEvan Quan if (if_version != smu->smc_driver_if_version) {
263e098bc96SEvan Quan dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
26482890466SMario Limonciello "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n",
265e098bc96SEvan Quan smu->smc_driver_if_version, if_version,
26682890466SMario Limonciello smu_program, smu_version, smu_major, smu_minor, smu_debug);
267424b3d75SGuchun Chen dev_info(smu->adev->dev, "SMU driver if version not matched\n");
268e098bc96SEvan Quan }
269e098bc96SEvan Quan
270e098bc96SEvan Quan return ret;
271e098bc96SEvan Quan }
272e098bc96SEvan Quan
smu_v11_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)273e098bc96SEvan Quan static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
274e098bc96SEvan Quan {
275e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
276e098bc96SEvan Quan uint32_t ppt_offset_bytes;
277e098bc96SEvan Quan const struct smc_firmware_header_v2_0 *v2;
278e098bc96SEvan Quan
279e098bc96SEvan Quan v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
280e098bc96SEvan Quan
281e098bc96SEvan Quan ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
282e098bc96SEvan Quan *size = le32_to_cpu(v2->ppt_size_bytes);
283e098bc96SEvan Quan *table = (uint8_t *)v2 + ppt_offset_bytes;
284e098bc96SEvan Quan
285e098bc96SEvan Quan return 0;
286e098bc96SEvan Quan }
287e098bc96SEvan Quan
smu_v11_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)288e098bc96SEvan Quan static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
289e098bc96SEvan Quan uint32_t *size, uint32_t pptable_id)
290e098bc96SEvan Quan {
291e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
292e098bc96SEvan Quan const struct smc_firmware_header_v2_1 *v2_1;
293e098bc96SEvan Quan struct smc_soft_pptable_entry *entries;
294e098bc96SEvan Quan uint32_t pptable_count = 0;
295e098bc96SEvan Quan int i = 0;
296e098bc96SEvan Quan
297e098bc96SEvan Quan v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
298e098bc96SEvan Quan entries = (struct smc_soft_pptable_entry *)
299e098bc96SEvan Quan ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
300e098bc96SEvan Quan pptable_count = le32_to_cpu(v2_1->pptable_count);
301e098bc96SEvan Quan for (i = 0; i < pptable_count; i++) {
302e098bc96SEvan Quan if (le32_to_cpu(entries[i].id) == pptable_id) {
303e098bc96SEvan Quan *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
304e098bc96SEvan Quan *size = le32_to_cpu(entries[i].ppt_size_bytes);
305e098bc96SEvan Quan break;
306e098bc96SEvan Quan }
307e098bc96SEvan Quan }
308e098bc96SEvan Quan
309e098bc96SEvan Quan if (i == pptable_count)
310e098bc96SEvan Quan return -EINVAL;
311e098bc96SEvan Quan
312e098bc96SEvan Quan return 0;
313e098bc96SEvan Quan }
314e098bc96SEvan Quan
smu_v11_0_setup_pptable(struct smu_context * smu)315e098bc96SEvan Quan int smu_v11_0_setup_pptable(struct smu_context *smu)
316e098bc96SEvan Quan {
317e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
318e098bc96SEvan Quan const struct smc_firmware_header_v1_0 *hdr;
319e098bc96SEvan Quan int ret, index;
320e098bc96SEvan Quan uint32_t size = 0;
321e098bc96SEvan Quan uint16_t atom_table_size;
322e098bc96SEvan Quan uint8_t frev, crev;
323e098bc96SEvan Quan void *table;
324e098bc96SEvan Quan uint16_t version_major, version_minor;
325e098bc96SEvan Quan
3267c67d74dSJingwen Chen if (!amdgpu_sriov_vf(adev)) {
327e098bc96SEvan Quan hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
328e098bc96SEvan Quan version_major = le16_to_cpu(hdr->header.header_version_major);
329e098bc96SEvan Quan version_minor = le16_to_cpu(hdr->header.header_version_minor);
330ac79f42aSChengming Gui if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
331e098bc96SEvan Quan dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
332e098bc96SEvan Quan switch (version_minor) {
333e098bc96SEvan Quan case 0:
334e098bc96SEvan Quan ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
335e098bc96SEvan Quan break;
336e098bc96SEvan Quan case 1:
337e098bc96SEvan Quan ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
338e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id);
339e098bc96SEvan Quan break;
340e098bc96SEvan Quan default:
341e098bc96SEvan Quan ret = -EINVAL;
342e098bc96SEvan Quan break;
343e098bc96SEvan Quan }
344e098bc96SEvan Quan if (ret)
345e098bc96SEvan Quan return ret;
3467c67d74dSJingwen Chen goto out;
3477c67d74dSJingwen Chen }
3487c67d74dSJingwen Chen }
349e098bc96SEvan Quan
350e098bc96SEvan Quan dev_info(adev->dev, "use vbios provided pptable\n");
351e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
352e098bc96SEvan Quan powerplayinfo);
353e098bc96SEvan Quan
354e098bc96SEvan Quan ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
355e098bc96SEvan Quan (uint8_t **)&table);
356e098bc96SEvan Quan if (ret)
357e098bc96SEvan Quan return ret;
358e098bc96SEvan Quan size = atom_table_size;
359e098bc96SEvan Quan
3607c67d74dSJingwen Chen out:
361e098bc96SEvan Quan if (!smu->smu_table.power_play_table)
362e098bc96SEvan Quan smu->smu_table.power_play_table = table;
363e098bc96SEvan Quan if (!smu->smu_table.power_play_table_size)
364e098bc96SEvan Quan smu->smu_table.power_play_table_size = size;
365e098bc96SEvan Quan
366e098bc96SEvan Quan return 0;
367e098bc96SEvan Quan }
368e098bc96SEvan Quan
smu_v11_0_init_smc_tables(struct smu_context * smu)369e098bc96SEvan Quan int smu_v11_0_init_smc_tables(struct smu_context *smu)
370e098bc96SEvan Quan {
371e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table;
372e098bc96SEvan Quan struct smu_table *tables = smu_table->tables;
373e098bc96SEvan Quan int ret = 0;
374e098bc96SEvan Quan
375e098bc96SEvan Quan smu_table->driver_pptable =
376e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
377e098bc96SEvan Quan if (!smu_table->driver_pptable) {
378e098bc96SEvan Quan ret = -ENOMEM;
379e098bc96SEvan Quan goto err0_out;
380e098bc96SEvan Quan }
381e098bc96SEvan Quan
382e098bc96SEvan Quan smu_table->max_sustainable_clocks =
383e098bc96SEvan Quan kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
384e098bc96SEvan Quan if (!smu_table->max_sustainable_clocks) {
385e098bc96SEvan Quan ret = -ENOMEM;
386e098bc96SEvan Quan goto err1_out;
387e098bc96SEvan Quan }
388e098bc96SEvan Quan
389e098bc96SEvan Quan /* Arcturus does not support OVERDRIVE */
390e098bc96SEvan Quan if (tables[SMU_TABLE_OVERDRIVE].size) {
391e098bc96SEvan Quan smu_table->overdrive_table =
392e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
393e098bc96SEvan Quan if (!smu_table->overdrive_table) {
394e098bc96SEvan Quan ret = -ENOMEM;
395e098bc96SEvan Quan goto err2_out;
396e098bc96SEvan Quan }
397e098bc96SEvan Quan
398e098bc96SEvan Quan smu_table->boot_overdrive_table =
399e098bc96SEvan Quan kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
400e098bc96SEvan Quan if (!smu_table->boot_overdrive_table) {
401e098bc96SEvan Quan ret = -ENOMEM;
402e098bc96SEvan Quan goto err3_out;
403e098bc96SEvan Quan }
40492cf0508SEvan Quan
40592cf0508SEvan Quan smu_table->user_overdrive_table =
40692cf0508SEvan Quan kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
40792cf0508SEvan Quan if (!smu_table->user_overdrive_table) {
40892cf0508SEvan Quan ret = -ENOMEM;
40992cf0508SEvan Quan goto err4_out;
41092cf0508SEvan Quan }
41192cf0508SEvan Quan
412e098bc96SEvan Quan }
413e098bc96SEvan Quan
414e098bc96SEvan Quan return 0;
415e098bc96SEvan Quan
41692cf0508SEvan Quan err4_out:
41792cf0508SEvan Quan kfree(smu_table->boot_overdrive_table);
418e098bc96SEvan Quan err3_out:
419e098bc96SEvan Quan kfree(smu_table->overdrive_table);
420e098bc96SEvan Quan err2_out:
421e098bc96SEvan Quan kfree(smu_table->max_sustainable_clocks);
422e098bc96SEvan Quan err1_out:
423e098bc96SEvan Quan kfree(smu_table->driver_pptable);
424e098bc96SEvan Quan err0_out:
425e098bc96SEvan Quan return ret;
426e098bc96SEvan Quan }
427e098bc96SEvan Quan
smu_v11_0_fini_smc_tables(struct smu_context * smu)428e098bc96SEvan Quan int smu_v11_0_fini_smc_tables(struct smu_context *smu)
429e098bc96SEvan Quan {
430e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table;
431e098bc96SEvan Quan struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
432e098bc96SEvan Quan
433e098bc96SEvan Quan kfree(smu_table->gpu_metrics_table);
43492cf0508SEvan Quan kfree(smu_table->user_overdrive_table);
435e098bc96SEvan Quan kfree(smu_table->boot_overdrive_table);
436e098bc96SEvan Quan kfree(smu_table->overdrive_table);
437e098bc96SEvan Quan kfree(smu_table->max_sustainable_clocks);
438e098bc96SEvan Quan kfree(smu_table->driver_pptable);
439c98ee897SXiaojian Du kfree(smu_table->clocks_table);
440e098bc96SEvan Quan smu_table->gpu_metrics_table = NULL;
44192cf0508SEvan Quan smu_table->user_overdrive_table = NULL;
442e098bc96SEvan Quan smu_table->boot_overdrive_table = NULL;
443e098bc96SEvan Quan smu_table->overdrive_table = NULL;
444e098bc96SEvan Quan smu_table->max_sustainable_clocks = NULL;
445e098bc96SEvan Quan smu_table->driver_pptable = NULL;
446c98ee897SXiaojian Du smu_table->clocks_table = NULL;
447e098bc96SEvan Quan kfree(smu_table->hardcode_pptable);
448e098bc96SEvan Quan smu_table->hardcode_pptable = NULL;
449e098bc96SEvan Quan
450816d61d5SEvan Quan kfree(smu_table->driver_smu_config_table);
4513ddd0c90Smziya kfree(smu_table->ecc_table);
452e098bc96SEvan Quan kfree(smu_table->metrics_table);
453e098bc96SEvan Quan kfree(smu_table->watermarks_table);
454816d61d5SEvan Quan smu_table->driver_smu_config_table = NULL;
4553ddd0c90Smziya smu_table->ecc_table = NULL;
456e098bc96SEvan Quan smu_table->metrics_table = NULL;
457e098bc96SEvan Quan smu_table->watermarks_table = NULL;
458e098bc96SEvan Quan smu_table->metrics_time = 0;
459e098bc96SEvan Quan
460e098bc96SEvan Quan kfree(smu_dpm->dpm_context);
461e098bc96SEvan Quan kfree(smu_dpm->golden_dpm_context);
462e098bc96SEvan Quan kfree(smu_dpm->dpm_current_power_state);
463e098bc96SEvan Quan kfree(smu_dpm->dpm_request_power_state);
464e098bc96SEvan Quan smu_dpm->dpm_context = NULL;
465e098bc96SEvan Quan smu_dpm->golden_dpm_context = NULL;
466e098bc96SEvan Quan smu_dpm->dpm_context_size = 0;
467e098bc96SEvan Quan smu_dpm->dpm_current_power_state = NULL;
468e098bc96SEvan Quan smu_dpm->dpm_request_power_state = NULL;
469e098bc96SEvan Quan
470e098bc96SEvan Quan return 0;
471e098bc96SEvan Quan }
472e098bc96SEvan Quan
smu_v11_0_init_power(struct smu_context * smu)473e098bc96SEvan Quan int smu_v11_0_init_power(struct smu_context *smu)
474e098bc96SEvan Quan {
475af3b89d3SAlex Deucher struct amdgpu_device *adev = smu->adev;
476e098bc96SEvan Quan struct smu_power_context *smu_power = &smu->smu_power;
4771d789535SAlex Deucher size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ?
478ae07970aSXiaomeng Hou sizeof(struct smu_11_5_power_context) :
479ae07970aSXiaomeng Hou sizeof(struct smu_11_0_power_context);
480e098bc96SEvan Quan
481ae07970aSXiaomeng Hou smu_power->power_context = kzalloc(size, GFP_KERNEL);
482e098bc96SEvan Quan if (!smu_power->power_context)
483e098bc96SEvan Quan return -ENOMEM;
484ae07970aSXiaomeng Hou smu_power->power_context_size = size;
485e098bc96SEvan Quan
486e098bc96SEvan Quan return 0;
487e098bc96SEvan Quan }
488e098bc96SEvan Quan
smu_v11_0_fini_power(struct smu_context * smu)489e098bc96SEvan Quan int smu_v11_0_fini_power(struct smu_context *smu)
490e098bc96SEvan Quan {
491e098bc96SEvan Quan struct smu_power_context *smu_power = &smu->smu_power;
492e098bc96SEvan Quan
493e098bc96SEvan Quan kfree(smu_power->power_context);
494e098bc96SEvan Quan smu_power->power_context = NULL;
495e098bc96SEvan Quan smu_power->power_context_size = 0;
496e098bc96SEvan Quan
497e098bc96SEvan Quan return 0;
498e098bc96SEvan Quan }
499e098bc96SEvan Quan
smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device * adev,uint8_t clk_id,uint8_t syspll_id,uint32_t * clk_freq)500e098bc96SEvan Quan static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
501e098bc96SEvan Quan uint8_t clk_id,
502e098bc96SEvan Quan uint8_t syspll_id,
503e098bc96SEvan Quan uint32_t *clk_freq)
504e098bc96SEvan Quan {
505e098bc96SEvan Quan struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
506e098bc96SEvan Quan struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
507e098bc96SEvan Quan int ret, index;
508e098bc96SEvan Quan
509e098bc96SEvan Quan input.clk_id = clk_id;
510e098bc96SEvan Quan input.syspll_id = syspll_id;
511e098bc96SEvan Quan input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
512e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
513e098bc96SEvan Quan getsmuclockinfo);
514e098bc96SEvan Quan
515e098bc96SEvan Quan ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
516e098bc96SEvan Quan (uint32_t *)&input);
517e098bc96SEvan Quan if (ret)
518e098bc96SEvan Quan return -EINVAL;
519e098bc96SEvan Quan
520e098bc96SEvan Quan output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
521e098bc96SEvan Quan *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
522e098bc96SEvan Quan
523e098bc96SEvan Quan return 0;
524e098bc96SEvan Quan }
525e098bc96SEvan Quan
smu_v11_0_get_vbios_bootup_values(struct smu_context * smu)526e098bc96SEvan Quan int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
527e098bc96SEvan Quan {
528e098bc96SEvan Quan int ret, index;
529e098bc96SEvan Quan uint16_t size;
530e098bc96SEvan Quan uint8_t frev, crev;
531e098bc96SEvan Quan struct atom_common_table_header *header;
532e098bc96SEvan Quan struct atom_firmware_info_v3_3 *v_3_3;
533e098bc96SEvan Quan struct atom_firmware_info_v3_1 *v_3_1;
534e098bc96SEvan Quan
535e098bc96SEvan Quan index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
536e098bc96SEvan Quan firmwareinfo);
537e098bc96SEvan Quan
538e098bc96SEvan Quan ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
539e098bc96SEvan Quan (uint8_t **)&header);
540e098bc96SEvan Quan if (ret)
541e098bc96SEvan Quan return ret;
542e098bc96SEvan Quan
543e098bc96SEvan Quan if (header->format_revision != 3) {
544e098bc96SEvan Quan dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
545e098bc96SEvan Quan return -EINVAL;
546e098bc96SEvan Quan }
547e098bc96SEvan Quan
548e098bc96SEvan Quan switch (header->content_revision) {
549e098bc96SEvan Quan case 0:
550e098bc96SEvan Quan case 1:
551e098bc96SEvan Quan case 2:
552e098bc96SEvan Quan v_3_1 = (struct atom_firmware_info_v3_1 *)header;
553e098bc96SEvan Quan smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
554e098bc96SEvan Quan smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
555e098bc96SEvan Quan smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
556e098bc96SEvan Quan smu->smu_table.boot_values.socclk = 0;
557e098bc96SEvan Quan smu->smu_table.boot_values.dcefclk = 0;
558e098bc96SEvan Quan smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
559e098bc96SEvan Quan smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
560e098bc96SEvan Quan smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
561e098bc96SEvan Quan smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
562e098bc96SEvan Quan smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
563e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id = 0;
564a7e660e5SEvan Quan smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
565e098bc96SEvan Quan break;
566e098bc96SEvan Quan case 3:
5673495d3c3SXiaojian Du case 4:
568e098bc96SEvan Quan default:
569e098bc96SEvan Quan v_3_3 = (struct atom_firmware_info_v3_3 *)header;
570e098bc96SEvan Quan smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
571e098bc96SEvan Quan smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
572e098bc96SEvan Quan smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
573e098bc96SEvan Quan smu->smu_table.boot_values.socclk = 0;
574e098bc96SEvan Quan smu->smu_table.boot_values.dcefclk = 0;
575e098bc96SEvan Quan smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
576e098bc96SEvan Quan smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
577e098bc96SEvan Quan smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
578e098bc96SEvan Quan smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
579e098bc96SEvan Quan smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
580e098bc96SEvan Quan smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
581a7e660e5SEvan Quan smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
582e098bc96SEvan Quan }
583e098bc96SEvan Quan
584e098bc96SEvan Quan smu->smu_table.boot_values.format_revision = header->format_revision;
585e098bc96SEvan Quan smu->smu_table.boot_values.content_revision = header->content_revision;
586e098bc96SEvan Quan
587e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev,
588e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
589e098bc96SEvan Quan (uint8_t)0,
590e098bc96SEvan Quan &smu->smu_table.boot_values.socclk);
591e098bc96SEvan Quan
592e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev,
593e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
594e098bc96SEvan Quan (uint8_t)0,
595e098bc96SEvan Quan &smu->smu_table.boot_values.dcefclk);
596e098bc96SEvan Quan
597e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev,
598e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_ECLK_ID,
599e098bc96SEvan Quan (uint8_t)0,
600e098bc96SEvan Quan &smu->smu_table.boot_values.eclk);
601e098bc96SEvan Quan
602e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev,
603e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_VCLK_ID,
604e098bc96SEvan Quan (uint8_t)0,
605e098bc96SEvan Quan &smu->smu_table.boot_values.vclk);
606e098bc96SEvan Quan
607e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev,
608e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL0_DCLK_ID,
609e098bc96SEvan Quan (uint8_t)0,
610e098bc96SEvan Quan &smu->smu_table.boot_values.dclk);
611e098bc96SEvan Quan
612e098bc96SEvan Quan if ((smu->smu_table.boot_values.format_revision == 3) &&
613e098bc96SEvan Quan (smu->smu_table.boot_values.content_revision >= 2))
614e098bc96SEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev,
615e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
616e098bc96SEvan Quan (uint8_t)SMU11_SYSPLL1_2_ID,
617e098bc96SEvan Quan &smu->smu_table.boot_values.fclk);
618e098bc96SEvan Quan
6197d92c1fdSEvan Quan smu_v11_0_atom_get_smu_clockinfo(smu->adev,
6207d92c1fdSEvan Quan (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
6217d92c1fdSEvan Quan (uint8_t)SMU11_SYSPLL3_1_ID,
6227d92c1fdSEvan Quan &smu->smu_table.boot_values.lclk);
6237d92c1fdSEvan Quan
624e098bc96SEvan Quan return 0;
625e098bc96SEvan Quan }
626e098bc96SEvan Quan
smu_v11_0_notify_memory_pool_location(struct smu_context * smu)627e098bc96SEvan Quan int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
628e098bc96SEvan Quan {
629e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table;
630e098bc96SEvan Quan struct smu_table *memory_pool = &smu_table->memory_pool;
631e098bc96SEvan Quan int ret = 0;
632e098bc96SEvan Quan uint64_t address;
633e098bc96SEvan Quan uint32_t address_low, address_high;
634e098bc96SEvan Quan
635e098bc96SEvan Quan if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
636e098bc96SEvan Quan return ret;
637e098bc96SEvan Quan
638e098bc96SEvan Quan address = (uintptr_t)memory_pool->cpu_addr;
639e098bc96SEvan Quan address_high = (uint32_t)upper_32_bits(address);
640e098bc96SEvan Quan address_low = (uint32_t)lower_32_bits(address);
641e098bc96SEvan Quan
642e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
643e098bc96SEvan Quan SMU_MSG_SetSystemVirtualDramAddrHigh,
644e098bc96SEvan Quan address_high,
645e098bc96SEvan Quan NULL);
646e098bc96SEvan Quan if (ret)
647e098bc96SEvan Quan return ret;
648e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
649e098bc96SEvan Quan SMU_MSG_SetSystemVirtualDramAddrLow,
650e098bc96SEvan Quan address_low,
651e098bc96SEvan Quan NULL);
652e098bc96SEvan Quan if (ret)
653e098bc96SEvan Quan return ret;
654e098bc96SEvan Quan
655e098bc96SEvan Quan address = memory_pool->mc_address;
656e098bc96SEvan Quan address_high = (uint32_t)upper_32_bits(address);
657e098bc96SEvan Quan address_low = (uint32_t)lower_32_bits(address);
658e098bc96SEvan Quan
659e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
660e098bc96SEvan Quan address_high, NULL);
661e098bc96SEvan Quan if (ret)
662e098bc96SEvan Quan return ret;
663e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
664e098bc96SEvan Quan address_low, NULL);
665e098bc96SEvan Quan if (ret)
666e098bc96SEvan Quan return ret;
667e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
668e098bc96SEvan Quan (uint32_t)memory_pool->size, NULL);
669e098bc96SEvan Quan if (ret)
670e098bc96SEvan Quan return ret;
671e098bc96SEvan Quan
672e098bc96SEvan Quan return ret;
673e098bc96SEvan Quan }
674e098bc96SEvan Quan
smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)675e098bc96SEvan Quan int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
676e098bc96SEvan Quan {
677e098bc96SEvan Quan int ret;
678e098bc96SEvan Quan
679e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
680e098bc96SEvan Quan SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
681e098bc96SEvan Quan if (ret)
682e098bc96SEvan Quan dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
683e098bc96SEvan Quan
684e098bc96SEvan Quan return ret;
685e098bc96SEvan Quan }
686e098bc96SEvan Quan
smu_v11_0_set_driver_table_location(struct smu_context * smu)687e098bc96SEvan Quan int smu_v11_0_set_driver_table_location(struct smu_context *smu)
688e098bc96SEvan Quan {
689e098bc96SEvan Quan struct smu_table *driver_table = &smu->smu_table.driver_table;
690e098bc96SEvan Quan int ret = 0;
691e098bc96SEvan Quan
692e098bc96SEvan Quan if (driver_table->mc_address) {
693e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
694e098bc96SEvan Quan SMU_MSG_SetDriverDramAddrHigh,
695e098bc96SEvan Quan upper_32_bits(driver_table->mc_address),
696e098bc96SEvan Quan NULL);
697e098bc96SEvan Quan if (!ret)
698e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
699e098bc96SEvan Quan SMU_MSG_SetDriverDramAddrLow,
700e098bc96SEvan Quan lower_32_bits(driver_table->mc_address),
701e098bc96SEvan Quan NULL);
702e098bc96SEvan Quan }
703e098bc96SEvan Quan
704e098bc96SEvan Quan return ret;
705e098bc96SEvan Quan }
706e098bc96SEvan Quan
smu_v11_0_set_tool_table_location(struct smu_context * smu)707e098bc96SEvan Quan int smu_v11_0_set_tool_table_location(struct smu_context *smu)
708e098bc96SEvan Quan {
709e098bc96SEvan Quan int ret = 0;
710e098bc96SEvan Quan struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
711e098bc96SEvan Quan
712e098bc96SEvan Quan if (tool_table->mc_address) {
713e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
714e098bc96SEvan Quan SMU_MSG_SetToolsDramAddrHigh,
715e098bc96SEvan Quan upper_32_bits(tool_table->mc_address),
716e098bc96SEvan Quan NULL);
717e098bc96SEvan Quan if (!ret)
718e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
719e098bc96SEvan Quan SMU_MSG_SetToolsDramAddrLow,
720e098bc96SEvan Quan lower_32_bits(tool_table->mc_address),
721e098bc96SEvan Quan NULL);
722e098bc96SEvan Quan }
723e098bc96SEvan Quan
724e098bc96SEvan Quan return ret;
725e098bc96SEvan Quan }
726e098bc96SEvan Quan
smu_v11_0_init_display_count(struct smu_context * smu,uint32_t count)727e098bc96SEvan Quan int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
728e098bc96SEvan Quan {
729e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
730e098bc96SEvan Quan
731db1f8a8fSTao Zhou /* Navy_Flounder/Dimgrey_Cavefish do not support to change
732db1f8a8fSTao Zhou * display num currently
733db1f8a8fSTao Zhou */
7341d789535SAlex Deucher if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) ||
7351d789535SAlex Deucher adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ||
7364df55857SAlex Deucher adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12) ||
7371d789535SAlex Deucher adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13))
738e098bc96SEvan Quan return 0;
739e098bc96SEvan Quan
74038d11e02SEvan Quan return smu_cmn_send_smc_msg_with_param(smu,
74138d11e02SEvan Quan SMU_MSG_NumOfDisplays,
74238d11e02SEvan Quan count,
74338d11e02SEvan Quan NULL);
744e098bc96SEvan Quan }
745e098bc96SEvan Quan
746e098bc96SEvan Quan
smu_v11_0_set_allowed_mask(struct smu_context * smu)747e098bc96SEvan Quan int smu_v11_0_set_allowed_mask(struct smu_context *smu)
748e098bc96SEvan Quan {
749e098bc96SEvan Quan struct smu_feature *feature = &smu->smu_feature;
750e098bc96SEvan Quan int ret = 0;
751e098bc96SEvan Quan uint32_t feature_mask[2];
752e098bc96SEvan Quan
753692bd2a0SJia-Ju Bai if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
754692bd2a0SJia-Ju Bai ret = -EINVAL;
755e098bc96SEvan Quan goto failed;
756692bd2a0SJia-Ju Bai }
757e098bc96SEvan Quan
758525d6515SYury Norov bitmap_to_arr32(feature_mask, feature->allowed, 64);
759e098bc96SEvan Quan
760e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
761e098bc96SEvan Quan feature_mask[1], NULL);
762e098bc96SEvan Quan if (ret)
763e098bc96SEvan Quan goto failed;
764e098bc96SEvan Quan
765e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
766e098bc96SEvan Quan feature_mask[0], NULL);
767e098bc96SEvan Quan if (ret)
768e098bc96SEvan Quan goto failed;
769e098bc96SEvan Quan
770e098bc96SEvan Quan failed:
771e098bc96SEvan Quan return ret;
772e098bc96SEvan Quan }
773e098bc96SEvan Quan
smu_v11_0_system_features_control(struct smu_context * smu,bool en)774e098bc96SEvan Quan int smu_v11_0_system_features_control(struct smu_context *smu,
775e098bc96SEvan Quan bool en)
776e098bc96SEvan Quan {
7773c6591e9SEvan Quan return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
778e098bc96SEvan Quan SMU_MSG_DisableAllSmuFeatures), NULL);
779e098bc96SEvan Quan }
780e098bc96SEvan Quan
smu_v11_0_notify_display_change(struct smu_context * smu)781e098bc96SEvan Quan int smu_v11_0_notify_display_change(struct smu_context *smu)
782e098bc96SEvan Quan {
783e098bc96SEvan Quan int ret = 0;
784e098bc96SEvan Quan
785e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
786e098bc96SEvan Quan smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
787e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
788e098bc96SEvan Quan
789e098bc96SEvan Quan return ret;
790e098bc96SEvan Quan }
791e098bc96SEvan Quan
792e098bc96SEvan Quan static int
smu_v11_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)793e098bc96SEvan Quan smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
794e098bc96SEvan Quan enum smu_clk_type clock_select)
795e098bc96SEvan Quan {
796e098bc96SEvan Quan int ret = 0;
797e098bc96SEvan Quan int clk_id;
798e098bc96SEvan Quan
799e098bc96SEvan Quan if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
800e098bc96SEvan Quan (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
801e098bc96SEvan Quan return 0;
802e098bc96SEvan Quan
803e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu,
804e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK,
805e098bc96SEvan Quan clock_select);
806e098bc96SEvan Quan if (clk_id < 0)
807e098bc96SEvan Quan return -EINVAL;
808e098bc96SEvan Quan
809e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
810e098bc96SEvan Quan clk_id << 16, clock);
811e098bc96SEvan Quan if (ret) {
812e098bc96SEvan Quan dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
813e098bc96SEvan Quan return ret;
814e098bc96SEvan Quan }
815e098bc96SEvan Quan
816e098bc96SEvan Quan if (*clock != 0)
817e098bc96SEvan Quan return 0;
818e098bc96SEvan Quan
819e098bc96SEvan Quan /* if DC limit is zero, return AC limit */
820e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
821e098bc96SEvan Quan clk_id << 16, clock);
822e098bc96SEvan Quan if (ret) {
823e098bc96SEvan Quan dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
824e098bc96SEvan Quan return ret;
825e098bc96SEvan Quan }
826e098bc96SEvan Quan
827e098bc96SEvan Quan return 0;
828e098bc96SEvan Quan }
829e098bc96SEvan Quan
smu_v11_0_init_max_sustainable_clocks(struct smu_context * smu)830e098bc96SEvan Quan int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
831e098bc96SEvan Quan {
832e098bc96SEvan Quan struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
833e098bc96SEvan Quan smu->smu_table.max_sustainable_clocks;
834e098bc96SEvan Quan int ret = 0;
835e098bc96SEvan Quan
836e098bc96SEvan Quan max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
837e098bc96SEvan Quan max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
838e098bc96SEvan Quan max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
839e098bc96SEvan Quan max_sustainable_clocks->display_clock = 0xFFFFFFFF;
840e098bc96SEvan Quan max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
841e098bc96SEvan Quan max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
842e098bc96SEvan Quan
843e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
844e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu,
845e098bc96SEvan Quan &(max_sustainable_clocks->uclock),
846e098bc96SEvan Quan SMU_UCLK);
847e098bc96SEvan Quan if (ret) {
848e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
849e098bc96SEvan Quan __func__);
850e098bc96SEvan Quan return ret;
851e098bc96SEvan Quan }
852e098bc96SEvan Quan }
853e098bc96SEvan Quan
854e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
855e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu,
856e098bc96SEvan Quan &(max_sustainable_clocks->soc_clock),
857e098bc96SEvan Quan SMU_SOCCLK);
858e098bc96SEvan Quan if (ret) {
859e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
860e098bc96SEvan Quan __func__);
861e098bc96SEvan Quan return ret;
862e098bc96SEvan Quan }
863e098bc96SEvan Quan }
864e098bc96SEvan Quan
865e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
866e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu,
867e098bc96SEvan Quan &(max_sustainable_clocks->dcef_clock),
868e098bc96SEvan Quan SMU_DCEFCLK);
869e098bc96SEvan Quan if (ret) {
870e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
871e098bc96SEvan Quan __func__);
872e098bc96SEvan Quan return ret;
873e098bc96SEvan Quan }
874e098bc96SEvan Quan
875e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu,
876e098bc96SEvan Quan &(max_sustainable_clocks->display_clock),
877e098bc96SEvan Quan SMU_DISPCLK);
878e098bc96SEvan Quan if (ret) {
879e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
880e098bc96SEvan Quan __func__);
881e098bc96SEvan Quan return ret;
882e098bc96SEvan Quan }
883e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu,
884e098bc96SEvan Quan &(max_sustainable_clocks->phy_clock),
885e098bc96SEvan Quan SMU_PHYCLK);
886e098bc96SEvan Quan if (ret) {
887e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
888e098bc96SEvan Quan __func__);
889e098bc96SEvan Quan return ret;
890e098bc96SEvan Quan }
891e098bc96SEvan Quan ret = smu_v11_0_get_max_sustainable_clock(smu,
892e098bc96SEvan Quan &(max_sustainable_clocks->pixel_clock),
893e098bc96SEvan Quan SMU_PIXCLK);
894e098bc96SEvan Quan if (ret) {
895e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
896e098bc96SEvan Quan __func__);
897e098bc96SEvan Quan return ret;
898e098bc96SEvan Quan }
899e098bc96SEvan Quan }
900e098bc96SEvan Quan
901e098bc96SEvan Quan if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
902e098bc96SEvan Quan max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
903e098bc96SEvan Quan
904e098bc96SEvan Quan return 0;
905e098bc96SEvan Quan }
906e098bc96SEvan Quan
smu_v11_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)907e098bc96SEvan Quan int smu_v11_0_get_current_power_limit(struct smu_context *smu,
908e098bc96SEvan Quan uint32_t *power_limit)
909e098bc96SEvan Quan {
910e098bc96SEvan Quan int power_src;
911e098bc96SEvan Quan int ret = 0;
912e098bc96SEvan Quan
913e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
914e098bc96SEvan Quan return -EINVAL;
915e098bc96SEvan Quan
916e098bc96SEvan Quan power_src = smu_cmn_to_asic_specific_index(smu,
917e098bc96SEvan Quan CMN2ASIC_MAPPING_PWR,
918e098bc96SEvan Quan smu->adev->pm.ac_power ?
919e098bc96SEvan Quan SMU_POWER_SOURCE_AC :
920e098bc96SEvan Quan SMU_POWER_SOURCE_DC);
921e098bc96SEvan Quan if (power_src < 0)
922e098bc96SEvan Quan return -EINVAL;
923e098bc96SEvan Quan
9240cb4c621SEvan Quan /*
9250cb4c621SEvan Quan * BIT 24-31: ControllerId (only PPT0 is supported for now)
9260cb4c621SEvan Quan * BIT 16-23: PowerSource
9270cb4c621SEvan Quan */
928e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
929e098bc96SEvan Quan SMU_MSG_GetPptLimit,
9300cb4c621SEvan Quan (0 << 24) | (power_src << 16),
931e098bc96SEvan Quan power_limit);
932e098bc96SEvan Quan if (ret)
933e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
934e098bc96SEvan Quan
935e098bc96SEvan Quan return ret;
936e098bc96SEvan Quan }
937e098bc96SEvan Quan
smu_v11_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)9382d1ac1cbSDarren Powell int smu_v11_0_set_power_limit(struct smu_context *smu,
9392d1ac1cbSDarren Powell enum smu_ppt_limit_type limit_type,
9402d1ac1cbSDarren Powell uint32_t limit)
941e098bc96SEvan Quan {
9420cb4c621SEvan Quan int power_src;
943e098bc96SEvan Quan int ret = 0;
94402f8aa9fSDarren Powell uint32_t limit_param;
945e098bc96SEvan Quan
9462d1ac1cbSDarren Powell if (limit_type != SMU_DEFAULT_PPT_LIMIT)
9472d1ac1cbSDarren Powell return -EINVAL;
9482d1ac1cbSDarren Powell
949e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
950e098bc96SEvan Quan dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
951e098bc96SEvan Quan return -EOPNOTSUPP;
952e098bc96SEvan Quan }
953e098bc96SEvan Quan
9540cb4c621SEvan Quan power_src = smu_cmn_to_asic_specific_index(smu,
9550cb4c621SEvan Quan CMN2ASIC_MAPPING_PWR,
9560cb4c621SEvan Quan smu->adev->pm.ac_power ?
9570cb4c621SEvan Quan SMU_POWER_SOURCE_AC :
9580cb4c621SEvan Quan SMU_POWER_SOURCE_DC);
9590cb4c621SEvan Quan if (power_src < 0)
9600cb4c621SEvan Quan return -EINVAL;
9610cb4c621SEvan Quan
9620cb4c621SEvan Quan /*
9630cb4c621SEvan Quan * BIT 24-31: ControllerId (only PPT0 is supported for now)
9640cb4c621SEvan Quan * BIT 16-23: PowerSource
9650cb4c621SEvan Quan * BIT 0-15: PowerLimit
9660cb4c621SEvan Quan */
96702f8aa9fSDarren Powell limit_param = (limit & 0xFFFF);
96802f8aa9fSDarren Powell limit_param |= 0 << 24;
96902f8aa9fSDarren Powell limit_param |= (power_src) << 16;
97002f8aa9fSDarren Powell ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL);
971e098bc96SEvan Quan if (ret) {
972e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
973e098bc96SEvan Quan return ret;
974e098bc96SEvan Quan }
975e098bc96SEvan Quan
9762d1ac1cbSDarren Powell smu->current_power_limit = limit;
977e098bc96SEvan Quan
978e098bc96SEvan Quan return 0;
979e098bc96SEvan Quan }
980e098bc96SEvan Quan
smu_v11_0_ack_ac_dc_interrupt(struct smu_context * smu)98171f9404fSEvan Quan static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
98271f9404fSEvan Quan {
98371f9404fSEvan Quan return smu_cmn_send_smc_msg(smu,
98471f9404fSEvan Quan SMU_MSG_ReenableAcDcInterrupt,
98571f9404fSEvan Quan NULL);
98671f9404fSEvan Quan }
98771f9404fSEvan Quan
smu_v11_0_process_pending_interrupt(struct smu_context * smu)98871f9404fSEvan Quan static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
98971f9404fSEvan Quan {
99071f9404fSEvan Quan int ret = 0;
99171f9404fSEvan Quan
99271f9404fSEvan Quan if (smu->dc_controlled_by_gpio &&
99371f9404fSEvan Quan smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
99471f9404fSEvan Quan ret = smu_v11_0_ack_ac_dc_interrupt(smu);
99571f9404fSEvan Quan
99671f9404fSEvan Quan return ret;
99771f9404fSEvan Quan }
99871f9404fSEvan Quan
smu_v11_0_interrupt_work(struct smu_context * smu)999234676d6SAlex Deucher void smu_v11_0_interrupt_work(struct smu_context *smu)
1000234676d6SAlex Deucher {
1001234676d6SAlex Deucher if (smu_v11_0_ack_ac_dc_interrupt(smu))
1002234676d6SAlex Deucher dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1003234676d6SAlex Deucher }
1004234676d6SAlex Deucher
smu_v11_0_enable_thermal_alert(struct smu_context * smu)1005e098bc96SEvan Quan int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1006e098bc96SEvan Quan {
100771f9404fSEvan Quan int ret = 0;
1008e098bc96SEvan Quan
100971f9404fSEvan Quan if (smu->smu_table.thermal_controller_type) {
101071f9404fSEvan Quan ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
101171f9404fSEvan Quan if (ret)
101271f9404fSEvan Quan return ret;
101371f9404fSEvan Quan }
101471f9404fSEvan Quan
101571f9404fSEvan Quan /*
101671f9404fSEvan Quan * After init there might have been missed interrupts triggered
101771f9404fSEvan Quan * before driver registers for interrupt (Ex. AC/DC).
101871f9404fSEvan Quan */
101971f9404fSEvan Quan return smu_v11_0_process_pending_interrupt(smu);
1020e098bc96SEvan Quan }
1021e098bc96SEvan Quan
smu_v11_0_disable_thermal_alert(struct smu_context * smu)1022e098bc96SEvan Quan int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1023e098bc96SEvan Quan {
1024e098bc96SEvan Quan return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1025e098bc96SEvan Quan }
1026e098bc96SEvan Quan
convert_to_vddc(uint8_t vid)1027e098bc96SEvan Quan static uint16_t convert_to_vddc(uint8_t vid)
1028e098bc96SEvan Quan {
1029e098bc96SEvan Quan return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1030e098bc96SEvan Quan }
1031e098bc96SEvan Quan
smu_v11_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1032e098bc96SEvan Quan int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1033e098bc96SEvan Quan {
1034e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
1035e098bc96SEvan Quan uint32_t vdd = 0, val_vid = 0;
1036e098bc96SEvan Quan
1037e098bc96SEvan Quan if (!value)
1038e098bc96SEvan Quan return -EINVAL;
1039e098bc96SEvan Quan val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1040e098bc96SEvan Quan SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1041e098bc96SEvan Quan SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1042e098bc96SEvan Quan
1043e098bc96SEvan Quan vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1044e098bc96SEvan Quan
1045e098bc96SEvan Quan *value = vdd;
1046e098bc96SEvan Quan
1047e098bc96SEvan Quan return 0;
1048e098bc96SEvan Quan
1049e098bc96SEvan Quan }
1050e098bc96SEvan Quan
1051e098bc96SEvan Quan int
smu_v11_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1052e098bc96SEvan Quan smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1053e098bc96SEvan Quan struct pp_display_clock_request
1054e098bc96SEvan Quan *clock_req)
1055e098bc96SEvan Quan {
1056e098bc96SEvan Quan enum amd_pp_clock_type clk_type = clock_req->clock_type;
1057e098bc96SEvan Quan int ret = 0;
1058e098bc96SEvan Quan enum smu_clk_type clk_select = 0;
1059e098bc96SEvan Quan uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1060e098bc96SEvan Quan
1061e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1062e098bc96SEvan Quan smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1063e098bc96SEvan Quan switch (clk_type) {
1064e098bc96SEvan Quan case amd_pp_dcef_clock:
1065e098bc96SEvan Quan clk_select = SMU_DCEFCLK;
1066e098bc96SEvan Quan break;
1067e098bc96SEvan Quan case amd_pp_disp_clock:
1068e098bc96SEvan Quan clk_select = SMU_DISPCLK;
1069e098bc96SEvan Quan break;
1070e098bc96SEvan Quan case amd_pp_pixel_clock:
1071e098bc96SEvan Quan clk_select = SMU_PIXCLK;
1072e098bc96SEvan Quan break;
1073e098bc96SEvan Quan case amd_pp_phy_clock:
1074e098bc96SEvan Quan clk_select = SMU_PHYCLK;
1075e098bc96SEvan Quan break;
1076e098bc96SEvan Quan case amd_pp_mem_clock:
1077e098bc96SEvan Quan clk_select = SMU_UCLK;
1078e098bc96SEvan Quan break;
1079e098bc96SEvan Quan default:
1080e098bc96SEvan Quan dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1081e098bc96SEvan Quan ret = -EINVAL;
1082e098bc96SEvan Quan break;
1083e098bc96SEvan Quan }
1084e098bc96SEvan Quan
1085e098bc96SEvan Quan if (ret)
1086e098bc96SEvan Quan goto failed;
1087e098bc96SEvan Quan
1088e098bc96SEvan Quan if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1089e098bc96SEvan Quan return 0;
1090e098bc96SEvan Quan
1091e098bc96SEvan Quan ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1092e098bc96SEvan Quan
1093e098bc96SEvan Quan if(clk_select == SMU_UCLK)
1094e098bc96SEvan Quan smu->hard_min_uclk_req_from_dal = clk_freq;
1095e098bc96SEvan Quan }
1096e098bc96SEvan Quan
1097e098bc96SEvan Quan failed:
1098e098bc96SEvan Quan return ret;
1099e098bc96SEvan Quan }
1100e098bc96SEvan Quan
smu_v11_0_gfx_off_control(struct smu_context * smu,bool enable)1101e098bc96SEvan Quan int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1102e098bc96SEvan Quan {
1103e098bc96SEvan Quan int ret = 0;
1104e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
1105e098bc96SEvan Quan
11061d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) {
1107af3b89d3SAlex Deucher case IP_VERSION(11, 0, 0):
1108af3b89d3SAlex Deucher case IP_VERSION(11, 0, 5):
1109af3b89d3SAlex Deucher case IP_VERSION(11, 0, 9):
1110af3b89d3SAlex Deucher case IP_VERSION(11, 0, 7):
1111af3b89d3SAlex Deucher case IP_VERSION(11, 0, 11):
1112af3b89d3SAlex Deucher case IP_VERSION(11, 0, 12):
1113af3b89d3SAlex Deucher case IP_VERSION(11, 0, 13):
1114af3b89d3SAlex Deucher case IP_VERSION(11, 5, 0):
1115e098bc96SEvan Quan if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1116e098bc96SEvan Quan return 0;
1117e098bc96SEvan Quan if (enable)
1118e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1119e098bc96SEvan Quan else
1120e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1121e098bc96SEvan Quan break;
1122e098bc96SEvan Quan default:
1123e098bc96SEvan Quan break;
1124e098bc96SEvan Quan }
1125e098bc96SEvan Quan
1126e098bc96SEvan Quan return ret;
1127e098bc96SEvan Quan }
1128e098bc96SEvan Quan
1129e098bc96SEvan Quan uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context * smu)1130e098bc96SEvan Quan smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1131e098bc96SEvan Quan {
11324954a76aSAlex Deucher if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1133e098bc96SEvan Quan return AMD_FAN_CTRL_AUTO;
11344954a76aSAlex Deucher else
11354954a76aSAlex Deucher return smu->user_dpm_profile.fan_mode;
1136e098bc96SEvan Quan }
1137e098bc96SEvan Quan
1138e098bc96SEvan Quan static int
smu_v11_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1139e098bc96SEvan Quan smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1140e098bc96SEvan Quan {
1141e098bc96SEvan Quan int ret = 0;
1142e098bc96SEvan Quan
1143e098bc96SEvan Quan if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1144e098bc96SEvan Quan return 0;
1145e098bc96SEvan Quan
1146e098bc96SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1147e098bc96SEvan Quan if (ret)
1148e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1149e098bc96SEvan Quan __func__, (auto_fan_control ? "Start" : "Stop"));
1150e098bc96SEvan Quan
1151e098bc96SEvan Quan return ret;
1152e098bc96SEvan Quan }
1153e098bc96SEvan Quan
1154e098bc96SEvan Quan static int
smu_v11_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1155e098bc96SEvan Quan smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1156e098bc96SEvan Quan {
1157e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
1158e098bc96SEvan Quan
1159e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1160e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1161e098bc96SEvan Quan CG_FDO_CTRL2, TMIN, 0));
1162e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1163e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1164e098bc96SEvan Quan CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1165e098bc96SEvan Quan
1166e098bc96SEvan Quan return 0;
1167e098bc96SEvan Quan }
1168e098bc96SEvan Quan
1169e098bc96SEvan Quan int
smu_v11_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)11700d8318e1SEvan Quan smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed)
1171cd305137SAlex Deucher {
1172cd305137SAlex Deucher struct amdgpu_device *adev = smu->adev;
1173cd305137SAlex Deucher uint32_t duty100, duty;
1174cd305137SAlex Deucher uint64_t tmp64;
1175cd305137SAlex Deucher
11760d8318e1SEvan Quan speed = MIN(speed, 255);
1177cd305137SAlex Deucher
1178cd305137SAlex Deucher duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1179cd305137SAlex Deucher CG_FDO_CTRL1, FMAX_DUTY100);
1180cd305137SAlex Deucher if (!duty100)
1181cd305137SAlex Deucher return -EINVAL;
1182cd305137SAlex Deucher
1183cd305137SAlex Deucher tmp64 = (uint64_t)speed * duty100;
11840d8318e1SEvan Quan do_div(tmp64, 255);
1185cd305137SAlex Deucher duty = (uint32_t)tmp64;
1186cd305137SAlex Deucher
1187cd305137SAlex Deucher WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1188cd305137SAlex Deucher REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1189cd305137SAlex Deucher CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1190cd305137SAlex Deucher
1191cd305137SAlex Deucher return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1192cd305137SAlex Deucher }
1193cd305137SAlex Deucher
smu_v11_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1194f3289d04SEvan Quan int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1195f3289d04SEvan Quan uint32_t speed)
1196f3289d04SEvan Quan {
1197f3289d04SEvan Quan struct amdgpu_device *adev = smu->adev;
1198f3289d04SEvan Quan /*
1199f3289d04SEvan Quan * crystal_clock_freq used for fan speed rpm calculation is
1200f3289d04SEvan Quan * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1201f3289d04SEvan Quan */
1202f3289d04SEvan Quan uint32_t crystal_clock_freq = 2500;
1203f3289d04SEvan Quan uint32_t tach_period;
1204f3289d04SEvan Quan
12051e866f1fSYefim Barashkin if (speed == 0)
12061e866f1fSYefim Barashkin return -EINVAL;
1207f3289d04SEvan Quan /*
1208f3289d04SEvan Quan * To prevent from possible overheat, some ASICs may have requirement
1209f3289d04SEvan Quan * for minimum fan speed:
1210f3289d04SEvan Quan * - For some NV10 SKU, the fan speed cannot be set lower than
1211f3289d04SEvan Quan * 700 RPM.
1212f3289d04SEvan Quan * - For some Sienna Cichlid SKU, the fan speed cannot be set
1213f3289d04SEvan Quan * lower than 500 RPM.
1214f3289d04SEvan Quan */
1215f3289d04SEvan Quan tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1216f3289d04SEvan Quan WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1217f3289d04SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1218f3289d04SEvan Quan CG_TACH_CTRL, TARGET_PERIOD,
1219f3289d04SEvan Quan tach_period));
1220f3289d04SEvan Quan
1221bc08cab6SEvan Quan return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1222f3289d04SEvan Quan }
1223f3289d04SEvan Quan
smu_v11_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)12240d8318e1SEvan Quan int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
1225fb1f667eSEvan Quan uint32_t *speed)
1226fb1f667eSEvan Quan {
1227fb1f667eSEvan Quan struct amdgpu_device *adev = smu->adev;
1228fb1f667eSEvan Quan uint32_t duty100, duty;
1229fb1f667eSEvan Quan uint64_t tmp64;
1230fb1f667eSEvan Quan
1231fb1f667eSEvan Quan /*
1232fb1f667eSEvan Quan * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1233fb1f667eSEvan Quan * detected via register retrieving. To workaround this, we will
1234fb1f667eSEvan Quan * report the fan speed as 0 PWM if user just requested such.
1235fb1f667eSEvan Quan */
1236fb1f667eSEvan Quan if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
12370d8318e1SEvan Quan && !smu->user_dpm_profile.fan_speed_pwm) {
1238fb1f667eSEvan Quan *speed = 0;
1239fb1f667eSEvan Quan return 0;
1240fb1f667eSEvan Quan }
1241fb1f667eSEvan Quan
1242fb1f667eSEvan Quan duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1243fb1f667eSEvan Quan CG_FDO_CTRL1, FMAX_DUTY100);
1244fb1f667eSEvan Quan duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
1245fb1f667eSEvan Quan CG_THERMAL_STATUS, FDO_PWM_DUTY);
1246fb1f667eSEvan Quan if (!duty100)
1247fb1f667eSEvan Quan return -EINVAL;
1248fb1f667eSEvan Quan
12490d8318e1SEvan Quan tmp64 = (uint64_t)duty * 255;
1250fb1f667eSEvan Quan do_div(tmp64, duty100);
12510d8318e1SEvan Quan *speed = MIN((uint32_t)tmp64, 255);
1252fb1f667eSEvan Quan
1253fb1f667eSEvan Quan return 0;
1254fb1f667eSEvan Quan }
1255fb1f667eSEvan Quan
smu_v11_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1256d9ca7567SEvan Quan int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1257d9ca7567SEvan Quan uint32_t *speed)
1258d9ca7567SEvan Quan {
1259d9ca7567SEvan Quan struct amdgpu_device *adev = smu->adev;
1260d9ca7567SEvan Quan uint32_t crystal_clock_freq = 2500;
1261d9ca7567SEvan Quan uint32_t tach_status;
1262d9ca7567SEvan Quan uint64_t tmp64;
1263d9ca7567SEvan Quan
1264d9ca7567SEvan Quan /*
1265d9ca7567SEvan Quan * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1266d9ca7567SEvan Quan * detected via register retrieving. To workaround this, we will
1267d9ca7567SEvan Quan * report the fan speed as 0 RPM if user just requested such.
1268d9ca7567SEvan Quan */
1269d9ca7567SEvan Quan if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1270d9ca7567SEvan Quan && !smu->user_dpm_profile.fan_speed_rpm) {
1271d9ca7567SEvan Quan *speed = 0;
1272d9ca7567SEvan Quan return 0;
1273d9ca7567SEvan Quan }
1274d9ca7567SEvan Quan
1275d9ca7567SEvan Quan tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1276d9ca7567SEvan Quan
1277d9ca7567SEvan Quan tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
12788ac1696bSEvan Quan if (tach_status) {
1279d9ca7567SEvan Quan do_div(tmp64, tach_status);
1280d9ca7567SEvan Quan *speed = (uint32_t)tmp64;
12818ac1696bSEvan Quan } else {
12828ac1696bSEvan Quan dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n");
12838ac1696bSEvan Quan *speed = 0;
12848ac1696bSEvan Quan }
1285d9ca7567SEvan Quan
1286d9ca7567SEvan Quan return 0;
1287d9ca7567SEvan Quan }
1288d9ca7567SEvan Quan
1289cd305137SAlex Deucher int
smu_v11_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1290e098bc96SEvan Quan smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1291e098bc96SEvan Quan uint32_t mode)
1292e098bc96SEvan Quan {
1293e098bc96SEvan Quan int ret = 0;
1294e098bc96SEvan Quan
1295e098bc96SEvan Quan switch (mode) {
1296e098bc96SEvan Quan case AMD_FAN_CTRL_NONE:
1297bc08cab6SEvan Quan ret = smu_v11_0_auto_fan_control(smu, 0);
1298bc08cab6SEvan Quan if (!ret)
12990d8318e1SEvan Quan ret = smu_v11_0_set_fan_speed_pwm(smu, 255);
1300e098bc96SEvan Quan break;
1301e098bc96SEvan Quan case AMD_FAN_CTRL_MANUAL:
1302e098bc96SEvan Quan ret = smu_v11_0_auto_fan_control(smu, 0);
1303e098bc96SEvan Quan break;
1304e098bc96SEvan Quan case AMD_FAN_CTRL_AUTO:
1305e098bc96SEvan Quan ret = smu_v11_0_auto_fan_control(smu, 1);
1306e098bc96SEvan Quan break;
1307e098bc96SEvan Quan default:
1308e098bc96SEvan Quan break;
1309e098bc96SEvan Quan }
1310e098bc96SEvan Quan
1311e098bc96SEvan Quan if (ret) {
1312e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1313e098bc96SEvan Quan return -EINVAL;
1314e098bc96SEvan Quan }
1315e098bc96SEvan Quan
1316e098bc96SEvan Quan return ret;
1317e098bc96SEvan Quan }
1318e098bc96SEvan Quan
smu_v11_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1319e098bc96SEvan Quan int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1320e098bc96SEvan Quan uint32_t pstate)
1321e098bc96SEvan Quan {
13226c20f157SEvan Quan return smu_cmn_send_smc_msg_with_param(smu,
1323e098bc96SEvan Quan SMU_MSG_SetXgmiMode,
1324e098bc96SEvan Quan pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1325e098bc96SEvan Quan NULL);
1326e098bc96SEvan Quan }
1327e098bc96SEvan Quan
smu_v11_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1328e098bc96SEvan Quan static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1329e098bc96SEvan Quan struct amdgpu_irq_src *source,
1330e098bc96SEvan Quan unsigned tyep,
1331e098bc96SEvan Quan enum amdgpu_interrupt_state state)
1332e098bc96SEvan Quan {
1333ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle;
1334e098bc96SEvan Quan uint32_t low, high;
1335e098bc96SEvan Quan uint32_t val = 0;
1336e098bc96SEvan Quan
1337e098bc96SEvan Quan switch (state) {
1338e098bc96SEvan Quan case AMDGPU_IRQ_STATE_DISABLE:
1339e098bc96SEvan Quan /* For THM irqs */
1340e098bc96SEvan Quan val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1341e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1342e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1343e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1344e098bc96SEvan Quan
1345e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1346e098bc96SEvan Quan
1347e098bc96SEvan Quan /* For MP1 SW irqs */
1348e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1349e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1350e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1351e098bc96SEvan Quan
1352e098bc96SEvan Quan break;
1353e098bc96SEvan Quan case AMDGPU_IRQ_STATE_ENABLE:
1354e098bc96SEvan Quan /* For THM irqs */
1355e098bc96SEvan Quan low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1356e098bc96SEvan Quan smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1357e098bc96SEvan Quan high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1358e098bc96SEvan Quan smu->thermal_range.software_shutdown_temp);
1359e098bc96SEvan Quan
1360e098bc96SEvan Quan val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1361e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1362e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1363e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1364e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1365e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1366e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1367e098bc96SEvan Quan val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1368e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1369e098bc96SEvan Quan
1370e098bc96SEvan Quan val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1371e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1372e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1373e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1374e098bc96SEvan Quan
1375e098bc96SEvan Quan /* For MP1 SW irqs */
1376e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1377e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1378e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1379e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1380e098bc96SEvan Quan
1381e098bc96SEvan Quan val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1382e098bc96SEvan Quan val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1383e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1384e098bc96SEvan Quan
1385e098bc96SEvan Quan break;
1386e098bc96SEvan Quan default:
1387e098bc96SEvan Quan break;
1388e098bc96SEvan Quan }
1389e098bc96SEvan Quan
1390e098bc96SEvan Quan return 0;
1391e098bc96SEvan Quan }
1392e098bc96SEvan Quan
1393e098bc96SEvan Quan #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1394e098bc96SEvan Quan #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1395e098bc96SEvan Quan
1396e098bc96SEvan Quan #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1397e098bc96SEvan Quan
smu_v11_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1398e098bc96SEvan Quan static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1399e098bc96SEvan Quan struct amdgpu_irq_src *source,
1400e098bc96SEvan Quan struct amdgpu_iv_entry *entry)
1401e098bc96SEvan Quan {
1402ebfc2533SEvan Quan struct smu_context *smu = adev->powerplay.pp_handle;
1403e098bc96SEvan Quan uint32_t client_id = entry->client_id;
1404e098bc96SEvan Quan uint32_t src_id = entry->src_id;
1405e098bc96SEvan Quan /*
1406e098bc96SEvan Quan * ctxid is used to distinguish different
1407e098bc96SEvan Quan * events for SMCToHost interrupt.
1408e098bc96SEvan Quan */
1409e098bc96SEvan Quan uint32_t ctxid = entry->src_data[0];
1410e098bc96SEvan Quan uint32_t data;
1411e098bc96SEvan Quan
1412e098bc96SEvan Quan if (client_id == SOC15_IH_CLIENTID_THM) {
1413e098bc96SEvan Quan switch (src_id) {
1414e098bc96SEvan Quan case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1415b75efe88SEvan Quan schedule_delayed_work(&smu->swctf_delayed_work,
1416b75efe88SEvan Quan msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1417e098bc96SEvan Quan break;
1418e098bc96SEvan Quan case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1419e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1420e098bc96SEvan Quan break;
1421e098bc96SEvan Quan default:
1422e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1423e098bc96SEvan Quan src_id);
1424e098bc96SEvan Quan break;
1425e098bc96SEvan Quan }
1426e098bc96SEvan Quan } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1427e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1428e098bc96SEvan Quan /*
1429e098bc96SEvan Quan * HW CTF just occurred. Shutdown to prevent further damage.
1430e098bc96SEvan Quan */
1431e098bc96SEvan Quan dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1432e098bc96SEvan Quan orderly_poweroff(true);
1433e098bc96SEvan Quan } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1434e098bc96SEvan Quan if (src_id == 0xfe) {
1435e098bc96SEvan Quan /* ACK SMUToHost interrupt */
1436e098bc96SEvan Quan data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1437e098bc96SEvan Quan data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1438e098bc96SEvan Quan WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1439e098bc96SEvan Quan
1440e098bc96SEvan Quan switch (ctxid) {
1441e098bc96SEvan Quan case 0x3:
1442e098bc96SEvan Quan dev_dbg(adev->dev, "Switched to AC mode!\n");
1443234676d6SAlex Deucher schedule_work(&smu->interrupt_work);
1444*dcda362dSMa Jun adev->pm.ac_power = true;
1445e098bc96SEvan Quan break;
1446e098bc96SEvan Quan case 0x4:
1447e098bc96SEvan Quan dev_dbg(adev->dev, "Switched to DC mode!\n");
1448234676d6SAlex Deucher schedule_work(&smu->interrupt_work);
1449*dcda362dSMa Jun adev->pm.ac_power = false;
1450e098bc96SEvan Quan break;
1451e098bc96SEvan Quan case 0x7:
1452e098bc96SEvan Quan /*
1453e098bc96SEvan Quan * Increment the throttle interrupt counter
1454e098bc96SEvan Quan */
1455e098bc96SEvan Quan atomic64_inc(&smu->throttle_int_counter);
1456e098bc96SEvan Quan
1457e098bc96SEvan Quan if (!atomic_read(&adev->throttling_logging_enabled))
1458e098bc96SEvan Quan return 0;
1459e098bc96SEvan Quan
1460e098bc96SEvan Quan if (__ratelimit(&adev->throttling_logging_rs))
1461e098bc96SEvan Quan schedule_work(&smu->throttling_logging_work);
1462e098bc96SEvan Quan
1463e098bc96SEvan Quan break;
1464e098bc96SEvan Quan }
1465e098bc96SEvan Quan }
1466e098bc96SEvan Quan }
1467e098bc96SEvan Quan
1468e098bc96SEvan Quan return 0;
1469e098bc96SEvan Quan }
1470e098bc96SEvan Quan
1471e098bc96SEvan Quan static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1472e098bc96SEvan Quan {
1473e098bc96SEvan Quan .set = smu_v11_0_set_irq_state,
1474e098bc96SEvan Quan .process = smu_v11_0_irq_process,
1475e098bc96SEvan Quan };
1476e098bc96SEvan Quan
smu_v11_0_register_irq_handler(struct smu_context * smu)1477e098bc96SEvan Quan int smu_v11_0_register_irq_handler(struct smu_context *smu)
1478e098bc96SEvan Quan {
1479e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
1480e098bc96SEvan Quan struct amdgpu_irq_src *irq_src = &smu->irq_source;
1481e098bc96SEvan Quan int ret = 0;
1482e098bc96SEvan Quan
1483e098bc96SEvan Quan irq_src->num_types = 1;
1484e098bc96SEvan Quan irq_src->funcs = &smu_v11_0_irq_funcs;
1485e098bc96SEvan Quan
1486e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1487e098bc96SEvan Quan THM_11_0__SRCID__THM_DIG_THERM_L2H,
1488e098bc96SEvan Quan irq_src);
1489e098bc96SEvan Quan if (ret)
1490e098bc96SEvan Quan return ret;
1491e098bc96SEvan Quan
1492e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1493e098bc96SEvan Quan THM_11_0__SRCID__THM_DIG_THERM_H2L,
1494e098bc96SEvan Quan irq_src);
1495e098bc96SEvan Quan if (ret)
1496e098bc96SEvan Quan return ret;
1497e098bc96SEvan Quan
1498e098bc96SEvan Quan /* Register CTF(GPIO_19) interrupt */
1499e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1500e098bc96SEvan Quan SMUIO_11_0__SRCID__SMUIO_GPIO19,
1501e098bc96SEvan Quan irq_src);
1502e098bc96SEvan Quan if (ret)
1503e098bc96SEvan Quan return ret;
1504e098bc96SEvan Quan
1505e098bc96SEvan Quan ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1506e098bc96SEvan Quan 0xfe,
1507e098bc96SEvan Quan irq_src);
1508e098bc96SEvan Quan if (ret)
1509e098bc96SEvan Quan return ret;
1510e098bc96SEvan Quan
1511e098bc96SEvan Quan return ret;
1512e098bc96SEvan Quan }
1513e098bc96SEvan Quan
smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1514e098bc96SEvan Quan int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1515e098bc96SEvan Quan struct pp_smu_nv_clock_table *max_clocks)
1516e098bc96SEvan Quan {
1517e098bc96SEvan Quan struct smu_table_context *table_context = &smu->smu_table;
1518e098bc96SEvan Quan struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1519e098bc96SEvan Quan
1520e098bc96SEvan Quan if (!max_clocks || !table_context->max_sustainable_clocks)
1521e098bc96SEvan Quan return -EINVAL;
1522e098bc96SEvan Quan
1523e098bc96SEvan Quan sustainable_clocks = table_context->max_sustainable_clocks;
1524e098bc96SEvan Quan
1525e098bc96SEvan Quan max_clocks->dcfClockInKhz =
1526e098bc96SEvan Quan (unsigned int) sustainable_clocks->dcef_clock * 1000;
1527e098bc96SEvan Quan max_clocks->displayClockInKhz =
1528e098bc96SEvan Quan (unsigned int) sustainable_clocks->display_clock * 1000;
1529e098bc96SEvan Quan max_clocks->phyClockInKhz =
1530e098bc96SEvan Quan (unsigned int) sustainable_clocks->phy_clock * 1000;
1531e098bc96SEvan Quan max_clocks->pixelClockInKhz =
1532e098bc96SEvan Quan (unsigned int) sustainable_clocks->pixel_clock * 1000;
1533e098bc96SEvan Quan max_clocks->uClockInKhz =
1534e098bc96SEvan Quan (unsigned int) sustainable_clocks->uclock * 1000;
1535e098bc96SEvan Quan max_clocks->socClockInKhz =
1536e098bc96SEvan Quan (unsigned int) sustainable_clocks->soc_clock * 1000;
1537e098bc96SEvan Quan max_clocks->dscClockInKhz = 0;
1538e098bc96SEvan Quan max_clocks->dppClockInKhz = 0;
1539e098bc96SEvan Quan max_clocks->fabricClockInKhz = 0;
1540e098bc96SEvan Quan
1541e098bc96SEvan Quan return 0;
1542e098bc96SEvan Quan }
1543e098bc96SEvan Quan
smu_v11_0_set_azalia_d3_pme(struct smu_context * smu)1544e098bc96SEvan Quan int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1545e098bc96SEvan Quan {
15466c20f157SEvan Quan return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1547e098bc96SEvan Quan }
1548e098bc96SEvan Quan
smu_v11_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)154913d75eadSEvan Quan int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
15508ae5a38cSEvan Quan enum smu_baco_seq baco_seq)
1551e098bc96SEvan Quan {
1552e098bc96SEvan Quan return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1553e098bc96SEvan Quan }
1554e098bc96SEvan Quan
smu_v11_0_baco_is_support(struct smu_context * smu)1555e098bc96SEvan Quan bool smu_v11_0_baco_is_support(struct smu_context *smu)
1556e098bc96SEvan Quan {
1557e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco;
1558e098bc96SEvan Quan
155952a9fd7bSLijo Lazar if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
1560e098bc96SEvan Quan return false;
1561e098bc96SEvan Quan
15626dca7efeSGuchun Chen /* return true if ASIC is in BACO state already */
15636dca7efeSGuchun Chen if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
15646dca7efeSGuchun Chen return true;
15656dca7efeSGuchun Chen
1566e098bc96SEvan Quan /* Arcturus does not support this bit mask */
1567e098bc96SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1568e098bc96SEvan Quan !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1569e098bc96SEvan Quan return false;
1570e098bc96SEvan Quan
1571e098bc96SEvan Quan return true;
1572e098bc96SEvan Quan }
1573e098bc96SEvan Quan
smu_v11_0_baco_get_state(struct smu_context * smu)1574e098bc96SEvan Quan enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1575e098bc96SEvan Quan {
1576e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco;
1577e098bc96SEvan Quan
15781c4dba5eSEvan Quan return smu_baco->state;
1579e098bc96SEvan Quan }
1580e098bc96SEvan Quan
15812261229cSLikun Gao #define D3HOT_BACO_SEQUENCE 0
15822261229cSLikun Gao #define D3HOT_BAMACO_SEQUENCE 2
15832261229cSLikun Gao
smu_v11_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)1584e098bc96SEvan Quan int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1585e098bc96SEvan Quan {
1586e098bc96SEvan Quan struct smu_baco_context *smu_baco = &smu->smu_baco;
1587e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
1588e098bc96SEvan Quan struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1589e098bc96SEvan Quan uint32_t data;
1590e098bc96SEvan Quan int ret = 0;
1591e098bc96SEvan Quan
1592e098bc96SEvan Quan if (smu_v11_0_baco_get_state(smu) == state)
1593e098bc96SEvan Quan return 0;
1594e098bc96SEvan Quan
1595e098bc96SEvan Quan if (state == SMU_BACO_STATE_ENTER) {
15961d789535SAlex Deucher switch (adev->ip_versions[MP1_HWIP][0]) {
1597af3b89d3SAlex Deucher case IP_VERSION(11, 0, 7):
1598af3b89d3SAlex Deucher case IP_VERSION(11, 0, 11):
1599af3b89d3SAlex Deucher case IP_VERSION(11, 0, 12):
1600af3b89d3SAlex Deucher case IP_VERSION(11, 0, 13):
16012261229cSLikun Gao if (amdgpu_runtime_pm == 2)
16022261229cSLikun Gao ret = smu_cmn_send_smc_msg_with_param(smu,
16032261229cSLikun Gao SMU_MSG_EnterBaco,
16042261229cSLikun Gao D3HOT_BAMACO_SEQUENCE,
16052261229cSLikun Gao NULL);
16062261229cSLikun Gao else
16072261229cSLikun Gao ret = smu_cmn_send_smc_msg_with_param(smu,
16082261229cSLikun Gao SMU_MSG_EnterBaco,
16092261229cSLikun Gao D3HOT_BACO_SEQUENCE,
16102261229cSLikun Gao NULL);
16112261229cSLikun Gao break;
16122261229cSLikun Gao default:
16138ab0d6f0SLuben Tuikov if (!ras || !adev->ras_enabled ||
1614acdae216SLuben Tuikov adev->gmc.xgmi.pending_reset) {
16151d789535SAlex Deucher if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
1616e9995d4aSEvan Quan data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1617e9995d4aSEvan Quan data |= 0x80000000;
1618e9995d4aSEvan Quan WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1619e9995d4aSEvan Quan } else {
1620e098bc96SEvan Quan data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1621e098bc96SEvan Quan data |= 0x80000000;
1622e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1623e9995d4aSEvan Quan }
1624e098bc96SEvan Quan
1625e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1626e098bc96SEvan Quan } else {
1627e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1628e098bc96SEvan Quan }
16292261229cSLikun Gao break;
16302261229cSLikun Gao }
16312261229cSLikun Gao
1632e098bc96SEvan Quan } else {
1633e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1634e098bc96SEvan Quan if (ret)
16351c4dba5eSEvan Quan return ret;
1636e098bc96SEvan Quan
1637e098bc96SEvan Quan /* clear vbios scratch 6 and 7 for coming asic reinit */
1638e098bc96SEvan Quan WREG32(adev->bios_scratch_reg_offset + 6, 0);
1639e098bc96SEvan Quan WREG32(adev->bios_scratch_reg_offset + 7, 0);
1640e098bc96SEvan Quan }
1641e098bc96SEvan Quan
16421c4dba5eSEvan Quan if (!ret)
1643e098bc96SEvan Quan smu_baco->state = state;
16441c4dba5eSEvan Quan
1645e098bc96SEvan Quan return ret;
1646e098bc96SEvan Quan }
1647e098bc96SEvan Quan
smu_v11_0_baco_enter(struct smu_context * smu)1648e098bc96SEvan Quan int smu_v11_0_baco_enter(struct smu_context *smu)
1649e098bc96SEvan Quan {
1650e098bc96SEvan Quan int ret = 0;
1651e098bc96SEvan Quan
1652e098bc96SEvan Quan ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1653e098bc96SEvan Quan if (ret)
1654e098bc96SEvan Quan return ret;
1655e098bc96SEvan Quan
1656e098bc96SEvan Quan msleep(10);
1657e098bc96SEvan Quan
1658e098bc96SEvan Quan return ret;
1659e098bc96SEvan Quan }
1660e098bc96SEvan Quan
smu_v11_0_baco_exit(struct smu_context * smu)1661e098bc96SEvan Quan int smu_v11_0_baco_exit(struct smu_context *smu)
1662e098bc96SEvan Quan {
166386a3c691SGuchun Chen int ret;
166486a3c691SGuchun Chen
166586a3c691SGuchun Chen ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
166686a3c691SGuchun Chen if (!ret) {
166786a3c691SGuchun Chen /*
166886a3c691SGuchun Chen * Poll BACO exit status to ensure FW has completed
166986a3c691SGuchun Chen * BACO exit process to avoid timing issues.
167086a3c691SGuchun Chen */
167186a3c691SGuchun Chen smu_v11_0_poll_baco_exit(smu);
167286a3c691SGuchun Chen }
167386a3c691SGuchun Chen
167486a3c691SGuchun Chen return ret;
1675e098bc96SEvan Quan }
1676e098bc96SEvan Quan
smu_v11_0_mode1_reset(struct smu_context * smu)1677e098bc96SEvan Quan int smu_v11_0_mode1_reset(struct smu_context *smu)
1678e098bc96SEvan Quan {
1679e098bc96SEvan Quan int ret = 0;
1680e098bc96SEvan Quan
1681e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1682e098bc96SEvan Quan if (!ret)
1683e098bc96SEvan Quan msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1684e098bc96SEvan Quan
1685e098bc96SEvan Quan return ret;
1686e098bc96SEvan Quan }
1687e098bc96SEvan Quan
smu_v11_0_handle_passthrough_sbr(struct smu_context * smu,bool enable)16884da8b639Ssashank saye int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
16890e921596Sshaoyunl {
16900e921596Sshaoyunl int ret = 0;
16910e921596Sshaoyunl
16920e921596Sshaoyunl ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
16930e921596Sshaoyunl
16940e921596Sshaoyunl return ret;
16950e921596Sshaoyunl }
16960e921596Sshaoyunl
16970e921596Sshaoyunl
smu_v11_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1698e098bc96SEvan Quan int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1699e098bc96SEvan Quan uint32_t *min, uint32_t *max)
1700e098bc96SEvan Quan {
1701e098bc96SEvan Quan int ret = 0, clk_id = 0;
1702e098bc96SEvan Quan uint32_t param = 0;
1703e098bc96SEvan Quan uint32_t clock_limit;
1704e098bc96SEvan Quan
1705e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1706e098bc96SEvan Quan switch (clk_type) {
1707e098bc96SEvan Quan case SMU_MCLK:
1708e098bc96SEvan Quan case SMU_UCLK:
1709e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.uclk;
1710e098bc96SEvan Quan break;
1711e098bc96SEvan Quan case SMU_GFXCLK:
1712e098bc96SEvan Quan case SMU_SCLK:
1713e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.gfxclk;
1714e098bc96SEvan Quan break;
1715e098bc96SEvan Quan case SMU_SOCCLK:
1716e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.socclk;
1717e098bc96SEvan Quan break;
1718e098bc96SEvan Quan default:
1719e098bc96SEvan Quan clock_limit = 0;
1720e098bc96SEvan Quan break;
1721e098bc96SEvan Quan }
1722e098bc96SEvan Quan
1723e098bc96SEvan Quan /* clock in Mhz unit */
1724e098bc96SEvan Quan if (min)
1725e098bc96SEvan Quan *min = clock_limit / 100;
1726e098bc96SEvan Quan if (max)
1727e098bc96SEvan Quan *max = clock_limit / 100;
1728e098bc96SEvan Quan
1729e098bc96SEvan Quan return 0;
1730e098bc96SEvan Quan }
1731e098bc96SEvan Quan
1732e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu,
1733e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK,
1734e098bc96SEvan Quan clk_type);
1735e098bc96SEvan Quan if (clk_id < 0) {
1736e098bc96SEvan Quan ret = -EINVAL;
1737e098bc96SEvan Quan goto failed;
1738e098bc96SEvan Quan }
1739e098bc96SEvan Quan param = (clk_id & 0xffff) << 16;
1740e098bc96SEvan Quan
1741e098bc96SEvan Quan if (max) {
1742e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1743e098bc96SEvan Quan if (ret)
1744e098bc96SEvan Quan goto failed;
1745e098bc96SEvan Quan }
1746e098bc96SEvan Quan
1747e098bc96SEvan Quan if (min) {
1748e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1749e098bc96SEvan Quan if (ret)
1750e098bc96SEvan Quan goto failed;
1751e098bc96SEvan Quan }
1752e098bc96SEvan Quan
1753e098bc96SEvan Quan failed:
1754e098bc96SEvan Quan return ret;
1755e098bc96SEvan Quan }
1756e098bc96SEvan Quan
smu_v11_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1757e098bc96SEvan Quan int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1758e098bc96SEvan Quan enum smu_clk_type clk_type,
1759e098bc96SEvan Quan uint32_t min,
1760e098bc96SEvan Quan uint32_t max)
1761e098bc96SEvan Quan {
1762e098bc96SEvan Quan int ret = 0, clk_id = 0;
1763e098bc96SEvan Quan uint32_t param;
1764e098bc96SEvan Quan
1765e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1766e098bc96SEvan Quan return 0;
1767e098bc96SEvan Quan
1768e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu,
1769e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK,
1770e098bc96SEvan Quan clk_type);
1771e098bc96SEvan Quan if (clk_id < 0)
1772e098bc96SEvan Quan return clk_id;
1773e098bc96SEvan Quan
1774e098bc96SEvan Quan if (max > 0) {
1775e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1776e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1777e098bc96SEvan Quan param, NULL);
1778e098bc96SEvan Quan if (ret)
1779e098bc96SEvan Quan goto out;
1780e098bc96SEvan Quan }
1781e098bc96SEvan Quan
1782e098bc96SEvan Quan if (min > 0) {
1783e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1784e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1785e098bc96SEvan Quan param, NULL);
1786e098bc96SEvan Quan if (ret)
1787e098bc96SEvan Quan goto out;
1788e098bc96SEvan Quan }
1789e098bc96SEvan Quan
1790e098bc96SEvan Quan out:
1791e098bc96SEvan Quan return ret;
1792e098bc96SEvan Quan }
1793e098bc96SEvan Quan
smu_v11_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1794e098bc96SEvan Quan int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1795e098bc96SEvan Quan enum smu_clk_type clk_type,
1796e098bc96SEvan Quan uint32_t min,
1797e098bc96SEvan Quan uint32_t max)
1798e098bc96SEvan Quan {
1799e098bc96SEvan Quan int ret = 0, clk_id = 0;
1800e098bc96SEvan Quan uint32_t param;
1801e098bc96SEvan Quan
1802e098bc96SEvan Quan if (min <= 0 && max <= 0)
1803e098bc96SEvan Quan return -EINVAL;
1804e098bc96SEvan Quan
1805e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1806e098bc96SEvan Quan return 0;
1807e098bc96SEvan Quan
1808e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu,
1809e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK,
1810e098bc96SEvan Quan clk_type);
1811e098bc96SEvan Quan if (clk_id < 0)
1812e098bc96SEvan Quan return clk_id;
1813e098bc96SEvan Quan
1814e098bc96SEvan Quan if (max > 0) {
1815e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1816e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1817e098bc96SEvan Quan param, NULL);
1818e098bc96SEvan Quan if (ret)
1819e098bc96SEvan Quan return ret;
1820e098bc96SEvan Quan }
1821e098bc96SEvan Quan
1822e098bc96SEvan Quan if (min > 0) {
1823e098bc96SEvan Quan param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1824e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1825e098bc96SEvan Quan param, NULL);
1826e098bc96SEvan Quan if (ret)
1827e098bc96SEvan Quan return ret;
1828e098bc96SEvan Quan }
1829e098bc96SEvan Quan
1830e098bc96SEvan Quan return ret;
1831e098bc96SEvan Quan }
1832e098bc96SEvan Quan
smu_v11_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1833e098bc96SEvan Quan int smu_v11_0_set_performance_level(struct smu_context *smu,
1834e098bc96SEvan Quan enum amd_dpm_forced_level level)
1835e098bc96SEvan Quan {
1836e098bc96SEvan Quan struct smu_11_0_dpm_context *dpm_context =
1837e098bc96SEvan Quan smu->smu_dpm.dpm_context;
1838e098bc96SEvan Quan struct smu_11_0_dpm_table *gfx_table =
1839e098bc96SEvan Quan &dpm_context->dpm_tables.gfx_table;
1840e098bc96SEvan Quan struct smu_11_0_dpm_table *mem_table =
1841e098bc96SEvan Quan &dpm_context->dpm_tables.uclk_table;
1842e098bc96SEvan Quan struct smu_11_0_dpm_table *soc_table =
1843e098bc96SEvan Quan &dpm_context->dpm_tables.soc_table;
1844e098bc96SEvan Quan struct smu_umd_pstate_table *pstate_table =
1845e098bc96SEvan Quan &smu->pstate_table;
1846e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
1847e098bc96SEvan Quan uint32_t sclk_min = 0, sclk_max = 0;
1848e098bc96SEvan Quan uint32_t mclk_min = 0, mclk_max = 0;
1849e098bc96SEvan Quan uint32_t socclk_min = 0, socclk_max = 0;
1850e098bc96SEvan Quan int ret = 0;
1851e098bc96SEvan Quan
1852e098bc96SEvan Quan switch (level) {
1853e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_HIGH:
1854e098bc96SEvan Quan sclk_min = sclk_max = gfx_table->max;
1855e098bc96SEvan Quan mclk_min = mclk_max = mem_table->max;
1856e098bc96SEvan Quan socclk_min = socclk_max = soc_table->max;
1857e098bc96SEvan Quan break;
1858e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_LOW:
1859e098bc96SEvan Quan sclk_min = sclk_max = gfx_table->min;
1860e098bc96SEvan Quan mclk_min = mclk_max = mem_table->min;
1861e098bc96SEvan Quan socclk_min = socclk_max = soc_table->min;
1862e098bc96SEvan Quan break;
1863e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_AUTO:
1864e098bc96SEvan Quan sclk_min = gfx_table->min;
1865e098bc96SEvan Quan sclk_max = gfx_table->max;
1866e098bc96SEvan Quan mclk_min = mem_table->min;
1867e098bc96SEvan Quan mclk_max = mem_table->max;
1868e098bc96SEvan Quan socclk_min = soc_table->min;
1869e098bc96SEvan Quan socclk_max = soc_table->max;
1870e098bc96SEvan Quan break;
1871e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1872e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1873e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1874e098bc96SEvan Quan socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1875e098bc96SEvan Quan break;
1876e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1877e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1878e098bc96SEvan Quan break;
1879e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1880e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1881e098bc96SEvan Quan break;
1882e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1883e098bc96SEvan Quan sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1884e098bc96SEvan Quan mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1885e098bc96SEvan Quan socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1886e098bc96SEvan Quan break;
1887e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_MANUAL:
1888e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1889e098bc96SEvan Quan return 0;
1890e098bc96SEvan Quan default:
1891e098bc96SEvan Quan dev_err(adev->dev, "Invalid performance level %d\n", level);
1892e098bc96SEvan Quan return -EINVAL;
1893e098bc96SEvan Quan }
1894e098bc96SEvan Quan
1895e098bc96SEvan Quan /*
1896e098bc96SEvan Quan * Separate MCLK and SOCCLK soft min/max settings are not allowed
1897e098bc96SEvan Quan * on Arcturus.
1898e098bc96SEvan Quan */
18991d789535SAlex Deucher if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 2)) {
1900e098bc96SEvan Quan mclk_min = mclk_max = 0;
1901e098bc96SEvan Quan socclk_min = socclk_max = 0;
1902e098bc96SEvan Quan }
1903e098bc96SEvan Quan
1904e098bc96SEvan Quan if (sclk_min && sclk_max) {
1905e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu,
1906e098bc96SEvan Quan SMU_GFXCLK,
1907e098bc96SEvan Quan sclk_min,
1908e098bc96SEvan Quan sclk_max);
1909e098bc96SEvan Quan if (ret)
1910e098bc96SEvan Quan return ret;
1911e098bc96SEvan Quan }
1912e098bc96SEvan Quan
1913e098bc96SEvan Quan if (mclk_min && mclk_max) {
1914e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu,
1915e098bc96SEvan Quan SMU_MCLK,
1916e098bc96SEvan Quan mclk_min,
1917e098bc96SEvan Quan mclk_max);
1918e098bc96SEvan Quan if (ret)
1919e098bc96SEvan Quan return ret;
1920e098bc96SEvan Quan }
1921e098bc96SEvan Quan
1922e098bc96SEvan Quan if (socclk_min && socclk_max) {
1923e098bc96SEvan Quan ret = smu_v11_0_set_soft_freq_limited_range(smu,
1924e098bc96SEvan Quan SMU_SOCCLK,
1925e098bc96SEvan Quan socclk_min,
1926e098bc96SEvan Quan socclk_max);
1927e098bc96SEvan Quan if (ret)
1928e098bc96SEvan Quan return ret;
1929e098bc96SEvan Quan }
1930e098bc96SEvan Quan
1931e098bc96SEvan Quan return ret;
1932e098bc96SEvan Quan }
1933e098bc96SEvan Quan
smu_v11_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1934e098bc96SEvan Quan int smu_v11_0_set_power_source(struct smu_context *smu,
1935e098bc96SEvan Quan enum smu_power_src_type power_src)
1936e098bc96SEvan Quan {
1937e098bc96SEvan Quan int pwr_source;
1938e098bc96SEvan Quan
1939e098bc96SEvan Quan pwr_source = smu_cmn_to_asic_specific_index(smu,
1940e098bc96SEvan Quan CMN2ASIC_MAPPING_PWR,
1941e098bc96SEvan Quan (uint32_t)power_src);
1942e098bc96SEvan Quan if (pwr_source < 0)
1943e098bc96SEvan Quan return -EINVAL;
1944e098bc96SEvan Quan
1945e098bc96SEvan Quan return smu_cmn_send_smc_msg_with_param(smu,
1946e098bc96SEvan Quan SMU_MSG_NotifyPowerSource,
1947e098bc96SEvan Quan pwr_source,
1948e098bc96SEvan Quan NULL);
1949e098bc96SEvan Quan }
1950e098bc96SEvan Quan
smu_v11_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1951e098bc96SEvan Quan int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1952e098bc96SEvan Quan enum smu_clk_type clk_type,
1953e098bc96SEvan Quan uint16_t level,
1954e098bc96SEvan Quan uint32_t *value)
1955e098bc96SEvan Quan {
1956e098bc96SEvan Quan int ret = 0, clk_id = 0;
1957e098bc96SEvan Quan uint32_t param;
1958e098bc96SEvan Quan
1959e098bc96SEvan Quan if (!value)
1960e098bc96SEvan Quan return -EINVAL;
1961e098bc96SEvan Quan
1962e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1963e098bc96SEvan Quan return 0;
1964e098bc96SEvan Quan
1965e098bc96SEvan Quan clk_id = smu_cmn_to_asic_specific_index(smu,
1966e098bc96SEvan Quan CMN2ASIC_MAPPING_CLK,
1967e098bc96SEvan Quan clk_type);
1968e098bc96SEvan Quan if (clk_id < 0)
1969e098bc96SEvan Quan return clk_id;
1970e098bc96SEvan Quan
1971e098bc96SEvan Quan param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1972e098bc96SEvan Quan
1973e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
1974e098bc96SEvan Quan SMU_MSG_GetDpmFreqByIndex,
1975e098bc96SEvan Quan param,
1976e098bc96SEvan Quan value);
1977e098bc96SEvan Quan if (ret)
1978e098bc96SEvan Quan return ret;
1979e098bc96SEvan Quan
1980e098bc96SEvan Quan /*
1981e098bc96SEvan Quan * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1982e098bc96SEvan Quan * now, we un-support it
1983e098bc96SEvan Quan */
1984e098bc96SEvan Quan *value = *value & 0x7fffffff;
1985e098bc96SEvan Quan
1986e098bc96SEvan Quan return ret;
1987e098bc96SEvan Quan }
1988e098bc96SEvan Quan
smu_v11_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1989e098bc96SEvan Quan int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1990e098bc96SEvan Quan enum smu_clk_type clk_type,
1991e098bc96SEvan Quan uint32_t *value)
1992e098bc96SEvan Quan {
1993e098bc96SEvan Quan return smu_v11_0_get_dpm_freq_by_index(smu,
1994e098bc96SEvan Quan clk_type,
1995e098bc96SEvan Quan 0xff,
1996e098bc96SEvan Quan value);
1997e098bc96SEvan Quan }
1998e098bc96SEvan Quan
smu_v11_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_11_0_dpm_table * single_dpm_table)1999e098bc96SEvan Quan int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
2000e098bc96SEvan Quan enum smu_clk_type clk_type,
2001e098bc96SEvan Quan struct smu_11_0_dpm_table *single_dpm_table)
2002e098bc96SEvan Quan {
2003e098bc96SEvan Quan int ret = 0;
2004e098bc96SEvan Quan uint32_t clk;
2005e098bc96SEvan Quan int i;
2006e098bc96SEvan Quan
2007e098bc96SEvan Quan ret = smu_v11_0_get_dpm_level_count(smu,
2008e098bc96SEvan Quan clk_type,
2009e098bc96SEvan Quan &single_dpm_table->count);
2010e098bc96SEvan Quan if (ret) {
2011e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2012e098bc96SEvan Quan return ret;
2013e098bc96SEvan Quan }
2014e098bc96SEvan Quan
2015e098bc96SEvan Quan for (i = 0; i < single_dpm_table->count; i++) {
2016e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu,
2017e098bc96SEvan Quan clk_type,
2018e098bc96SEvan Quan i,
2019e098bc96SEvan Quan &clk);
2020e098bc96SEvan Quan if (ret) {
2021e098bc96SEvan Quan dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2022e098bc96SEvan Quan return ret;
2023e098bc96SEvan Quan }
2024e098bc96SEvan Quan
2025e098bc96SEvan Quan single_dpm_table->dpm_levels[i].value = clk;
2026e098bc96SEvan Quan single_dpm_table->dpm_levels[i].enabled = true;
2027e098bc96SEvan Quan
2028e098bc96SEvan Quan if (i == 0)
2029e098bc96SEvan Quan single_dpm_table->min = clk;
2030e098bc96SEvan Quan else if (i == single_dpm_table->count - 1)
2031e098bc96SEvan Quan single_dpm_table->max = clk;
2032e098bc96SEvan Quan }
2033e098bc96SEvan Quan
2034e098bc96SEvan Quan return 0;
2035e098bc96SEvan Quan }
2036e098bc96SEvan Quan
smu_v11_0_get_dpm_level_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min_value,uint32_t * max_value)2037e098bc96SEvan Quan int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
2038e098bc96SEvan Quan enum smu_clk_type clk_type,
2039e098bc96SEvan Quan uint32_t *min_value,
2040e098bc96SEvan Quan uint32_t *max_value)
2041e098bc96SEvan Quan {
2042e098bc96SEvan Quan uint32_t level_count = 0;
2043e098bc96SEvan Quan int ret = 0;
2044e098bc96SEvan Quan
2045e098bc96SEvan Quan if (!min_value && !max_value)
2046e098bc96SEvan Quan return -EINVAL;
2047e098bc96SEvan Quan
2048e098bc96SEvan Quan if (min_value) {
2049e098bc96SEvan Quan /* by default, level 0 clock value as min value */
2050e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu,
2051e098bc96SEvan Quan clk_type,
2052e098bc96SEvan Quan 0,
2053e098bc96SEvan Quan min_value);
2054e098bc96SEvan Quan if (ret)
2055e098bc96SEvan Quan return ret;
2056e098bc96SEvan Quan }
2057e098bc96SEvan Quan
2058e098bc96SEvan Quan if (max_value) {
2059e098bc96SEvan Quan ret = smu_v11_0_get_dpm_level_count(smu,
2060e098bc96SEvan Quan clk_type,
2061e098bc96SEvan Quan &level_count);
2062e098bc96SEvan Quan if (ret)
2063e098bc96SEvan Quan return ret;
2064e098bc96SEvan Quan
2065e098bc96SEvan Quan ret = smu_v11_0_get_dpm_freq_by_index(smu,
2066e098bc96SEvan Quan clk_type,
2067e098bc96SEvan Quan level_count - 1,
2068e098bc96SEvan Quan max_value);
2069e098bc96SEvan Quan if (ret)
2070e098bc96SEvan Quan return ret;
2071e098bc96SEvan Quan }
2072e098bc96SEvan Quan
2073e098bc96SEvan Quan return ret;
2074e098bc96SEvan Quan }
2075e098bc96SEvan Quan
smu_v11_0_get_current_pcie_link_width_level(struct smu_context * smu)2076e098bc96SEvan Quan int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2077e098bc96SEvan Quan {
2078e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
2079e098bc96SEvan Quan
2080e098bc96SEvan Quan return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2081e098bc96SEvan Quan PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2082e098bc96SEvan Quan >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2083e098bc96SEvan Quan }
2084e098bc96SEvan Quan
smu_v11_0_get_current_pcie_link_width(struct smu_context * smu)2085152bb95cSEvan Quan uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2086e098bc96SEvan Quan {
2087e098bc96SEvan Quan uint32_t width_level;
2088e098bc96SEvan Quan
2089e098bc96SEvan Quan width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2090e098bc96SEvan Quan if (width_level > LINK_WIDTH_MAX)
2091e098bc96SEvan Quan width_level = 0;
2092e098bc96SEvan Quan
2093e098bc96SEvan Quan return link_width[width_level];
2094e098bc96SEvan Quan }
2095e098bc96SEvan Quan
smu_v11_0_get_current_pcie_link_speed_level(struct smu_context * smu)2096e098bc96SEvan Quan int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2097e098bc96SEvan Quan {
2098e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
2099e098bc96SEvan Quan
2100e098bc96SEvan Quan return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2101e098bc96SEvan Quan PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2102e098bc96SEvan Quan >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2103e098bc96SEvan Quan }
2104e098bc96SEvan Quan
smu_v11_0_get_current_pcie_link_speed(struct smu_context * smu)2105152bb95cSEvan Quan uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2106e098bc96SEvan Quan {
2107e098bc96SEvan Quan uint32_t speed_level;
2108e098bc96SEvan Quan
2109e098bc96SEvan Quan speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2110e098bc96SEvan Quan if (speed_level > LINK_SPEED_MAX)
2111e098bc96SEvan Quan speed_level = 0;
2112e098bc96SEvan Quan
2113e098bc96SEvan Quan return link_speed[speed_level];
2114e098bc96SEvan Quan }
2115e098bc96SEvan Quan
smu_v11_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2116e988026fSEvan Quan int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2117e988026fSEvan Quan bool enablement)
2118e988026fSEvan Quan {
2119e988026fSEvan Quan int ret = 0;
2120e988026fSEvan Quan
2121e988026fSEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2122e988026fSEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2123e988026fSEvan Quan
2124e988026fSEvan Quan return ret;
2125e988026fSEvan Quan }
21265ce99853SEvan Quan
smu_v11_0_deep_sleep_control(struct smu_context * smu,bool enablement)21275ce99853SEvan Quan int smu_v11_0_deep_sleep_control(struct smu_context *smu,
21285ce99853SEvan Quan bool enablement)
21295ce99853SEvan Quan {
21305ce99853SEvan Quan struct amdgpu_device *adev = smu->adev;
21315ce99853SEvan Quan int ret = 0;
21325ce99853SEvan Quan
21335ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
21345ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
21355ce99853SEvan Quan if (ret) {
21365ce99853SEvan Quan dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
21375ce99853SEvan Quan return ret;
21385ce99853SEvan Quan }
21395ce99853SEvan Quan }
21405ce99853SEvan Quan
214178d907e2SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
214278d907e2SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
214378d907e2SEvan Quan if (ret) {
214478d907e2SEvan Quan dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
214578d907e2SEvan Quan return ret;
214678d907e2SEvan Quan }
214778d907e2SEvan Quan }
214878d907e2SEvan Quan
214978d907e2SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
215078d907e2SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
215178d907e2SEvan Quan if (ret) {
215278d907e2SEvan Quan dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
215378d907e2SEvan Quan return ret;
215478d907e2SEvan Quan }
215578d907e2SEvan Quan }
215678d907e2SEvan Quan
21575ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
21585ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
21595ce99853SEvan Quan if (ret) {
21605ce99853SEvan Quan dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
21615ce99853SEvan Quan return ret;
21625ce99853SEvan Quan }
21635ce99853SEvan Quan }
21645ce99853SEvan Quan
21655ce99853SEvan Quan if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
21665ce99853SEvan Quan ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
21675ce99853SEvan Quan if (ret) {
21685ce99853SEvan Quan dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
21695ce99853SEvan Quan return ret;
21705ce99853SEvan Quan }
21715ce99853SEvan Quan }
21725ce99853SEvan Quan
21735ce99853SEvan Quan return ret;
21745ce99853SEvan Quan }
217592cf0508SEvan Quan
smu_v11_0_restore_user_od_settings(struct smu_context * smu)217692cf0508SEvan Quan int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
217792cf0508SEvan Quan {
217892cf0508SEvan Quan struct smu_table_context *table_context = &smu->smu_table;
217992cf0508SEvan Quan void *user_od_table = table_context->user_overdrive_table;
218092cf0508SEvan Quan int ret = 0;
218192cf0508SEvan Quan
218292cf0508SEvan Quan ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true);
218392cf0508SEvan Quan if (ret)
218492cf0508SEvan Quan dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
218592cf0508SEvan Quan
218692cf0508SEvan Quan return ret;
218792cf0508SEvan Quan }
2188da1db031SAlex Deucher
smu_v11_0_set_smu_mailbox_registers(struct smu_context * smu)2189da1db031SAlex Deucher void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
2190da1db031SAlex Deucher {
2191da1db031SAlex Deucher struct amdgpu_device *adev = smu->adev;
2192da1db031SAlex Deucher
2193da1db031SAlex Deucher smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2194da1db031SAlex Deucher smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2195da1db031SAlex Deucher smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2196da1db031SAlex Deucher }
2197