1f46a221bSXiaojian Du /*
2f46a221bSXiaojian Du * Copyright 2020 Advanced Micro Devices, Inc.
3f46a221bSXiaojian Du *
4f46a221bSXiaojian Du * Permission is hereby granted, free of charge, to any person obtaining a
5f46a221bSXiaojian Du * copy of this software and associated documentation files (the "Software"),
6f46a221bSXiaojian Du * to deal in the Software without restriction, including without limitation
7f46a221bSXiaojian Du * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8f46a221bSXiaojian Du * and/or sell copies of the Software, and to permit persons to whom the
9f46a221bSXiaojian Du * Software is furnished to do so, subject to the following conditions:
10f46a221bSXiaojian Du *
11f46a221bSXiaojian Du * The above copyright notice and this permission notice shall be included in
12f46a221bSXiaojian Du * all copies or substantial portions of the Software.
13f46a221bSXiaojian Du *
14f46a221bSXiaojian Du * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15f46a221bSXiaojian Du * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16f46a221bSXiaojian Du * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17f46a221bSXiaojian Du * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18f46a221bSXiaojian Du * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19f46a221bSXiaojian Du * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20f46a221bSXiaojian Du * OTHER DEALINGS IN THE SOFTWARE.
21f46a221bSXiaojian Du *
22f46a221bSXiaojian Du */
23f46a221bSXiaojian Du
24f46a221bSXiaojian Du #define SWSMU_CODE_LAYER_L2
25f46a221bSXiaojian Du
26f46a221bSXiaojian Du #include "amdgpu.h"
27f46a221bSXiaojian Du #include "amdgpu_smu.h"
28f46a221bSXiaojian Du #include "smu_v11_0.h"
29f46a221bSXiaojian Du #include "smu11_driver_if_vangogh.h"
30f46a221bSXiaojian Du #include "vangogh_ppt.h"
31f46a221bSXiaojian Du #include "smu_v11_5_ppsmc.h"
32f46a221bSXiaojian Du #include "smu_v11_5_pmfw.h"
33f46a221bSXiaojian Du #include "smu_cmn.h"
34eefdf047SJinzhou Su #include "soc15_common.h"
35eefdf047SJinzhou Su #include "asic_reg/gc/gc_10_3_0_offset.h"
36eefdf047SJinzhou Su #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37517cb957SHuang Rui #include <asm/processor.h>
38f46a221bSXiaojian Du
39f46a221bSXiaojian Du /*
40f46a221bSXiaojian Du * DO NOT use these for err/warn/info/debug messages.
41f46a221bSXiaojian Du * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42f46a221bSXiaojian Du * They are more MGPU friendly.
43f46a221bSXiaojian Du */
44f46a221bSXiaojian Du #undef pr_err
45f46a221bSXiaojian Du #undef pr_warn
46f46a221bSXiaojian Du #undef pr_info
47f46a221bSXiaojian Du #undef pr_debug
48f46a221bSXiaojian Du
4943195162SAndré Almeida // Registers related to GFXOFF
5043195162SAndré Almeida // addressBlock: smuio_smuio_SmuSmuioDec
5143195162SAndré Almeida // base address: 0x5a000
5243195162SAndré Almeida #define mmSMUIO_GFX_MISC_CNTL 0x00c5
5343195162SAndré Almeida #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
5443195162SAndré Almeida
5543195162SAndré Almeida //SMUIO_GFX_MISC_CNTL
5643195162SAndré Almeida #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0
5743195162SAndré Almeida #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
5843195162SAndré Almeida #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
5943195162SAndré Almeida #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
6043195162SAndré Almeida
61f46a221bSXiaojian Du #define FEATURE_MASK(feature) (1ULL << feature)
62f46a221bSXiaojian Du #define SMC_DPM_FEATURE ( \
63f46a221bSXiaojian Du FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
64f46a221bSXiaojian Du FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
65f46a221bSXiaojian Du FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
66f46a221bSXiaojian Du FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
67f46a221bSXiaojian Du FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
68f46a221bSXiaojian Du FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
69f46a221bSXiaojian Du FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
70f46a221bSXiaojian Du FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
71271ab489SXiaojian Du FEATURE_MASK(FEATURE_GFX_DPM_BIT))
72f46a221bSXiaojian Du
73f46a221bSXiaojian Du static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
74271ab489SXiaojian Du MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
75271ab489SXiaojian Du MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
76271ab489SXiaojian Du MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
77271ab489SXiaojian Du MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
78b58ce1feSJinzhou Su MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
79b58ce1feSJinzhou Su MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
80271ab489SXiaojian Du MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
81271ab489SXiaojian Du MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
82271ab489SXiaojian Du MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
83271ab489SXiaojian Du MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
84a0f55287SXiaomeng Hou MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
85271ab489SXiaojian Du MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
86271ab489SXiaojian Du MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
87271ab489SXiaojian Du MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
88271ab489SXiaojian Du MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
89271ab489SXiaojian Du MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
90271ab489SXiaojian Du MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
91271ab489SXiaojian Du MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
92271ab489SXiaojian Du MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
93271ab489SXiaojian Du MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
94271ab489SXiaojian Du MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
95271ab489SXiaojian Du MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
96271ab489SXiaojian Du MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
97271ab489SXiaojian Du MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
98271ab489SXiaojian Du MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
99271ab489SXiaojian Du MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
100271ab489SXiaojian Du MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
101271ab489SXiaojian Du MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
102271ab489SXiaojian Du MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
103271ab489SXiaojian Du MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
104271ab489SXiaojian Du MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
105271ab489SXiaojian Du MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
106271ab489SXiaojian Du MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
107271ab489SXiaojian Du MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
108271ab489SXiaojian Du MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
109271ab489SXiaojian Du MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
110271ab489SXiaojian Du MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
111271ab489SXiaojian Du MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
112271ab489SXiaojian Du MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
113271ab489SXiaojian Du MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
114271ab489SXiaojian Du MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
115271ab489SXiaojian Du MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
116271ab489SXiaojian Du MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
117271ab489SXiaojian Du MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
118271ab489SXiaojian Du MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
119271ab489SXiaojian Du MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
120271ab489SXiaojian Du MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
121271ab489SXiaojian Du MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
122271ab489SXiaojian Du MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
123271ab489SXiaojian Du MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
124271ab489SXiaojian Du MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
125271ab489SXiaojian Du MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
126271ab489SXiaojian Du MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
127271ab489SXiaojian Du MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
128271ab489SXiaojian Du MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
129271ab489SXiaojian Du MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
130271ab489SXiaojian Du MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
131271ab489SXiaojian Du MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
132271ab489SXiaojian Du MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
133271ab489SXiaojian Du MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
134271ab489SXiaojian Du MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
135271ab489SXiaojian Du MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
136eefdf047SJinzhou Su MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0),
137ae07970aSXiaomeng Hou MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0),
138ae07970aSXiaomeng Hou MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0),
139ae07970aSXiaomeng Hou MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0),
140ae07970aSXiaomeng Hou MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0),
1411ed5a845SAndré Almeida MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0),
1421ed5a845SAndré Almeida MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0),
1431ed5a845SAndré Almeida MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0),
144f46a221bSXiaojian Du };
145f46a221bSXiaojian Du
146f46a221bSXiaojian Du static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
147f46a221bSXiaojian Du FEA_MAP(PPT),
148f46a221bSXiaojian Du FEA_MAP(TDC),
149f46a221bSXiaojian Du FEA_MAP(THERMAL),
150f46a221bSXiaojian Du FEA_MAP(DS_GFXCLK),
151f46a221bSXiaojian Du FEA_MAP(DS_SOCCLK),
152f46a221bSXiaojian Du FEA_MAP(DS_LCLK),
153f46a221bSXiaojian Du FEA_MAP(DS_FCLK),
154f46a221bSXiaojian Du FEA_MAP(DS_MP1CLK),
155f46a221bSXiaojian Du FEA_MAP(DS_MP0CLK),
156f46a221bSXiaojian Du FEA_MAP(ATHUB_PG),
157f46a221bSXiaojian Du FEA_MAP(CCLK_DPM),
158f46a221bSXiaojian Du FEA_MAP(FAN_CONTROLLER),
159f46a221bSXiaojian Du FEA_MAP(ULV),
160f46a221bSXiaojian Du FEA_MAP(VCN_DPM),
161f46a221bSXiaojian Du FEA_MAP(LCLK_DPM),
162f46a221bSXiaojian Du FEA_MAP(SHUBCLK_DPM),
163f46a221bSXiaojian Du FEA_MAP(DCFCLK_DPM),
164f46a221bSXiaojian Du FEA_MAP(DS_DCFCLK),
165f46a221bSXiaojian Du FEA_MAP(S0I2),
166f46a221bSXiaojian Du FEA_MAP(SMU_LOW_POWER),
167f46a221bSXiaojian Du FEA_MAP(GFX_DEM),
168f46a221bSXiaojian Du FEA_MAP(PSI),
169f46a221bSXiaojian Du FEA_MAP(PROCHOT),
170f46a221bSXiaojian Du FEA_MAP(CPUOFF),
171f46a221bSXiaojian Du FEA_MAP(STAPM),
172f46a221bSXiaojian Du FEA_MAP(S0I3),
173f46a221bSXiaojian Du FEA_MAP(DF_CSTATES),
174f46a221bSXiaojian Du FEA_MAP(PERF_LIMIT),
175f46a221bSXiaojian Du FEA_MAP(CORE_DLDO),
176f46a221bSXiaojian Du FEA_MAP(RSMU_LOW_POWER),
177f46a221bSXiaojian Du FEA_MAP(SMN_LOW_POWER),
178f46a221bSXiaojian Du FEA_MAP(THM_LOW_POWER),
179f46a221bSXiaojian Du FEA_MAP(SMUIO_LOW_POWER),
180f46a221bSXiaojian Du FEA_MAP(MP1_LOW_POWER),
181f46a221bSXiaojian Du FEA_MAP(DS_VCN),
182f46a221bSXiaojian Du FEA_MAP(CPPC),
183f46a221bSXiaojian Du FEA_MAP(OS_CSTATES),
184f46a221bSXiaojian Du FEA_MAP(ISP_DPM),
185f46a221bSXiaojian Du FEA_MAP(A55_DPM),
186f46a221bSXiaojian Du FEA_MAP(CVIP_DSP_DPM),
187f46a221bSXiaojian Du FEA_MAP(MSMU_LOW_POWER),
18854800b58SXiaojian Du FEA_MAP_REVERSE(SOCCLK),
18954800b58SXiaojian Du FEA_MAP_REVERSE(FCLK),
19054800b58SXiaojian Du FEA_MAP_HALF_REVERSE(GFX),
191f46a221bSXiaojian Du };
192f46a221bSXiaojian Du
193f46a221bSXiaojian Du static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
194f46a221bSXiaojian Du TAB_MAP_VALID(WATERMARKS),
195f46a221bSXiaojian Du TAB_MAP_VALID(SMU_METRICS),
196f46a221bSXiaojian Du TAB_MAP_VALID(CUSTOM_DPM),
197f46a221bSXiaojian Du TAB_MAP_VALID(DPMCLOCKS),
198f46a221bSXiaojian Du };
199f46a221bSXiaojian Du
200f727ebebSXiaojian Du static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
201f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
202f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
203f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
204f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
205f727ebebSXiaojian Du WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
206dc622367SPerry Yuan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT),
207dc622367SPerry Yuan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT),
208f727ebebSXiaojian Du };
209f727ebebSXiaojian Du
2107cab3cffSGraham Sider static const uint8_t vangogh_throttler_map[] = {
2117cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
2127cab3cffSGraham Sider [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
2137cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
2147cab3cffSGraham Sider [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
2157cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
2167cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
2177cab3cffSGraham Sider [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
2187cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
2197cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
2207cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
2217cab3cffSGraham Sider [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
2227cab3cffSGraham Sider };
2237cab3cffSGraham Sider
vangogh_tables_init(struct smu_context * smu)224f46a221bSXiaojian Du static int vangogh_tables_init(struct smu_context *smu)
225f46a221bSXiaojian Du {
226f46a221bSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
227f46a221bSXiaojian Du struct smu_table *tables = smu_table->tables;
22886c8236eSXiaojian Du uint32_t if_version;
2290d6516efSLi Ma uint32_t smu_version;
23086c8236eSXiaojian Du uint32_t ret = 0;
23186c8236eSXiaojian Du
2320d6516efSLi Ma ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
23386c8236eSXiaojian Du if (ret) {
2340d6516efSLi Ma return ret;
23586c8236eSXiaojian Du }
236f46a221bSXiaojian Du
237f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
238f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
239f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
240f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
241f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
242f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
243f46a221bSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
244f46a221bSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
24586c8236eSXiaojian Du
24686c8236eSXiaojian Du if (if_version < 0x3) {
24786c8236eSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_legacy_t),
24886c8236eSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
24986c8236eSXiaojian Du smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_legacy_t), GFP_KERNEL);
25086c8236eSXiaojian Du } else {
25186c8236eSXiaojian Du SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
25286c8236eSXiaojian Du PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
253f46a221bSXiaojian Du smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
25486c8236eSXiaojian Du }
255f46a221bSXiaojian Du if (!smu_table->metrics_table)
256f46a221bSXiaojian Du goto err0_out;
257f46a221bSXiaojian Du smu_table->metrics_time = 0;
258f46a221bSXiaojian Du
2590d6516efSLi Ma if (smu_version >= 0x043F3E00)
2600d6516efSLi Ma smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_3);
2610d6516efSLi Ma else
2627cab3cffSGraham Sider smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
263f46a221bSXiaojian Du smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
264f46a221bSXiaojian Du if (!smu_table->gpu_metrics_table)
265f46a221bSXiaojian Du goto err1_out;
266f46a221bSXiaojian Du
267f46a221bSXiaojian Du smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
268f46a221bSXiaojian Du if (!smu_table->watermarks_table)
269f46a221bSXiaojian Du goto err2_out;
270f46a221bSXiaojian Du
271c98ee897SXiaojian Du smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
272c98ee897SXiaojian Du if (!smu_table->clocks_table)
273c98ee897SXiaojian Du goto err3_out;
274c98ee897SXiaojian Du
275f46a221bSXiaojian Du return 0;
276f46a221bSXiaojian Du
277c98ee897SXiaojian Du err3_out:
278a5467ebdSChristophe JAILLET kfree(smu_table->watermarks_table);
279f46a221bSXiaojian Du err2_out:
280f46a221bSXiaojian Du kfree(smu_table->gpu_metrics_table);
281f46a221bSXiaojian Du err1_out:
282f46a221bSXiaojian Du kfree(smu_table->metrics_table);
283f46a221bSXiaojian Du err0_out:
284f46a221bSXiaojian Du return -ENOMEM;
285f46a221bSXiaojian Du }
286f46a221bSXiaojian Du
vangogh_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)28786c8236eSXiaojian Du static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
288271ab489SXiaojian Du MetricsMember_t member,
289271ab489SXiaojian Du uint32_t *value)
290271ab489SXiaojian Du {
291271ab489SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
29286c8236eSXiaojian Du SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
293271ab489SXiaojian Du int ret = 0;
294271ab489SXiaojian Du
295da11407fSEvan Quan ret = smu_cmn_get_metrics_table(smu,
296271ab489SXiaojian Du NULL,
297271ab489SXiaojian Du false);
298da11407fSEvan Quan if (ret)
299271ab489SXiaojian Du return ret;
300271ab489SXiaojian Du
301271ab489SXiaojian Du switch (member) {
302a99a5116SXiaojian Du case METRICS_CURR_GFXCLK:
303271ab489SXiaojian Du *value = metrics->GfxclkFrequency;
304271ab489SXiaojian Du break;
305271ab489SXiaojian Du case METRICS_AVERAGE_SOCCLK:
306271ab489SXiaojian Du *value = metrics->SocclkFrequency;
307271ab489SXiaojian Du break;
308f02c7336SXiaojian Du case METRICS_AVERAGE_VCLK:
309f02c7336SXiaojian Du *value = metrics->VclkFrequency;
310f02c7336SXiaojian Du break;
311f02c7336SXiaojian Du case METRICS_AVERAGE_DCLK:
312f02c7336SXiaojian Du *value = metrics->DclkFrequency;
313f02c7336SXiaojian Du break;
314a99a5116SXiaojian Du case METRICS_CURR_UCLK:
315271ab489SXiaojian Du *value = metrics->MemclkFrequency;
316271ab489SXiaojian Du break;
317271ab489SXiaojian Du case METRICS_AVERAGE_GFXACTIVITY:
318271ab489SXiaojian Du *value = metrics->GfxActivity / 100;
319271ab489SXiaojian Du break;
320271ab489SXiaojian Du case METRICS_AVERAGE_VCNACTIVITY:
321271ab489SXiaojian Du *value = metrics->UvdActivity;
322271ab489SXiaojian Du break;
323271ab489SXiaojian Du case METRICS_AVERAGE_SOCKETPOWER:
32423289a22SXiaojian Du *value = (metrics->CurrentSocketPower << 8) /
32523289a22SXiaojian Du 1000 ;
326271ab489SXiaojian Du break;
327271ab489SXiaojian Du case METRICS_TEMPERATURE_EDGE:
328271ab489SXiaojian Du *value = metrics->GfxTemperature / 100 *
329271ab489SXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
330271ab489SXiaojian Du break;
331271ab489SXiaojian Du case METRICS_TEMPERATURE_HOTSPOT:
332271ab489SXiaojian Du *value = metrics->SocTemperature / 100 *
333271ab489SXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
334271ab489SXiaojian Du break;
335271ab489SXiaojian Du case METRICS_THROTTLER_STATUS:
336271ab489SXiaojian Du *value = metrics->ThrottlerStatus;
337271ab489SXiaojian Du break;
3382139d12bSAlex Deucher case METRICS_VOLTAGE_VDDGFX:
3392139d12bSAlex Deucher *value = metrics->Voltage[2];
3402139d12bSAlex Deucher break;
3412139d12bSAlex Deucher case METRICS_VOLTAGE_VDDSOC:
3422139d12bSAlex Deucher *value = metrics->Voltage[1];
3432139d12bSAlex Deucher break;
344517cb957SHuang Rui case METRICS_AVERAGE_CPUCLK:
345517cb957SHuang Rui memcpy(value, &metrics->CoreFrequency[0],
3464aef0ebcSHuang Rui smu->cpu_core_num * sizeof(uint16_t));
347517cb957SHuang Rui break;
348271ab489SXiaojian Du default:
349271ab489SXiaojian Du *value = UINT_MAX;
350271ab489SXiaojian Du break;
351271ab489SXiaojian Du }
352271ab489SXiaojian Du
353271ab489SXiaojian Du return ret;
354271ab489SXiaojian Du }
355271ab489SXiaojian Du
vangogh_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)35686c8236eSXiaojian Du static int vangogh_get_smu_metrics_data(struct smu_context *smu,
35786c8236eSXiaojian Du MetricsMember_t member,
35886c8236eSXiaojian Du uint32_t *value)
35986c8236eSXiaojian Du {
36086c8236eSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
36186c8236eSXiaojian Du SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
36286c8236eSXiaojian Du int ret = 0;
36386c8236eSXiaojian Du
364da11407fSEvan Quan ret = smu_cmn_get_metrics_table(smu,
36586c8236eSXiaojian Du NULL,
36686c8236eSXiaojian Du false);
367da11407fSEvan Quan if (ret)
36886c8236eSXiaojian Du return ret;
36986c8236eSXiaojian Du
37086c8236eSXiaojian Du switch (member) {
371a99a5116SXiaojian Du case METRICS_CURR_GFXCLK:
37286c8236eSXiaojian Du *value = metrics->Current.GfxclkFrequency;
37386c8236eSXiaojian Du break;
37486c8236eSXiaojian Du case METRICS_AVERAGE_SOCCLK:
37586c8236eSXiaojian Du *value = metrics->Current.SocclkFrequency;
37686c8236eSXiaojian Du break;
37786c8236eSXiaojian Du case METRICS_AVERAGE_VCLK:
37886c8236eSXiaojian Du *value = metrics->Current.VclkFrequency;
37986c8236eSXiaojian Du break;
38086c8236eSXiaojian Du case METRICS_AVERAGE_DCLK:
38186c8236eSXiaojian Du *value = metrics->Current.DclkFrequency;
38286c8236eSXiaojian Du break;
383a99a5116SXiaojian Du case METRICS_CURR_UCLK:
38486c8236eSXiaojian Du *value = metrics->Current.MemclkFrequency;
38586c8236eSXiaojian Du break;
38686c8236eSXiaojian Du case METRICS_AVERAGE_GFXACTIVITY:
38786c8236eSXiaojian Du *value = metrics->Current.GfxActivity;
38886c8236eSXiaojian Du break;
38986c8236eSXiaojian Du case METRICS_AVERAGE_VCNACTIVITY:
39086c8236eSXiaojian Du *value = metrics->Current.UvdActivity;
39186c8236eSXiaojian Du break;
39286c8236eSXiaojian Du case METRICS_AVERAGE_SOCKETPOWER:
39347f1724dSMario Limonciello *value = (metrics->Average.CurrentSocketPower << 8) /
39447f1724dSMario Limonciello 1000;
39547f1724dSMario Limonciello break;
39647f1724dSMario Limonciello case METRICS_CURR_SOCKETPOWER:
39786c8236eSXiaojian Du *value = (metrics->Current.CurrentSocketPower << 8) /
39886c8236eSXiaojian Du 1000;
39986c8236eSXiaojian Du break;
40086c8236eSXiaojian Du case METRICS_TEMPERATURE_EDGE:
40186c8236eSXiaojian Du *value = metrics->Current.GfxTemperature / 100 *
40286c8236eSXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
40386c8236eSXiaojian Du break;
40486c8236eSXiaojian Du case METRICS_TEMPERATURE_HOTSPOT:
40586c8236eSXiaojian Du *value = metrics->Current.SocTemperature / 100 *
40686c8236eSXiaojian Du SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
40786c8236eSXiaojian Du break;
40886c8236eSXiaojian Du case METRICS_THROTTLER_STATUS:
40986c8236eSXiaojian Du *value = metrics->Current.ThrottlerStatus;
41086c8236eSXiaojian Du break;
41186c8236eSXiaojian Du case METRICS_VOLTAGE_VDDGFX:
41286c8236eSXiaojian Du *value = metrics->Current.Voltage[2];
41386c8236eSXiaojian Du break;
41486c8236eSXiaojian Du case METRICS_VOLTAGE_VDDSOC:
41586c8236eSXiaojian Du *value = metrics->Current.Voltage[1];
41686c8236eSXiaojian Du break;
41786c8236eSXiaojian Du case METRICS_AVERAGE_CPUCLK:
41886c8236eSXiaojian Du memcpy(value, &metrics->Current.CoreFrequency[0],
41986c8236eSXiaojian Du smu->cpu_core_num * sizeof(uint16_t));
42086c8236eSXiaojian Du break;
42186c8236eSXiaojian Du default:
42286c8236eSXiaojian Du *value = UINT_MAX;
42386c8236eSXiaojian Du break;
42486c8236eSXiaojian Du }
42586c8236eSXiaojian Du
42686c8236eSXiaojian Du return ret;
42786c8236eSXiaojian Du }
42886c8236eSXiaojian Du
vangogh_common_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)42986c8236eSXiaojian Du static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
43086c8236eSXiaojian Du MetricsMember_t member,
43186c8236eSXiaojian Du uint32_t *value)
43286c8236eSXiaojian Du {
43386c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev;
43486c8236eSXiaojian Du uint32_t if_version;
43586c8236eSXiaojian Du int ret = 0;
43686c8236eSXiaojian Du
43786c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
43886c8236eSXiaojian Du if (ret) {
43986c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n");
44086c8236eSXiaojian Du return ret;
44186c8236eSXiaojian Du }
44286c8236eSXiaojian Du
44386c8236eSXiaojian Du if (if_version < 0x3)
44486c8236eSXiaojian Du ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
44586c8236eSXiaojian Du else
44686c8236eSXiaojian Du ret = vangogh_get_smu_metrics_data(smu, member, value);
44786c8236eSXiaojian Du
44886c8236eSXiaojian Du return ret;
44986c8236eSXiaojian Du }
45086c8236eSXiaojian Du
vangogh_allocate_dpm_context(struct smu_context * smu)451f46a221bSXiaojian Du static int vangogh_allocate_dpm_context(struct smu_context *smu)
452f46a221bSXiaojian Du {
453f46a221bSXiaojian Du struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
454f46a221bSXiaojian Du
455f46a221bSXiaojian Du smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
456f46a221bSXiaojian Du GFP_KERNEL);
457f46a221bSXiaojian Du if (!smu_dpm->dpm_context)
458f46a221bSXiaojian Du return -ENOMEM;
459f46a221bSXiaojian Du
460f46a221bSXiaojian Du smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
461f46a221bSXiaojian Du
462f46a221bSXiaojian Du return 0;
463f46a221bSXiaojian Du }
464f46a221bSXiaojian Du
vangogh_init_smc_tables(struct smu_context * smu)465f46a221bSXiaojian Du static int vangogh_init_smc_tables(struct smu_context *smu)
466f46a221bSXiaojian Du {
467f46a221bSXiaojian Du int ret = 0;
468f46a221bSXiaojian Du
469f46a221bSXiaojian Du ret = vangogh_tables_init(smu);
470f46a221bSXiaojian Du if (ret)
471f46a221bSXiaojian Du return ret;
472f46a221bSXiaojian Du
473f46a221bSXiaojian Du ret = vangogh_allocate_dpm_context(smu);
474f46a221bSXiaojian Du if (ret)
475f46a221bSXiaojian Du return ret;
476f46a221bSXiaojian Du
4774aef0ebcSHuang Rui #ifdef CONFIG_X86
4784aef0ebcSHuang Rui /* AMD x86 APU only */
4794aef0ebcSHuang Rui smu->cpu_core_num = boot_cpu_data.x86_max_cores;
4804aef0ebcSHuang Rui #else
4814aef0ebcSHuang Rui smu->cpu_core_num = 4;
4824aef0ebcSHuang Rui #endif
4834aef0ebcSHuang Rui
484f46a221bSXiaojian Du return smu_v11_0_init_smc_tables(smu);
485f46a221bSXiaojian Du }
486f46a221bSXiaojian Du
vangogh_dpm_set_vcn_enable(struct smu_context * smu,bool enable)487f46a221bSXiaojian Du static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
488f46a221bSXiaojian Du {
489f46a221bSXiaojian Du int ret = 0;
490f46a221bSXiaojian Du
491f46a221bSXiaojian Du if (enable) {
492f46a221bSXiaojian Du /* vcn dpm on is a prerequisite for vcn power gate messages */
493f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
494f46a221bSXiaojian Du if (ret)
495f46a221bSXiaojian Du return ret;
496f46a221bSXiaojian Du } else {
497f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
498f46a221bSXiaojian Du if (ret)
499f46a221bSXiaojian Du return ret;
500f46a221bSXiaojian Du }
501f46a221bSXiaojian Du
502f46a221bSXiaojian Du return ret;
503f46a221bSXiaojian Du }
504f46a221bSXiaojian Du
vangogh_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)505f46a221bSXiaojian Du static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
506f46a221bSXiaojian Du {
507f46a221bSXiaojian Du int ret = 0;
508f46a221bSXiaojian Du
509f46a221bSXiaojian Du if (enable) {
510f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
511f46a221bSXiaojian Du if (ret)
512f46a221bSXiaojian Du return ret;
513f46a221bSXiaojian Du } else {
514f46a221bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
515f46a221bSXiaojian Du if (ret)
516f46a221bSXiaojian Du return ret;
517f46a221bSXiaojian Du }
518f46a221bSXiaojian Du
519f46a221bSXiaojian Du return ret;
520f46a221bSXiaojian Du }
521f46a221bSXiaojian Du
vangogh_is_dpm_running(struct smu_context * smu)522f46a221bSXiaojian Du static bool vangogh_is_dpm_running(struct smu_context *smu)
523f46a221bSXiaojian Du {
5241c0f0430SAlex Deucher struct amdgpu_device *adev = smu->adev;
525271ab489SXiaojian Du int ret = 0;
526271ab489SXiaojian Du uint64_t feature_enabled;
527f46a221bSXiaojian Du
5281c0f0430SAlex Deucher /* we need to re-init after suspend so return false */
5291c0f0430SAlex Deucher if (adev->in_suspend)
5301c0f0430SAlex Deucher return false;
5311c0f0430SAlex Deucher
5322d282665SEvan Quan ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
533271ab489SXiaojian Du
534271ab489SXiaojian Du if (ret)
535f46a221bSXiaojian Du return false;
536f46a221bSXiaojian Du
537271ab489SXiaojian Du return !!(feature_enabled & SMC_DPM_FEATURE);
538271ab489SXiaojian Du }
539271ab489SXiaojian Du
vangogh_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)540ae7b32e7SXiaojian Du static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
541ae7b32e7SXiaojian Du uint32_t dpm_level, uint32_t *freq)
542ae7b32e7SXiaojian Du {
543ae7b32e7SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
544ae7b32e7SXiaojian Du
545ae7b32e7SXiaojian Du if (!clk_table || clk_type >= SMU_CLK_COUNT)
546ae7b32e7SXiaojian Du return -EINVAL;
547ae7b32e7SXiaojian Du
548ae7b32e7SXiaojian Du switch (clk_type) {
549ae7b32e7SXiaojian Du case SMU_SOCCLK:
550ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
551ae7b32e7SXiaojian Du return -EINVAL;
552ae7b32e7SXiaojian Du *freq = clk_table->SocClocks[dpm_level];
553ae7b32e7SXiaojian Du break;
554f02c7336SXiaojian Du case SMU_VCLK:
555f02c7336SXiaojian Du if (dpm_level >= clk_table->VcnClkLevelsEnabled)
556f02c7336SXiaojian Du return -EINVAL;
557f02c7336SXiaojian Du *freq = clk_table->VcnClocks[dpm_level].vclk;
558f02c7336SXiaojian Du break;
559f02c7336SXiaojian Du case SMU_DCLK:
560f02c7336SXiaojian Du if (dpm_level >= clk_table->VcnClkLevelsEnabled)
561f02c7336SXiaojian Du return -EINVAL;
562f02c7336SXiaojian Du *freq = clk_table->VcnClocks[dpm_level].dclk;
563f02c7336SXiaojian Du break;
564ae7b32e7SXiaojian Du case SMU_UCLK:
565ae7b32e7SXiaojian Du case SMU_MCLK:
566ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumDfPstatesEnabled)
567ae7b32e7SXiaojian Du return -EINVAL;
568ae7b32e7SXiaojian Du *freq = clk_table->DfPstateTable[dpm_level].memclk;
569ae7b32e7SXiaojian Du
570ae7b32e7SXiaojian Du break;
571ae7b32e7SXiaojian Du case SMU_FCLK:
572ae7b32e7SXiaojian Du if (dpm_level >= clk_table->NumDfPstatesEnabled)
573ae7b32e7SXiaojian Du return -EINVAL;
574ae7b32e7SXiaojian Du *freq = clk_table->DfPstateTable[dpm_level].fclk;
575ae7b32e7SXiaojian Du break;
576ae7b32e7SXiaojian Du default:
577ae7b32e7SXiaojian Du return -EINVAL;
578ae7b32e7SXiaojian Du }
579ae7b32e7SXiaojian Du
580ae7b32e7SXiaojian Du return 0;
581ae7b32e7SXiaojian Du }
582ae7b32e7SXiaojian Du
vangogh_print_legacy_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)58386c8236eSXiaojian Du static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
584c98ee897SXiaojian Du enum smu_clk_type clk_type, char *buf)
585c98ee897SXiaojian Du {
586ae7b32e7SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
58786c8236eSXiaojian Du SmuMetrics_legacy_t metrics;
588d7379efaSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
58963b9acdfSTim Huang int i, idx, size = 0, ret = 0;
590ae7b32e7SXiaojian Du uint32_t cur_value = 0, value = 0, count = 0;
591ae7b32e7SXiaojian Du bool cur_value_match_level = false;
592ae7b32e7SXiaojian Du
593ae7b32e7SXiaojian Du memset(&metrics, 0, sizeof(metrics));
594ae7b32e7SXiaojian Du
595ae7b32e7SXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, false);
596ae7b32e7SXiaojian Du if (ret)
597ae7b32e7SXiaojian Du return ret;
598c98ee897SXiaojian Du
5998f48ba30SLang Yu smu_cmn_get_sysfs_buf(&buf, &size);
6008f48ba30SLang Yu
601c98ee897SXiaojian Du switch (clk_type) {
602c98ee897SXiaojian Du case SMU_OD_SCLK:
603d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
6048f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
605fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
606c98ee897SXiaojian Du (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
607fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
608c98ee897SXiaojian Du (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
609c98ee897SXiaojian Du }
610c98ee897SXiaojian Du break;
6110d90d0ddSHuang Rui case SMU_OD_CCLK:
612d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
6138f48ba30SLang Yu size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
614fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
6150d90d0ddSHuang Rui (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
616fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
6170d90d0ddSHuang Rui (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
6180d90d0ddSHuang Rui }
6190d90d0ddSHuang Rui break;
620c98ee897SXiaojian Du case SMU_OD_RANGE:
621d7379efaSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
6228f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
623fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
624c98ee897SXiaojian Du smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
625fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
6260d90d0ddSHuang Rui smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
627c98ee897SXiaojian Du }
628c98ee897SXiaojian Du break;
629ae7b32e7SXiaojian Du case SMU_SOCCLK:
630ae7b32e7SXiaojian Du /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
631ae7b32e7SXiaojian Du count = clk_table->NumSocClkLevelsEnabled;
632ae7b32e7SXiaojian Du cur_value = metrics.SocclkFrequency;
633ae7b32e7SXiaojian Du break;
634f02c7336SXiaojian Du case SMU_VCLK:
635f02c7336SXiaojian Du count = clk_table->VcnClkLevelsEnabled;
636f02c7336SXiaojian Du cur_value = metrics.VclkFrequency;
637f02c7336SXiaojian Du break;
638f02c7336SXiaojian Du case SMU_DCLK:
639f02c7336SXiaojian Du count = clk_table->VcnClkLevelsEnabled;
640f02c7336SXiaojian Du cur_value = metrics.DclkFrequency;
641f02c7336SXiaojian Du break;
642ae7b32e7SXiaojian Du case SMU_MCLK:
643ae7b32e7SXiaojian Du count = clk_table->NumDfPstatesEnabled;
644ae7b32e7SXiaojian Du cur_value = metrics.MemclkFrequency;
645ae7b32e7SXiaojian Du break;
646ae7b32e7SXiaojian Du case SMU_FCLK:
647ae7b32e7SXiaojian Du count = clk_table->NumDfPstatesEnabled;
648ae7b32e7SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
649ae7b32e7SXiaojian Du if (ret)
650ae7b32e7SXiaojian Du return ret;
651ae7b32e7SXiaojian Du break;
652ae7b32e7SXiaojian Du default:
653ae7b32e7SXiaojian Du break;
654ae7b32e7SXiaojian Du }
655ae7b32e7SXiaojian Du
656ae7b32e7SXiaojian Du switch (clk_type) {
657ae7b32e7SXiaojian Du case SMU_SOCCLK:
658f02c7336SXiaojian Du case SMU_VCLK:
659f02c7336SXiaojian Du case SMU_DCLK:
660ae7b32e7SXiaojian Du case SMU_MCLK:
661ae7b32e7SXiaojian Du case SMU_FCLK:
662ae7b32e7SXiaojian Du for (i = 0; i < count; i++) {
66363b9acdfSTim Huang idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
66463b9acdfSTim Huang ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
665ae7b32e7SXiaojian Du if (ret)
666ae7b32e7SXiaojian Du return ret;
667ae7b32e7SXiaojian Du if (!value)
668ae7b32e7SXiaojian Du continue;
669fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
670ae7b32e7SXiaojian Du cur_value == value ? "*" : "");
671ae7b32e7SXiaojian Du if (cur_value == value)
672ae7b32e7SXiaojian Du cur_value_match_level = true;
673ae7b32e7SXiaojian Du }
674ae7b32e7SXiaojian Du
675ae7b32e7SXiaojian Du if (!cur_value_match_level)
676fe14c285SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
677ae7b32e7SXiaojian Du break;
678c98ee897SXiaojian Du default:
679c98ee897SXiaojian Du break;
680c98ee897SXiaojian Du }
681c98ee897SXiaojian Du
682c98ee897SXiaojian Du return size;
683c98ee897SXiaojian Du }
684c98ee897SXiaojian Du
vangogh_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)68586c8236eSXiaojian Du static int vangogh_print_clk_levels(struct smu_context *smu,
68686c8236eSXiaojian Du enum smu_clk_type clk_type, char *buf)
68786c8236eSXiaojian Du {
68886c8236eSXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
68986c8236eSXiaojian Du SmuMetrics_t metrics;
69086c8236eSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
69163b9acdfSTim Huang int i, idx, size = 0, ret = 0;
69286c8236eSXiaojian Du uint32_t cur_value = 0, value = 0, count = 0;
69386c8236eSXiaojian Du bool cur_value_match_level = false;
69448c19a95SPerry Yuan uint32_t min, max;
69586c8236eSXiaojian Du
69686c8236eSXiaojian Du memset(&metrics, 0, sizeof(metrics));
69786c8236eSXiaojian Du
69886c8236eSXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, false);
69986c8236eSXiaojian Du if (ret)
70086c8236eSXiaojian Du return ret;
70186c8236eSXiaojian Du
7028f48ba30SLang Yu smu_cmn_get_sysfs_buf(&buf, &size);
7038f48ba30SLang Yu
70486c8236eSXiaojian Du switch (clk_type) {
70586c8236eSXiaojian Du case SMU_OD_SCLK:
70686c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
7078f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
708fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
70986c8236eSXiaojian Du (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
710fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
71186c8236eSXiaojian Du (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
71286c8236eSXiaojian Du }
71386c8236eSXiaojian Du break;
71486c8236eSXiaojian Du case SMU_OD_CCLK:
71586c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
7168f48ba30SLang Yu size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
717fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
71886c8236eSXiaojian Du (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
719fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
72086c8236eSXiaojian Du (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
72186c8236eSXiaojian Du }
72286c8236eSXiaojian Du break;
72386c8236eSXiaojian Du case SMU_OD_RANGE:
72486c8236eSXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
7258f48ba30SLang Yu size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
726fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
72786c8236eSXiaojian Du smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
728fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
72986c8236eSXiaojian Du smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
73086c8236eSXiaojian Du }
73186c8236eSXiaojian Du break;
73286c8236eSXiaojian Du case SMU_SOCCLK:
73386c8236eSXiaojian Du /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
73486c8236eSXiaojian Du count = clk_table->NumSocClkLevelsEnabled;
73586c8236eSXiaojian Du cur_value = metrics.Current.SocclkFrequency;
73686c8236eSXiaojian Du break;
73786c8236eSXiaojian Du case SMU_VCLK:
73886c8236eSXiaojian Du count = clk_table->VcnClkLevelsEnabled;
73986c8236eSXiaojian Du cur_value = metrics.Current.VclkFrequency;
74086c8236eSXiaojian Du break;
74186c8236eSXiaojian Du case SMU_DCLK:
74286c8236eSXiaojian Du count = clk_table->VcnClkLevelsEnabled;
74386c8236eSXiaojian Du cur_value = metrics.Current.DclkFrequency;
74486c8236eSXiaojian Du break;
74586c8236eSXiaojian Du case SMU_MCLK:
74686c8236eSXiaojian Du count = clk_table->NumDfPstatesEnabled;
74786c8236eSXiaojian Du cur_value = metrics.Current.MemclkFrequency;
74886c8236eSXiaojian Du break;
74986c8236eSXiaojian Du case SMU_FCLK:
75086c8236eSXiaojian Du count = clk_table->NumDfPstatesEnabled;
75186c8236eSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
75286c8236eSXiaojian Du if (ret)
75386c8236eSXiaojian Du return ret;
75486c8236eSXiaojian Du break;
75548c19a95SPerry Yuan case SMU_GFXCLK:
75648c19a95SPerry Yuan case SMU_SCLK:
75748c19a95SPerry Yuan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
75848c19a95SPerry Yuan if (ret) {
75948c19a95SPerry Yuan return ret;
76048c19a95SPerry Yuan }
76148c19a95SPerry Yuan break;
76286c8236eSXiaojian Du default:
76386c8236eSXiaojian Du break;
76486c8236eSXiaojian Du }
76586c8236eSXiaojian Du
76686c8236eSXiaojian Du switch (clk_type) {
76786c8236eSXiaojian Du case SMU_SOCCLK:
76886c8236eSXiaojian Du case SMU_VCLK:
76986c8236eSXiaojian Du case SMU_DCLK:
77086c8236eSXiaojian Du case SMU_MCLK:
77186c8236eSXiaojian Du case SMU_FCLK:
77286c8236eSXiaojian Du for (i = 0; i < count; i++) {
77363b9acdfSTim Huang idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
77463b9acdfSTim Huang ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
77586c8236eSXiaojian Du if (ret)
77686c8236eSXiaojian Du return ret;
77786c8236eSXiaojian Du if (!value)
77886c8236eSXiaojian Du continue;
779fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
78086c8236eSXiaojian Du cur_value == value ? "*" : "");
78186c8236eSXiaojian Du if (cur_value == value)
78286c8236eSXiaojian Du cur_value_match_level = true;
78386c8236eSXiaojian Du }
78486c8236eSXiaojian Du
78586c8236eSXiaojian Du if (!cur_value_match_level)
786fe14c285SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
78786c8236eSXiaojian Du break;
78848c19a95SPerry Yuan case SMU_GFXCLK:
78948c19a95SPerry Yuan case SMU_SCLK:
79048c19a95SPerry Yuan min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
79148c19a95SPerry Yuan max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
79248c19a95SPerry Yuan if (cur_value == max)
79348c19a95SPerry Yuan i = 2;
79448c19a95SPerry Yuan else if (cur_value == min)
79548c19a95SPerry Yuan i = 0;
79648c19a95SPerry Yuan else
79748c19a95SPerry Yuan i = 1;
79848c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
79948c19a95SPerry Yuan i == 0 ? "*" : "");
80048c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
80148c19a95SPerry Yuan i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
80248c19a95SPerry Yuan i == 1 ? "*" : "");
80348c19a95SPerry Yuan size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
80448c19a95SPerry Yuan i == 2 ? "*" : "");
80548c19a95SPerry Yuan break;
80686c8236eSXiaojian Du default:
80786c8236eSXiaojian Du break;
80886c8236eSXiaojian Du }
80986c8236eSXiaojian Du
81086c8236eSXiaojian Du return size;
81186c8236eSXiaojian Du }
81286c8236eSXiaojian Du
vangogh_common_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)81386c8236eSXiaojian Du static int vangogh_common_print_clk_levels(struct smu_context *smu,
81486c8236eSXiaojian Du enum smu_clk_type clk_type, char *buf)
81586c8236eSXiaojian Du {
81686c8236eSXiaojian Du struct amdgpu_device *adev = smu->adev;
81786c8236eSXiaojian Du uint32_t if_version;
81886c8236eSXiaojian Du int ret = 0;
81986c8236eSXiaojian Du
82086c8236eSXiaojian Du ret = smu_cmn_get_smc_version(smu, &if_version, NULL);
82186c8236eSXiaojian Du if (ret) {
82286c8236eSXiaojian Du dev_err(adev->dev, "Failed to get smu if version!\n");
82386c8236eSXiaojian Du return ret;
82486c8236eSXiaojian Du }
82586c8236eSXiaojian Du
82686c8236eSXiaojian Du if (if_version < 0x3)
82786c8236eSXiaojian Du ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
82886c8236eSXiaojian Du else
82986c8236eSXiaojian Du ret = vangogh_print_clk_levels(smu, clk_type, buf);
83086c8236eSXiaojian Du
83186c8236eSXiaojian Du return ret;
83286c8236eSXiaojian Du }
83386c8236eSXiaojian Du
vangogh_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * vclk_mask,uint32_t * dclk_mask,uint32_t * mclk_mask,uint32_t * fclk_mask,uint32_t * soc_mask)834d0e4e112SXiaojian Du static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
835d0e4e112SXiaojian Du enum amd_dpm_forced_level level,
836d0e4e112SXiaojian Du uint32_t *vclk_mask,
837d0e4e112SXiaojian Du uint32_t *dclk_mask,
838d0e4e112SXiaojian Du uint32_t *mclk_mask,
839d0e4e112SXiaojian Du uint32_t *fclk_mask,
840d0e4e112SXiaojian Du uint32_t *soc_mask)
841d0e4e112SXiaojian Du {
842d0e4e112SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
843d0e4e112SXiaojian Du
844307f049bSXiaojian Du if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
845d0e4e112SXiaojian Du if (mclk_mask)
846d0e4e112SXiaojian Du *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
847307f049bSXiaojian Du
848d0e4e112SXiaojian Du if (fclk_mask)
849d0e4e112SXiaojian Du *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
850307f049bSXiaojian Du
851307f049bSXiaojian Du if (soc_mask)
852307f049bSXiaojian Du *soc_mask = 0;
853d0e4e112SXiaojian Du } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
854d0e4e112SXiaojian Du if (mclk_mask)
855d0e4e112SXiaojian Du *mclk_mask = 0;
856307f049bSXiaojian Du
857d0e4e112SXiaojian Du if (fclk_mask)
858d0e4e112SXiaojian Du *fclk_mask = 0;
859d0e4e112SXiaojian Du
860d0e4e112SXiaojian Du if (soc_mask)
861307f049bSXiaojian Du *soc_mask = 1;
862307f049bSXiaojian Du
863307f049bSXiaojian Du if (vclk_mask)
864307f049bSXiaojian Du *vclk_mask = 1;
865307f049bSXiaojian Du
866307f049bSXiaojian Du if (dclk_mask)
867307f049bSXiaojian Du *dclk_mask = 1;
868307f049bSXiaojian Du } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
869307f049bSXiaojian Du if (mclk_mask)
870307f049bSXiaojian Du *mclk_mask = 0;
871307f049bSXiaojian Du
872307f049bSXiaojian Du if (fclk_mask)
873307f049bSXiaojian Du *fclk_mask = 0;
874307f049bSXiaojian Du
875307f049bSXiaojian Du if (soc_mask)
876307f049bSXiaojian Du *soc_mask = 1;
877307f049bSXiaojian Du
878307f049bSXiaojian Du if (vclk_mask)
879307f049bSXiaojian Du *vclk_mask = 1;
880307f049bSXiaojian Du
881307f049bSXiaojian Du if (dclk_mask)
882307f049bSXiaojian Du *dclk_mask = 1;
883d0e4e112SXiaojian Du }
884d0e4e112SXiaojian Du
885d0e4e112SXiaojian Du return 0;
886d0e4e112SXiaojian Du }
887d0e4e112SXiaojian Du
vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)8888f8150faSSouptick Joarder static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
889d0e4e112SXiaojian Du enum smu_clk_type clk_type)
890d0e4e112SXiaojian Du {
891d0e4e112SXiaojian Du enum smu_feature_mask feature_id = 0;
892d0e4e112SXiaojian Du
893d0e4e112SXiaojian Du switch (clk_type) {
894d0e4e112SXiaojian Du case SMU_MCLK:
895d0e4e112SXiaojian Du case SMU_UCLK:
896d0e4e112SXiaojian Du case SMU_FCLK:
897d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_FCLK_BIT;
898d0e4e112SXiaojian Du break;
899d0e4e112SXiaojian Du case SMU_GFXCLK:
900d0e4e112SXiaojian Du case SMU_SCLK:
901d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
902d0e4e112SXiaojian Du break;
903d0e4e112SXiaojian Du case SMU_SOCCLK:
904d0e4e112SXiaojian Du feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
905d0e4e112SXiaojian Du break;
906d0e4e112SXiaojian Du case SMU_VCLK:
907d0e4e112SXiaojian Du case SMU_DCLK:
908d0e4e112SXiaojian Du feature_id = SMU_FEATURE_VCN_DPM_BIT;
909d0e4e112SXiaojian Du break;
910d0e4e112SXiaojian Du default:
911d0e4e112SXiaojian Du return true;
912d0e4e112SXiaojian Du }
913d0e4e112SXiaojian Du
914d0e4e112SXiaojian Du if (!smu_cmn_feature_is_enabled(smu, feature_id))
915d0e4e112SXiaojian Du return false;
916d0e4e112SXiaojian Du
917d0e4e112SXiaojian Du return true;
918d0e4e112SXiaojian Du }
919d0e4e112SXiaojian Du
vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)920d0e4e112SXiaojian Du static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
921d0e4e112SXiaojian Du enum smu_clk_type clk_type,
922d0e4e112SXiaojian Du uint32_t *min,
923d0e4e112SXiaojian Du uint32_t *max)
924d0e4e112SXiaojian Du {
925d0e4e112SXiaojian Du int ret = 0;
926d0e4e112SXiaojian Du uint32_t soc_mask;
927d0e4e112SXiaojian Du uint32_t vclk_mask;
928d0e4e112SXiaojian Du uint32_t dclk_mask;
929d0e4e112SXiaojian Du uint32_t mclk_mask;
930d0e4e112SXiaojian Du uint32_t fclk_mask;
931d0e4e112SXiaojian Du uint32_t clock_limit;
932d0e4e112SXiaojian Du
933d0e4e112SXiaojian Du if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
934d0e4e112SXiaojian Du switch (clk_type) {
935d0e4e112SXiaojian Du case SMU_MCLK:
936d0e4e112SXiaojian Du case SMU_UCLK:
937d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.uclk;
938d0e4e112SXiaojian Du break;
939d0e4e112SXiaojian Du case SMU_FCLK:
940d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.fclk;
941d0e4e112SXiaojian Du break;
942d0e4e112SXiaojian Du case SMU_GFXCLK:
943d0e4e112SXiaojian Du case SMU_SCLK:
944d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.gfxclk;
945d0e4e112SXiaojian Du break;
946d0e4e112SXiaojian Du case SMU_SOCCLK:
947d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.socclk;
948d0e4e112SXiaojian Du break;
949d0e4e112SXiaojian Du case SMU_VCLK:
950d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.vclk;
951d0e4e112SXiaojian Du break;
952d0e4e112SXiaojian Du case SMU_DCLK:
953d0e4e112SXiaojian Du clock_limit = smu->smu_table.boot_values.dclk;
954d0e4e112SXiaojian Du break;
955d0e4e112SXiaojian Du default:
956d0e4e112SXiaojian Du clock_limit = 0;
957d0e4e112SXiaojian Du break;
958d0e4e112SXiaojian Du }
959d0e4e112SXiaojian Du
960d0e4e112SXiaojian Du /* clock in Mhz unit */
961d0e4e112SXiaojian Du if (min)
962d0e4e112SXiaojian Du *min = clock_limit / 100;
963d0e4e112SXiaojian Du if (max)
964d0e4e112SXiaojian Du *max = clock_limit / 100;
965d0e4e112SXiaojian Du
966d0e4e112SXiaojian Du return 0;
967d0e4e112SXiaojian Du }
968d0e4e112SXiaojian Du if (max) {
969d0e4e112SXiaojian Du ret = vangogh_get_profiling_clk_mask(smu,
970d0e4e112SXiaojian Du AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
971d0e4e112SXiaojian Du &vclk_mask,
972d0e4e112SXiaojian Du &dclk_mask,
973d0e4e112SXiaojian Du &mclk_mask,
974d0e4e112SXiaojian Du &fclk_mask,
975d0e4e112SXiaojian Du &soc_mask);
976d0e4e112SXiaojian Du if (ret)
977d0e4e112SXiaojian Du goto failed;
978d0e4e112SXiaojian Du
979d0e4e112SXiaojian Du switch (clk_type) {
980d0e4e112SXiaojian Du case SMU_UCLK:
981d0e4e112SXiaojian Du case SMU_MCLK:
982d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
983d0e4e112SXiaojian Du if (ret)
984d0e4e112SXiaojian Du goto failed;
985d0e4e112SXiaojian Du break;
986d0e4e112SXiaojian Du case SMU_SOCCLK:
987d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
988d0e4e112SXiaojian Du if (ret)
989d0e4e112SXiaojian Du goto failed;
990d0e4e112SXiaojian Du break;
991d0e4e112SXiaojian Du case SMU_FCLK:
992d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
993d0e4e112SXiaojian Du if (ret)
994d0e4e112SXiaojian Du goto failed;
995d0e4e112SXiaojian Du break;
996d0e4e112SXiaojian Du case SMU_VCLK:
997d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
998d0e4e112SXiaojian Du if (ret)
999d0e4e112SXiaojian Du goto failed;
1000d0e4e112SXiaojian Du break;
1001d0e4e112SXiaojian Du case SMU_DCLK:
1002d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
1003d0e4e112SXiaojian Du if (ret)
1004d0e4e112SXiaojian Du goto failed;
1005d0e4e112SXiaojian Du break;
1006d0e4e112SXiaojian Du default:
1007d0e4e112SXiaojian Du ret = -EINVAL;
1008d0e4e112SXiaojian Du goto failed;
1009d0e4e112SXiaojian Du }
1010d0e4e112SXiaojian Du }
1011d0e4e112SXiaojian Du if (min) {
1012d0e4e112SXiaojian Du switch (clk_type) {
1013d0e4e112SXiaojian Du case SMU_UCLK:
1014d0e4e112SXiaojian Du case SMU_MCLK:
1015d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
1016d0e4e112SXiaojian Du if (ret)
1017d0e4e112SXiaojian Du goto failed;
1018d0e4e112SXiaojian Du break;
1019d0e4e112SXiaojian Du case SMU_SOCCLK:
1020d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
1021d0e4e112SXiaojian Du if (ret)
1022d0e4e112SXiaojian Du goto failed;
1023d0e4e112SXiaojian Du break;
1024d0e4e112SXiaojian Du case SMU_FCLK:
1025d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
1026d0e4e112SXiaojian Du if (ret)
1027d0e4e112SXiaojian Du goto failed;
1028d0e4e112SXiaojian Du break;
1029d0e4e112SXiaojian Du case SMU_VCLK:
1030d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1031d0e4e112SXiaojian Du if (ret)
1032d0e4e112SXiaojian Du goto failed;
1033d0e4e112SXiaojian Du break;
1034d0e4e112SXiaojian Du case SMU_DCLK:
1035d0e4e112SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1036d0e4e112SXiaojian Du if (ret)
1037d0e4e112SXiaojian Du goto failed;
1038d0e4e112SXiaojian Du break;
1039d0e4e112SXiaojian Du default:
1040d0e4e112SXiaojian Du ret = -EINVAL;
1041d0e4e112SXiaojian Du goto failed;
1042d0e4e112SXiaojian Du }
1043d0e4e112SXiaojian Du }
1044d0e4e112SXiaojian Du failed:
1045d0e4e112SXiaojian Du return ret;
1046d0e4e112SXiaojian Du }
1047d0e4e112SXiaojian Du
vangogh_get_power_profile_mode(struct smu_context * smu,char * buf)1048307f049bSXiaojian Du static int vangogh_get_power_profile_mode(struct smu_context *smu,
1049307f049bSXiaojian Du char *buf)
1050307f049bSXiaojian Du {
1051307f049bSXiaojian Du uint32_t i, size = 0;
1052307f049bSXiaojian Du int16_t workload_type = 0;
1053307f049bSXiaojian Du
1054307f049bSXiaojian Du if (!buf)
1055307f049bSXiaojian Du return -EINVAL;
1056307f049bSXiaojian Du
1057dc622367SPerry Yuan for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1058307f049bSXiaojian Du /*
1059307f049bSXiaojian Du * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1060307f049bSXiaojian Du * Not all profile modes are supported on vangogh.
1061307f049bSXiaojian Du */
1062307f049bSXiaojian Du workload_type = smu_cmn_to_asic_specific_index(smu,
1063307f049bSXiaojian Du CMN2ASIC_MAPPING_WORKLOAD,
1064307f049bSXiaojian Du i);
1065307f049bSXiaojian Du
1066307f049bSXiaojian Du if (workload_type < 0)
1067307f049bSXiaojian Du continue;
1068307f049bSXiaojian Du
1069fe14c285SDarren Powell size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
107094a80b5bSDarren Powell i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1071307f049bSXiaojian Du }
1072307f049bSXiaojian Du
1073307f049bSXiaojian Du return size;
1074307f049bSXiaojian Du }
1075307f049bSXiaojian Du
vangogh_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1076d0e4e112SXiaojian Du static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1077d0e4e112SXiaojian Du {
1078d0e4e112SXiaojian Du int workload_type, ret;
1079d0e4e112SXiaojian Du uint32_t profile_mode = input[size];
1080d0e4e112SXiaojian Du
1081dc622367SPerry Yuan if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) {
1082d0e4e112SXiaojian Du dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1083d0e4e112SXiaojian Du return -EINVAL;
1084d0e4e112SXiaojian Du }
1085d0e4e112SXiaojian Du
1086f727ebebSXiaojian Du if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
1087f727ebebSXiaojian Du profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
1088f727ebebSXiaojian Du return 0;
1089f727ebebSXiaojian Du
1090d0e4e112SXiaojian Du /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1091d0e4e112SXiaojian Du workload_type = smu_cmn_to_asic_specific_index(smu,
1092d0e4e112SXiaojian Du CMN2ASIC_MAPPING_WORKLOAD,
1093d0e4e112SXiaojian Du profile_mode);
1094d0e4e112SXiaojian Du if (workload_type < 0) {
10959d489afdSAlex Deucher dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
1096d0e4e112SXiaojian Du profile_mode);
1097d0e4e112SXiaojian Du return -EINVAL;
1098d0e4e112SXiaojian Du }
1099d0e4e112SXiaojian Du
1100d0e4e112SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1101d0e4e112SXiaojian Du 1 << workload_type,
1102d0e4e112SXiaojian Du NULL);
1103d0e4e112SXiaojian Du if (ret) {
1104d0e4e112SXiaojian Du dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
1105d0e4e112SXiaojian Du workload_type);
1106d0e4e112SXiaojian Du return ret;
1107d0e4e112SXiaojian Du }
1108d0e4e112SXiaojian Du
1109d0e4e112SXiaojian Du smu->power_profile_mode = profile_mode;
1110d0e4e112SXiaojian Du
1111d0e4e112SXiaojian Du return 0;
1112d0e4e112SXiaojian Du }
1113d0e4e112SXiaojian Du
vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1114dd9e0b21SXiaojian Du static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1115dd9e0b21SXiaojian Du enum smu_clk_type clk_type,
1116dd9e0b21SXiaojian Du uint32_t min,
1117dd9e0b21SXiaojian Du uint32_t max)
1118dd9e0b21SXiaojian Du {
1119dd9e0b21SXiaojian Du int ret = 0;
1120dd9e0b21SXiaojian Du
1121dd9e0b21SXiaojian Du if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1122dd9e0b21SXiaojian Du return 0;
1123dd9e0b21SXiaojian Du
1124dd9e0b21SXiaojian Du switch (clk_type) {
1125dd9e0b21SXiaojian Du case SMU_GFXCLK:
1126dd9e0b21SXiaojian Du case SMU_SCLK:
1127dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1128dd9e0b21SXiaojian Du SMU_MSG_SetHardMinGfxClk,
1129dd9e0b21SXiaojian Du min, NULL);
1130dd9e0b21SXiaojian Du if (ret)
1131dd9e0b21SXiaojian Du return ret;
1132dd9e0b21SXiaojian Du
1133dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1134dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxGfxClk,
1135dd9e0b21SXiaojian Du max, NULL);
1136dd9e0b21SXiaojian Du if (ret)
1137dd9e0b21SXiaojian Du return ret;
1138dd9e0b21SXiaojian Du break;
1139dd9e0b21SXiaojian Du case SMU_FCLK:
1140dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1141dd9e0b21SXiaojian Du SMU_MSG_SetHardMinFclkByFreq,
1142dd9e0b21SXiaojian Du min, NULL);
1143dd9e0b21SXiaojian Du if (ret)
1144dd9e0b21SXiaojian Du return ret;
1145dd9e0b21SXiaojian Du
1146dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1147dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxFclkByFreq,
1148dd9e0b21SXiaojian Du max, NULL);
1149dd9e0b21SXiaojian Du if (ret)
1150dd9e0b21SXiaojian Du return ret;
1151dd9e0b21SXiaojian Du break;
1152dd9e0b21SXiaojian Du case SMU_SOCCLK:
1153dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1154dd9e0b21SXiaojian Du SMU_MSG_SetHardMinSocclkByFreq,
1155dd9e0b21SXiaojian Du min, NULL);
1156dd9e0b21SXiaojian Du if (ret)
1157dd9e0b21SXiaojian Du return ret;
1158dd9e0b21SXiaojian Du
1159dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1160dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxSocclkByFreq,
1161dd9e0b21SXiaojian Du max, NULL);
1162dd9e0b21SXiaojian Du if (ret)
1163dd9e0b21SXiaojian Du return ret;
1164dd9e0b21SXiaojian Du break;
1165dd9e0b21SXiaojian Du case SMU_VCLK:
1166dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1167dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn,
1168dd9e0b21SXiaojian Du min << 16, NULL);
1169dd9e0b21SXiaojian Du if (ret)
1170dd9e0b21SXiaojian Du return ret;
1171dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1172dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxVcn,
1173dd9e0b21SXiaojian Du max << 16, NULL);
1174dd9e0b21SXiaojian Du if (ret)
1175dd9e0b21SXiaojian Du return ret;
1176dd9e0b21SXiaojian Du break;
1177dd9e0b21SXiaojian Du case SMU_DCLK:
1178dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1179dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn,
1180dd9e0b21SXiaojian Du min, NULL);
1181dd9e0b21SXiaojian Du if (ret)
1182dd9e0b21SXiaojian Du return ret;
1183dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1184dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxVcn,
1185dd9e0b21SXiaojian Du max, NULL);
1186dd9e0b21SXiaojian Du if (ret)
1187dd9e0b21SXiaojian Du return ret;
1188dd9e0b21SXiaojian Du break;
1189dd9e0b21SXiaojian Du default:
1190dd9e0b21SXiaojian Du return -EINVAL;
1191dd9e0b21SXiaojian Du }
1192dd9e0b21SXiaojian Du
1193dd9e0b21SXiaojian Du return ret;
1194dd9e0b21SXiaojian Du }
1195dd9e0b21SXiaojian Du
vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1196dd9e0b21SXiaojian Du static int vangogh_force_clk_levels(struct smu_context *smu,
1197dd9e0b21SXiaojian Du enum smu_clk_type clk_type, uint32_t mask)
1198dd9e0b21SXiaojian Du {
1199dd9e0b21SXiaojian Du uint32_t soft_min_level = 0, soft_max_level = 0;
1200dd9e0b21SXiaojian Du uint32_t min_freq = 0, max_freq = 0;
1201dd9e0b21SXiaojian Du int ret = 0 ;
1202dd9e0b21SXiaojian Du
1203dd9e0b21SXiaojian Du soft_min_level = mask ? (ffs(mask) - 1) : 0;
1204dd9e0b21SXiaojian Du soft_max_level = mask ? (fls(mask) - 1) : 0;
1205dd9e0b21SXiaojian Du
1206dd9e0b21SXiaojian Du switch (clk_type) {
1207dd9e0b21SXiaojian Du case SMU_SOCCLK:
1208dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1209dd9e0b21SXiaojian Du soft_min_level, &min_freq);
1210dd9e0b21SXiaojian Du if (ret)
1211dd9e0b21SXiaojian Du return ret;
1212dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1213dd9e0b21SXiaojian Du soft_max_level, &max_freq);
1214dd9e0b21SXiaojian Du if (ret)
1215dd9e0b21SXiaojian Du return ret;
1216dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1217dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxSocclkByFreq,
1218dd9e0b21SXiaojian Du max_freq, NULL);
1219dd9e0b21SXiaojian Du if (ret)
1220dd9e0b21SXiaojian Du return ret;
1221dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1222dd9e0b21SXiaojian Du SMU_MSG_SetHardMinSocclkByFreq,
1223dd9e0b21SXiaojian Du min_freq, NULL);
1224dd9e0b21SXiaojian Du if (ret)
1225dd9e0b21SXiaojian Du return ret;
1226dd9e0b21SXiaojian Du break;
1227dd9e0b21SXiaojian Du case SMU_FCLK:
1228dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1229dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq);
1230dd9e0b21SXiaojian Du if (ret)
1231dd9e0b21SXiaojian Du return ret;
1232dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1233dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq);
1234dd9e0b21SXiaojian Du if (ret)
1235dd9e0b21SXiaojian Du return ret;
1236dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1237dd9e0b21SXiaojian Du SMU_MSG_SetSoftMaxFclkByFreq,
1238dd9e0b21SXiaojian Du max_freq, NULL);
1239dd9e0b21SXiaojian Du if (ret)
1240dd9e0b21SXiaojian Du return ret;
1241dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1242dd9e0b21SXiaojian Du SMU_MSG_SetHardMinFclkByFreq,
1243dd9e0b21SXiaojian Du min_freq, NULL);
1244dd9e0b21SXiaojian Du if (ret)
1245dd9e0b21SXiaojian Du return ret;
1246dd9e0b21SXiaojian Du break;
1247dd9e0b21SXiaojian Du case SMU_VCLK:
1248dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1249dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq);
1250dd9e0b21SXiaojian Du if (ret)
1251dd9e0b21SXiaojian Du return ret;
1252307f049bSXiaojian Du
1253dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1254dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq);
1255dd9e0b21SXiaojian Du if (ret)
1256dd9e0b21SXiaojian Du return ret;
1257307f049bSXiaojian Du
1258307f049bSXiaojian Du
1259dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1260dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn,
1261dd9e0b21SXiaojian Du min_freq << 16, NULL);
1262dd9e0b21SXiaojian Du if (ret)
1263dd9e0b21SXiaojian Du return ret;
1264307f049bSXiaojian Du
1265307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1266307f049bSXiaojian Du SMU_MSG_SetSoftMaxVcn,
1267307f049bSXiaojian Du max_freq << 16, NULL);
1268307f049bSXiaojian Du if (ret)
1269307f049bSXiaojian Du return ret;
1270307f049bSXiaojian Du
1271dd9e0b21SXiaojian Du break;
1272dd9e0b21SXiaojian Du case SMU_DCLK:
1273dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1274dd9e0b21SXiaojian Du clk_type, soft_min_level, &min_freq);
1275dd9e0b21SXiaojian Du if (ret)
1276dd9e0b21SXiaojian Du return ret;
1277307f049bSXiaojian Du
1278dd9e0b21SXiaojian Du ret = vangogh_get_dpm_clk_limited(smu,
1279dd9e0b21SXiaojian Du clk_type, soft_max_level, &max_freq);
1280dd9e0b21SXiaojian Du if (ret)
1281dd9e0b21SXiaojian Du return ret;
1282307f049bSXiaojian Du
1283dd9e0b21SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1284dd9e0b21SXiaojian Du SMU_MSG_SetHardMinVcn,
1285dd9e0b21SXiaojian Du min_freq, NULL);
1286dd9e0b21SXiaojian Du if (ret)
1287dd9e0b21SXiaojian Du return ret;
1288307f049bSXiaojian Du
1289307f049bSXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
1290307f049bSXiaojian Du SMU_MSG_SetSoftMaxVcn,
1291307f049bSXiaojian Du max_freq, NULL);
1292307f049bSXiaojian Du if (ret)
1293307f049bSXiaojian Du return ret;
1294307f049bSXiaojian Du
1295dd9e0b21SXiaojian Du break;
1296dd9e0b21SXiaojian Du default:
1297dd9e0b21SXiaojian Du break;
1298dd9e0b21SXiaojian Du }
1299dd9e0b21SXiaojian Du
1300dd9e0b21SXiaojian Du return ret;
1301dd9e0b21SXiaojian Du }
1302dd9e0b21SXiaojian Du
vangogh_force_dpm_limit_value(struct smu_context * smu,bool highest)1303dd9e0b21SXiaojian Du static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1304dd9e0b21SXiaojian Du {
1305dd9e0b21SXiaojian Du int ret = 0, i = 0;
1306dd9e0b21SXiaojian Du uint32_t min_freq, max_freq, force_freq;
1307dd9e0b21SXiaojian Du enum smu_clk_type clk_type;
1308dd9e0b21SXiaojian Du
1309dd9e0b21SXiaojian Du enum smu_clk_type clks[] = {
1310dd9e0b21SXiaojian Du SMU_SOCCLK,
1311dd9e0b21SXiaojian Du SMU_VCLK,
1312dd9e0b21SXiaojian Du SMU_DCLK,
1313dd9e0b21SXiaojian Du SMU_FCLK,
1314dd9e0b21SXiaojian Du };
1315dd9e0b21SXiaojian Du
1316dd9e0b21SXiaojian Du for (i = 0; i < ARRAY_SIZE(clks); i++) {
1317dd9e0b21SXiaojian Du clk_type = clks[i];
1318dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1319dd9e0b21SXiaojian Du if (ret)
1320dd9e0b21SXiaojian Du return ret;
1321dd9e0b21SXiaojian Du
1322dd9e0b21SXiaojian Du force_freq = highest ? max_freq : min_freq;
1323dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1324dd9e0b21SXiaojian Du if (ret)
1325dd9e0b21SXiaojian Du return ret;
1326dd9e0b21SXiaojian Du }
1327dd9e0b21SXiaojian Du
1328dd9e0b21SXiaojian Du return ret;
1329dd9e0b21SXiaojian Du }
1330dd9e0b21SXiaojian Du
vangogh_unforce_dpm_levels(struct smu_context * smu)1331dd9e0b21SXiaojian Du static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1332dd9e0b21SXiaojian Du {
1333dd9e0b21SXiaojian Du int ret = 0, i = 0;
1334dd9e0b21SXiaojian Du uint32_t min_freq, max_freq;
1335dd9e0b21SXiaojian Du enum smu_clk_type clk_type;
1336dd9e0b21SXiaojian Du
1337dd9e0b21SXiaojian Du struct clk_feature_map {
1338dd9e0b21SXiaojian Du enum smu_clk_type clk_type;
1339dd9e0b21SXiaojian Du uint32_t feature;
1340dd9e0b21SXiaojian Du } clk_feature_map[] = {
1341dd9e0b21SXiaojian Du {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1342dd9e0b21SXiaojian Du {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1343b0eec124SXiaojian Du {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1344b0eec124SXiaojian Du {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1345dd9e0b21SXiaojian Du };
1346dd9e0b21SXiaojian Du
1347dd9e0b21SXiaojian Du for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1348dd9e0b21SXiaojian Du
1349dd9e0b21SXiaojian Du if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1350dd9e0b21SXiaojian Du continue;
1351dd9e0b21SXiaojian Du
1352dd9e0b21SXiaojian Du clk_type = clk_feature_map[i].clk_type;
1353dd9e0b21SXiaojian Du
1354dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1355dd9e0b21SXiaojian Du
1356dd9e0b21SXiaojian Du if (ret)
1357dd9e0b21SXiaojian Du return ret;
1358dd9e0b21SXiaojian Du
1359dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1360dd9e0b21SXiaojian Du
1361dd9e0b21SXiaojian Du if (ret)
1362dd9e0b21SXiaojian Du return ret;
1363dd9e0b21SXiaojian Du }
1364dd9e0b21SXiaojian Du
1365dd9e0b21SXiaojian Du return ret;
1366dd9e0b21SXiaojian Du }
1367dd9e0b21SXiaojian Du
vangogh_set_peak_clock_by_device(struct smu_context * smu)1368dd9e0b21SXiaojian Du static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1369dd9e0b21SXiaojian Du {
1370dd9e0b21SXiaojian Du int ret = 0;
1371dd9e0b21SXiaojian Du uint32_t socclk_freq = 0, fclk_freq = 0;
1372307f049bSXiaojian Du uint32_t vclk_freq = 0, dclk_freq = 0;
1373dd9e0b21SXiaojian Du
1374dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1375dd9e0b21SXiaojian Du if (ret)
1376dd9e0b21SXiaojian Du return ret;
1377dd9e0b21SXiaojian Du
1378dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1379dd9e0b21SXiaojian Du if (ret)
1380dd9e0b21SXiaojian Du return ret;
1381dd9e0b21SXiaojian Du
1382dd9e0b21SXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1383dd9e0b21SXiaojian Du if (ret)
1384dd9e0b21SXiaojian Du return ret;
1385dd9e0b21SXiaojian Du
1386dd9e0b21SXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1387dd9e0b21SXiaojian Du if (ret)
1388dd9e0b21SXiaojian Du return ret;
1389dd9e0b21SXiaojian Du
1390307f049bSXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1391307f049bSXiaojian Du if (ret)
1392307f049bSXiaojian Du return ret;
1393307f049bSXiaojian Du
1394307f049bSXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1395307f049bSXiaojian Du if (ret)
1396307f049bSXiaojian Du return ret;
1397307f049bSXiaojian Du
1398307f049bSXiaojian Du ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1399307f049bSXiaojian Du if (ret)
1400307f049bSXiaojian Du return ret;
1401307f049bSXiaojian Du
1402307f049bSXiaojian Du ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1403307f049bSXiaojian Du if (ret)
1404307f049bSXiaojian Du return ret;
1405307f049bSXiaojian Du
1406dd9e0b21SXiaojian Du return ret;
1407dd9e0b21SXiaojian Du }
1408dd9e0b21SXiaojian Du
vangogh_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1409ea173d15SXiaojian Du static int vangogh_set_performance_level(struct smu_context *smu,
1410ea173d15SXiaojian Du enum amd_dpm_forced_level level)
1411ea173d15SXiaojian Du {
141291aa9c8fSAlex Deucher int ret = 0, i;
1413ea173d15SXiaojian Du uint32_t soc_mask, mclk_mask, fclk_mask;
1414307f049bSXiaojian Du uint32_t vclk_mask = 0, dclk_mask = 0;
1415ea173d15SXiaojian Du
1416d7379efaSXiaojian Du smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1417d7379efaSXiaojian Du smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1418d7379efaSXiaojian Du
141968e3871dSAlex Deucher switch (level) {
142068e3871dSAlex Deucher case AMD_DPM_FORCED_LEVEL_HIGH:
142168e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
142268e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
142368e3871dSAlex Deucher
142468e3871dSAlex Deucher
1425ea173d15SXiaojian Du ret = vangogh_force_dpm_limit_value(smu, true);
142668e3871dSAlex Deucher if (ret)
142768e3871dSAlex Deucher return ret;
1428ea173d15SXiaojian Du break;
1429ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_LOW:
1430d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
143168e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1432d7379efaSXiaojian Du
1433ea173d15SXiaojian Du ret = vangogh_force_dpm_limit_value(smu, false);
143468e3871dSAlex Deucher if (ret)
143568e3871dSAlex Deucher return ret;
1436ea173d15SXiaojian Du break;
1437ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_AUTO:
1438d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1439d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1440d7379efaSXiaojian Du
1441ea173d15SXiaojian Du ret = vangogh_unforce_dpm_levels(smu);
144268e3871dSAlex Deucher if (ret)
144368e3871dSAlex Deucher return ret;
1444ea173d15SXiaojian Du break;
1445ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
144668e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
144768e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1448307f049bSXiaojian Du
1449307f049bSXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, level,
1450307f049bSXiaojian Du &vclk_mask,
1451307f049bSXiaojian Du &dclk_mask,
1452307f049bSXiaojian Du &mclk_mask,
1453307f049bSXiaojian Du &fclk_mask,
1454307f049bSXiaojian Du &soc_mask);
1455307f049bSXiaojian Du if (ret)
1456307f049bSXiaojian Du return ret;
1457307f049bSXiaojian Du
1458307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1459307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1460307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1461307f049bSXiaojian Du vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1462ea173d15SXiaojian Du break;
1463ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1464d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
146568e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1466ea173d15SXiaojian Du break;
1467ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1468d7379efaSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1469d7379efaSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1470d7379efaSXiaojian Du
1471ea173d15SXiaojian Du ret = vangogh_get_profiling_clk_mask(smu, level,
1472ea173d15SXiaojian Du NULL,
1473ea173d15SXiaojian Du NULL,
1474ea173d15SXiaojian Du &mclk_mask,
1475ea173d15SXiaojian Du &fclk_mask,
1476307f049bSXiaojian Du NULL);
1477ea173d15SXiaojian Du if (ret)
1478ea173d15SXiaojian Du return ret;
1479307f049bSXiaojian Du
1480ea173d15SXiaojian Du vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1481ea173d15SXiaojian Du break;
1482ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
148368e3871dSAlex Deucher smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
148468e3871dSAlex Deucher smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1485307f049bSXiaojian Du
1486ea173d15SXiaojian Du ret = vangogh_set_peak_clock_by_device(smu);
148768e3871dSAlex Deucher if (ret)
148868e3871dSAlex Deucher return ret;
1489ea173d15SXiaojian Du break;
1490ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_MANUAL:
1491ea173d15SXiaojian Du case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1492ea173d15SXiaojian Du default:
149368e3871dSAlex Deucher return 0;
1494ea173d15SXiaojian Du }
149568e3871dSAlex Deucher
149668e3871dSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
149768e3871dSAlex Deucher smu->gfx_actual_hard_min_freq, NULL);
149868e3871dSAlex Deucher if (ret)
149968e3871dSAlex Deucher return ret;
150068e3871dSAlex Deucher
150168e3871dSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
150268e3871dSAlex Deucher smu->gfx_actual_soft_max_freq, NULL);
150368e3871dSAlex Deucher if (ret)
150468e3871dSAlex Deucher return ret;
150568e3871dSAlex Deucher
150691aa9c8fSAlex Deucher if (smu->adev->pm.fw_version >= 0x43f1b00) {
150791aa9c8fSAlex Deucher for (i = 0; i < smu->cpu_core_num; i++) {
150891aa9c8fSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
150991aa9c8fSAlex Deucher ((i << 20)
151091aa9c8fSAlex Deucher | smu->cpu_actual_soft_min_freq),
151191aa9c8fSAlex Deucher NULL);
151291aa9c8fSAlex Deucher if (ret)
151391aa9c8fSAlex Deucher return ret;
151491aa9c8fSAlex Deucher
151591aa9c8fSAlex Deucher ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
151691aa9c8fSAlex Deucher ((i << 20)
151791aa9c8fSAlex Deucher | smu->cpu_actual_soft_max_freq),
151891aa9c8fSAlex Deucher NULL);
151991aa9c8fSAlex Deucher if (ret)
152091aa9c8fSAlex Deucher return ret;
152191aa9c8fSAlex Deucher }
152291aa9c8fSAlex Deucher }
152391aa9c8fSAlex Deucher
1524ea173d15SXiaojian Du return ret;
1525ea173d15SXiaojian Du }
1526ea173d15SXiaojian Du
vangogh_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1527271ab489SXiaojian Du static int vangogh_read_sensor(struct smu_context *smu,
1528271ab489SXiaojian Du enum amd_pp_sensors sensor,
1529271ab489SXiaojian Du void *data, uint32_t *size)
1530271ab489SXiaojian Du {
1531271ab489SXiaojian Du int ret = 0;
1532271ab489SXiaojian Du
1533271ab489SXiaojian Du if (!data || !size)
1534271ab489SXiaojian Du return -EINVAL;
1535271ab489SXiaojian Du
1536271ab489SXiaojian Du switch (sensor) {
1537271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GPU_LOAD:
153886c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15396cc24d8dSAlex Deucher METRICS_AVERAGE_GFXACTIVITY,
15406cc24d8dSAlex Deucher (uint32_t *)data);
1541271ab489SXiaojian Du *size = 4;
1542271ab489SXiaojian Du break;
1543*9366c2e8SMario Limonciello case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
154486c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15456cc24d8dSAlex Deucher METRICS_AVERAGE_SOCKETPOWER,
15466cc24d8dSAlex Deucher (uint32_t *)data);
1547271ab489SXiaojian Du *size = 4;
1548271ab489SXiaojian Du break;
154947f1724dSMario Limonciello case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
155047f1724dSMario Limonciello ret = vangogh_common_get_smu_metrics_data(smu,
155147f1724dSMario Limonciello METRICS_CURR_SOCKETPOWER,
155247f1724dSMario Limonciello (uint32_t *)data);
155347f1724dSMario Limonciello *size = 4;
155447f1724dSMario Limonciello break;
1555271ab489SXiaojian Du case AMDGPU_PP_SENSOR_EDGE_TEMP:
155686c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15576cc24d8dSAlex Deucher METRICS_TEMPERATURE_EDGE,
15586cc24d8dSAlex Deucher (uint32_t *)data);
15596cc24d8dSAlex Deucher *size = 4;
15606cc24d8dSAlex Deucher break;
1561271ab489SXiaojian Du case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
156286c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15636cc24d8dSAlex Deucher METRICS_TEMPERATURE_HOTSPOT,
15646cc24d8dSAlex Deucher (uint32_t *)data);
1565271ab489SXiaojian Du *size = 4;
1566271ab489SXiaojian Du break;
1567271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GFX_MCLK:
156886c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
1569a99a5116SXiaojian Du METRICS_CURR_UCLK,
15706cc24d8dSAlex Deucher (uint32_t *)data);
1571271ab489SXiaojian Du *(uint32_t *)data *= 100;
1572271ab489SXiaojian Du *size = 4;
1573271ab489SXiaojian Du break;
1574271ab489SXiaojian Du case AMDGPU_PP_SENSOR_GFX_SCLK:
157586c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
1576a99a5116SXiaojian Du METRICS_CURR_GFXCLK,
15776cc24d8dSAlex Deucher (uint32_t *)data);
1578271ab489SXiaojian Du *(uint32_t *)data *= 100;
1579271ab489SXiaojian Du *size = 4;
1580271ab489SXiaojian Du break;
1581271ab489SXiaojian Du case AMDGPU_PP_SENSOR_VDDGFX:
158286c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15832139d12bSAlex Deucher METRICS_VOLTAGE_VDDGFX,
15842139d12bSAlex Deucher (uint32_t *)data);
15852139d12bSAlex Deucher *size = 4;
15862139d12bSAlex Deucher break;
15872139d12bSAlex Deucher case AMDGPU_PP_SENSOR_VDDNB:
158886c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
15892139d12bSAlex Deucher METRICS_VOLTAGE_VDDSOC,
15902139d12bSAlex Deucher (uint32_t *)data);
1591271ab489SXiaojian Du *size = 4;
1592271ab489SXiaojian Du break;
1593517cb957SHuang Rui case AMDGPU_PP_SENSOR_CPU_CLK:
159486c8236eSXiaojian Du ret = vangogh_common_get_smu_metrics_data(smu,
1595517cb957SHuang Rui METRICS_AVERAGE_CPUCLK,
1596517cb957SHuang Rui (uint32_t *)data);
15974aef0ebcSHuang Rui *size = smu->cpu_core_num * sizeof(uint16_t);
1598517cb957SHuang Rui break;
1599271ab489SXiaojian Du default:
1600271ab489SXiaojian Du ret = -EOPNOTSUPP;
1601271ab489SXiaojian Du break;
1602271ab489SXiaojian Du }
1603271ab489SXiaojian Du
1604271ab489SXiaojian Du return ret;
1605271ab489SXiaojian Du }
1606271ab489SXiaojian Du
vangogh_get_apu_thermal_limit(struct smu_context * smu,uint32_t * limit)16070c3c9936SKun Liu static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
16080c3c9936SKun Liu {
16090c3c9936SKun Liu return smu_cmn_send_smc_msg_with_param(smu,
16100c3c9936SKun Liu SMU_MSG_GetThermalLimit,
16110c3c9936SKun Liu 0, limit);
16120c3c9936SKun Liu }
16130c3c9936SKun Liu
vangogh_set_apu_thermal_limit(struct smu_context * smu,uint32_t limit)1614aea9040cSKun Liu static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
16150c3c9936SKun Liu {
16160c3c9936SKun Liu return smu_cmn_send_smc_msg_with_param(smu,
16170c3c9936SKun Liu SMU_MSG_SetReducedThermalLimit,
16180c3c9936SKun Liu limit, NULL);
16190c3c9936SKun Liu }
16200c3c9936SKun Liu
16210c3c9936SKun Liu
vangogh_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1622271ab489SXiaojian Du static int vangogh_set_watermarks_table(struct smu_context *smu,
1623271ab489SXiaojian Du struct pp_smu_wm_range_sets *clock_ranges)
1624271ab489SXiaojian Du {
1625271ab489SXiaojian Du int i;
1626271ab489SXiaojian Du int ret = 0;
1627271ab489SXiaojian Du Watermarks_t *table = smu->smu_table.watermarks_table;
1628271ab489SXiaojian Du
1629271ab489SXiaojian Du if (!table || !clock_ranges)
1630271ab489SXiaojian Du return -EINVAL;
1631271ab489SXiaojian Du
1632271ab489SXiaojian Du if (clock_ranges) {
1633271ab489SXiaojian Du if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1634271ab489SXiaojian Du clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1635271ab489SXiaojian Du return -EINVAL;
1636271ab489SXiaojian Du
1637271ab489SXiaojian Du for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1638271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MinClock =
1639271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1640271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1641271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1642271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1643271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1644271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1645271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1646271ab489SXiaojian Du
1647271ab489SXiaojian Du table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1648271ab489SXiaojian Du clock_ranges->reader_wm_sets[i].wm_inst;
1649271ab489SXiaojian Du }
1650271ab489SXiaojian Du
1651271ab489SXiaojian Du for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1652271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MinClock =
1653271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1654271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1655271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1656271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1657271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1658271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1659271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1660271ab489SXiaojian Du
1661271ab489SXiaojian Du table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1662271ab489SXiaojian Du clock_ranges->writer_wm_sets[i].wm_inst;
1663271ab489SXiaojian Du }
1664271ab489SXiaojian Du
1665271ab489SXiaojian Du smu->watermarks_bitmap |= WATERMARKS_EXIST;
1666271ab489SXiaojian Du }
1667271ab489SXiaojian Du
1668271ab489SXiaojian Du /* pass data to smu controller */
1669271ab489SXiaojian Du if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1670271ab489SXiaojian Du !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1671271ab489SXiaojian Du ret = smu_cmn_write_watermarks_table(smu);
1672271ab489SXiaojian Du if (ret) {
1673271ab489SXiaojian Du dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1674271ab489SXiaojian Du return ret;
1675271ab489SXiaojian Du }
1676271ab489SXiaojian Du smu->watermarks_bitmap |= WATERMARKS_LOADED;
1677271ab489SXiaojian Du }
1678271ab489SXiaojian Du
1679271ab489SXiaojian Du return 0;
1680f46a221bSXiaojian Du }
1681f46a221bSXiaojian Du
vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context * smu,void ** table)16820d6516efSLi Ma static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
16830d6516efSLi Ma void **table)
16840d6516efSLi Ma {
16850d6516efSLi Ma struct smu_table_context *smu_table = &smu->smu_table;
16860d6516efSLi Ma struct gpu_metrics_v2_3 *gpu_metrics =
16870d6516efSLi Ma (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
16880d6516efSLi Ma SmuMetrics_legacy_t metrics;
16890d6516efSLi Ma int ret = 0;
16900d6516efSLi Ma
16910d6516efSLi Ma ret = smu_cmn_get_metrics_table(smu, &metrics, true);
16920d6516efSLi Ma if (ret)
16930d6516efSLi Ma return ret;
16940d6516efSLi Ma
16950d6516efSLi Ma smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
16960d6516efSLi Ma
16970d6516efSLi Ma gpu_metrics->temperature_gfx = metrics.GfxTemperature;
16980d6516efSLi Ma gpu_metrics->temperature_soc = metrics.SocTemperature;
16990d6516efSLi Ma memcpy(&gpu_metrics->temperature_core[0],
17000d6516efSLi Ma &metrics.CoreTemperature[0],
17010d6516efSLi Ma sizeof(uint16_t) * 4);
17020d6516efSLi Ma gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
17030d6516efSLi Ma
17040d6516efSLi Ma gpu_metrics->average_gfx_activity = metrics.GfxActivity;
17050d6516efSLi Ma gpu_metrics->average_mm_activity = metrics.UvdActivity;
17060d6516efSLi Ma
17070d6516efSLi Ma gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
17080d6516efSLi Ma gpu_metrics->average_cpu_power = metrics.Power[0];
17090d6516efSLi Ma gpu_metrics->average_soc_power = metrics.Power[1];
17100d6516efSLi Ma gpu_metrics->average_gfx_power = metrics.Power[2];
17110d6516efSLi Ma memcpy(&gpu_metrics->average_core_power[0],
17120d6516efSLi Ma &metrics.CorePower[0],
17130d6516efSLi Ma sizeof(uint16_t) * 4);
17140d6516efSLi Ma
17150d6516efSLi Ma gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
17160d6516efSLi Ma gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
17170d6516efSLi Ma gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
17180d6516efSLi Ma gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
17190d6516efSLi Ma gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
17200d6516efSLi Ma gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
17210d6516efSLi Ma
17220d6516efSLi Ma memcpy(&gpu_metrics->current_coreclk[0],
17230d6516efSLi Ma &metrics.CoreFrequency[0],
17240d6516efSLi Ma sizeof(uint16_t) * 4);
17250d6516efSLi Ma gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
17260d6516efSLi Ma
17270d6516efSLi Ma gpu_metrics->throttle_status = metrics.ThrottlerStatus;
17280d6516efSLi Ma gpu_metrics->indep_throttle_status =
17290d6516efSLi Ma smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
17300d6516efSLi Ma vangogh_throttler_map);
17310d6516efSLi Ma
17320d6516efSLi Ma gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
17330d6516efSLi Ma
17340d6516efSLi Ma *table = (void *)gpu_metrics;
17350d6516efSLi Ma
17360d6516efSLi Ma return sizeof(struct gpu_metrics_v2_3);
17370d6516efSLi Ma }
17380d6516efSLi Ma
vangogh_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)173986c8236eSXiaojian Du static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
174086c8236eSXiaojian Du void **table)
174186c8236eSXiaojian Du {
174286c8236eSXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
17437cab3cffSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics =
17447cab3cffSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
174586c8236eSXiaojian Du SmuMetrics_legacy_t metrics;
174686c8236eSXiaojian Du int ret = 0;
174786c8236eSXiaojian Du
174886c8236eSXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, true);
174986c8236eSXiaojian Du if (ret)
175086c8236eSXiaojian Du return ret;
175186c8236eSXiaojian Du
17527cab3cffSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
175386c8236eSXiaojian Du
175486c8236eSXiaojian Du gpu_metrics->temperature_gfx = metrics.GfxTemperature;
175586c8236eSXiaojian Du gpu_metrics->temperature_soc = metrics.SocTemperature;
175686c8236eSXiaojian Du memcpy(&gpu_metrics->temperature_core[0],
175786c8236eSXiaojian Du &metrics.CoreTemperature[0],
175886c8236eSXiaojian Du sizeof(uint16_t) * 4);
175986c8236eSXiaojian Du gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
176086c8236eSXiaojian Du
176186c8236eSXiaojian Du gpu_metrics->average_gfx_activity = metrics.GfxActivity;
176286c8236eSXiaojian Du gpu_metrics->average_mm_activity = metrics.UvdActivity;
176386c8236eSXiaojian Du
176486c8236eSXiaojian Du gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
176586c8236eSXiaojian Du gpu_metrics->average_cpu_power = metrics.Power[0];
176686c8236eSXiaojian Du gpu_metrics->average_soc_power = metrics.Power[1];
176786c8236eSXiaojian Du gpu_metrics->average_gfx_power = metrics.Power[2];
176886c8236eSXiaojian Du memcpy(&gpu_metrics->average_core_power[0],
176986c8236eSXiaojian Du &metrics.CorePower[0],
177086c8236eSXiaojian Du sizeof(uint16_t) * 4);
177186c8236eSXiaojian Du
177286c8236eSXiaojian Du gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
177386c8236eSXiaojian Du gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
177486c8236eSXiaojian Du gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
177586c8236eSXiaojian Du gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
177686c8236eSXiaojian Du gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
177786c8236eSXiaojian Du gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
177886c8236eSXiaojian Du
177986c8236eSXiaojian Du memcpy(&gpu_metrics->current_coreclk[0],
178086c8236eSXiaojian Du &metrics.CoreFrequency[0],
178186c8236eSXiaojian Du sizeof(uint16_t) * 4);
178286c8236eSXiaojian Du gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
178386c8236eSXiaojian Du
178486c8236eSXiaojian Du gpu_metrics->throttle_status = metrics.ThrottlerStatus;
17857cab3cffSGraham Sider gpu_metrics->indep_throttle_status =
17867cab3cffSGraham Sider smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
17877cab3cffSGraham Sider vangogh_throttler_map);
178886c8236eSXiaojian Du
178986c8236eSXiaojian Du gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
179086c8236eSXiaojian Du
179186c8236eSXiaojian Du *table = (void *)gpu_metrics;
179286c8236eSXiaojian Du
17937cab3cffSGraham Sider return sizeof(struct gpu_metrics_v2_2);
179486c8236eSXiaojian Du }
179586c8236eSXiaojian Du
vangogh_get_gpu_metrics_v2_3(struct smu_context * smu,void ** table)17960d6516efSLi Ma static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
17970d6516efSLi Ma void **table)
17980d6516efSLi Ma {
17990d6516efSLi Ma struct smu_table_context *smu_table = &smu->smu_table;
18000d6516efSLi Ma struct gpu_metrics_v2_3 *gpu_metrics =
18010d6516efSLi Ma (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
18020d6516efSLi Ma SmuMetrics_t metrics;
18030d6516efSLi Ma int ret = 0;
18040d6516efSLi Ma
18050d6516efSLi Ma ret = smu_cmn_get_metrics_table(smu, &metrics, true);
18060d6516efSLi Ma if (ret)
18070d6516efSLi Ma return ret;
18080d6516efSLi Ma
18090d6516efSLi Ma smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
18100d6516efSLi Ma
18110d6516efSLi Ma gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
18120d6516efSLi Ma gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
18130d6516efSLi Ma memcpy(&gpu_metrics->temperature_core[0],
18140d6516efSLi Ma &metrics.Current.CoreTemperature[0],
18150d6516efSLi Ma sizeof(uint16_t) * 4);
18160d6516efSLi Ma gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
18170d6516efSLi Ma
18180d6516efSLi Ma gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
18190d6516efSLi Ma gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
18200d6516efSLi Ma memcpy(&gpu_metrics->average_temperature_core[0],
18210d6516efSLi Ma &metrics.Average.CoreTemperature[0],
18220d6516efSLi Ma sizeof(uint16_t) * 4);
18230d6516efSLi Ma gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
18240d6516efSLi Ma
18250d6516efSLi Ma gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
18260d6516efSLi Ma gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
18270d6516efSLi Ma
18280d6516efSLi Ma gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
18290d6516efSLi Ma gpu_metrics->average_cpu_power = metrics.Current.Power[0];
18300d6516efSLi Ma gpu_metrics->average_soc_power = metrics.Current.Power[1];
18310d6516efSLi Ma gpu_metrics->average_gfx_power = metrics.Current.Power[2];
18320d6516efSLi Ma memcpy(&gpu_metrics->average_core_power[0],
18330d6516efSLi Ma &metrics.Average.CorePower[0],
18340d6516efSLi Ma sizeof(uint16_t) * 4);
18350d6516efSLi Ma
18360d6516efSLi Ma gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
18370d6516efSLi Ma gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
18380d6516efSLi Ma gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
18390d6516efSLi Ma gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
18400d6516efSLi Ma gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
18410d6516efSLi Ma gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
18420d6516efSLi Ma
18430d6516efSLi Ma gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
18440d6516efSLi Ma gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
18450d6516efSLi Ma gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
18460d6516efSLi Ma gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
18470d6516efSLi Ma gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
18480d6516efSLi Ma gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
18490d6516efSLi Ma
18500d6516efSLi Ma memcpy(&gpu_metrics->current_coreclk[0],
18510d6516efSLi Ma &metrics.Current.CoreFrequency[0],
18520d6516efSLi Ma sizeof(uint16_t) * 4);
18530d6516efSLi Ma gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
18540d6516efSLi Ma
18550d6516efSLi Ma gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
18560d6516efSLi Ma gpu_metrics->indep_throttle_status =
18570d6516efSLi Ma smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
18580d6516efSLi Ma vangogh_throttler_map);
18590d6516efSLi Ma
18600d6516efSLi Ma gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
18610d6516efSLi Ma
18620d6516efSLi Ma *table = (void *)gpu_metrics;
18630d6516efSLi Ma
18640d6516efSLi Ma return sizeof(struct gpu_metrics_v2_3);
18650d6516efSLi Ma }
18660d6516efSLi Ma
vangogh_get_gpu_metrics_v2_4(struct smu_context * smu,void ** table)186741cec40bSWenyou Yang static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
186841cec40bSWenyou Yang void **table)
186941cec40bSWenyou Yang {
187041cec40bSWenyou Yang SmuMetrics_t metrics;
187141cec40bSWenyou Yang struct smu_table_context *smu_table = &smu->smu_table;
187241cec40bSWenyou Yang struct gpu_metrics_v2_4 *gpu_metrics =
187341cec40bSWenyou Yang (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table;
187441cec40bSWenyou Yang int ret = 0;
187541cec40bSWenyou Yang
187641cec40bSWenyou Yang ret = smu_cmn_get_metrics_table(smu, &metrics, true);
187741cec40bSWenyou Yang if (ret)
187841cec40bSWenyou Yang return ret;
187941cec40bSWenyou Yang
188041cec40bSWenyou Yang smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
188141cec40bSWenyou Yang
188241cec40bSWenyou Yang gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
188341cec40bSWenyou Yang gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
188441cec40bSWenyou Yang memcpy(&gpu_metrics->temperature_core[0],
188541cec40bSWenyou Yang &metrics.Current.CoreTemperature[0],
188641cec40bSWenyou Yang sizeof(uint16_t) * 4);
188741cec40bSWenyou Yang gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
188841cec40bSWenyou Yang
188941cec40bSWenyou Yang gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
189041cec40bSWenyou Yang gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
189141cec40bSWenyou Yang memcpy(&gpu_metrics->average_temperature_core[0],
189241cec40bSWenyou Yang &metrics.Average.CoreTemperature[0],
189341cec40bSWenyou Yang sizeof(uint16_t) * 4);
189441cec40bSWenyou Yang gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
189541cec40bSWenyou Yang
189641cec40bSWenyou Yang gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
189741cec40bSWenyou Yang gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
189841cec40bSWenyou Yang
189941cec40bSWenyou Yang gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
190041cec40bSWenyou Yang gpu_metrics->average_cpu_power = metrics.Current.Power[0];
190141cec40bSWenyou Yang gpu_metrics->average_soc_power = metrics.Current.Power[1];
190241cec40bSWenyou Yang gpu_metrics->average_gfx_power = metrics.Current.Power[2];
190341cec40bSWenyou Yang
190441cec40bSWenyou Yang gpu_metrics->average_cpu_voltage = metrics.Current.Voltage[0];
190541cec40bSWenyou Yang gpu_metrics->average_soc_voltage = metrics.Current.Voltage[1];
190641cec40bSWenyou Yang gpu_metrics->average_gfx_voltage = metrics.Current.Voltage[2];
190741cec40bSWenyou Yang
190841cec40bSWenyou Yang gpu_metrics->average_cpu_current = metrics.Current.Current[0];
190941cec40bSWenyou Yang gpu_metrics->average_soc_current = metrics.Current.Current[1];
191041cec40bSWenyou Yang gpu_metrics->average_gfx_current = metrics.Current.Current[2];
191141cec40bSWenyou Yang
191241cec40bSWenyou Yang memcpy(&gpu_metrics->average_core_power[0],
191341cec40bSWenyou Yang &metrics.Average.CorePower[0],
191441cec40bSWenyou Yang sizeof(uint16_t) * 4);
191541cec40bSWenyou Yang
191641cec40bSWenyou Yang gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
191741cec40bSWenyou Yang gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
191841cec40bSWenyou Yang gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
191941cec40bSWenyou Yang gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
192041cec40bSWenyou Yang gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
192141cec40bSWenyou Yang gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
192241cec40bSWenyou Yang
192341cec40bSWenyou Yang gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
192441cec40bSWenyou Yang gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
192541cec40bSWenyou Yang gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
192641cec40bSWenyou Yang gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
192741cec40bSWenyou Yang gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
192841cec40bSWenyou Yang gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
192941cec40bSWenyou Yang
193041cec40bSWenyou Yang memcpy(&gpu_metrics->current_coreclk[0],
193141cec40bSWenyou Yang &metrics.Current.CoreFrequency[0],
193241cec40bSWenyou Yang sizeof(uint16_t) * 4);
193341cec40bSWenyou Yang gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
193441cec40bSWenyou Yang
193541cec40bSWenyou Yang gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
193641cec40bSWenyou Yang gpu_metrics->indep_throttle_status =
193741cec40bSWenyou Yang smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
193841cec40bSWenyou Yang vangogh_throttler_map);
193941cec40bSWenyou Yang
194041cec40bSWenyou Yang gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
194141cec40bSWenyou Yang
194241cec40bSWenyou Yang *table = (void *)gpu_metrics;
194341cec40bSWenyou Yang
194441cec40bSWenyou Yang return sizeof(struct gpu_metrics_v2_4);
194541cec40bSWenyou Yang }
194641cec40bSWenyou Yang
vangogh_get_gpu_metrics(struct smu_context * smu,void ** table)1947fd253334SXiaojian Du static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1948fd253334SXiaojian Du void **table)
1949fd253334SXiaojian Du {
1950fd253334SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
19517cab3cffSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics =
19527cab3cffSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1953fd253334SXiaojian Du SmuMetrics_t metrics;
1954fd253334SXiaojian Du int ret = 0;
1955fd253334SXiaojian Du
1956fd253334SXiaojian Du ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1957fd253334SXiaojian Du if (ret)
1958fd253334SXiaojian Du return ret;
1959fd253334SXiaojian Du
19607cab3cffSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1961fd253334SXiaojian Du
196286c8236eSXiaojian Du gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
196386c8236eSXiaojian Du gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1964fd253334SXiaojian Du memcpy(&gpu_metrics->temperature_core[0],
196586c8236eSXiaojian Du &metrics.Current.CoreTemperature[0],
196686c8236eSXiaojian Du sizeof(uint16_t) * 4);
196786c8236eSXiaojian Du gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1968fd253334SXiaojian Du
196986c8236eSXiaojian Du gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
197086c8236eSXiaojian Du gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1971fd253334SXiaojian Du
197286c8236eSXiaojian Du gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
197386c8236eSXiaojian Du gpu_metrics->average_cpu_power = metrics.Current.Power[0];
197486c8236eSXiaojian Du gpu_metrics->average_soc_power = metrics.Current.Power[1];
197586c8236eSXiaojian Du gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1976fd253334SXiaojian Du memcpy(&gpu_metrics->average_core_power[0],
197786c8236eSXiaojian Du &metrics.Average.CorePower[0],
197886c8236eSXiaojian Du sizeof(uint16_t) * 4);
1979fd253334SXiaojian Du
198086c8236eSXiaojian Du gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
198186c8236eSXiaojian Du gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
198286c8236eSXiaojian Du gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
198386c8236eSXiaojian Du gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
198486c8236eSXiaojian Du gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
198586c8236eSXiaojian Du gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
198686c8236eSXiaojian Du
198786c8236eSXiaojian Du gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
198886c8236eSXiaojian Du gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
198986c8236eSXiaojian Du gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
199086c8236eSXiaojian Du gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
199186c8236eSXiaojian Du gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
199286c8236eSXiaojian Du gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1993fd253334SXiaojian Du
1994fd253334SXiaojian Du memcpy(&gpu_metrics->current_coreclk[0],
199586c8236eSXiaojian Du &metrics.Current.CoreFrequency[0],
199686c8236eSXiaojian Du sizeof(uint16_t) * 4);
199786c8236eSXiaojian Du gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1998fd253334SXiaojian Du
199986c8236eSXiaojian Du gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
20007cab3cffSGraham Sider gpu_metrics->indep_throttle_status =
20017cab3cffSGraham Sider smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
20027cab3cffSGraham Sider vangogh_throttler_map);
2003fd253334SXiaojian Du
2004de4b7cd8SKevin Wang gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2005de4b7cd8SKevin Wang
2006fd253334SXiaojian Du *table = (void *)gpu_metrics;
2007fd253334SXiaojian Du
20087cab3cffSGraham Sider return sizeof(struct gpu_metrics_v2_2);
2009fd253334SXiaojian Du }
2010fd253334SXiaojian Du
vangogh_common_get_gpu_metrics(struct smu_context * smu,void ** table)201186c8236eSXiaojian Du static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
201286c8236eSXiaojian Du void **table)
201386c8236eSXiaojian Du {
201486c8236eSXiaojian Du uint32_t if_version;
20150d6516efSLi Ma uint32_t smu_version;
201641cec40bSWenyou Yang uint32_t smu_program;
201741cec40bSWenyou Yang uint32_t fw_version;
201886c8236eSXiaojian Du int ret = 0;
201986c8236eSXiaojian Du
20200d6516efSLi Ma ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
202141cec40bSWenyou Yang if (ret)
202286c8236eSXiaojian Du return ret;
202386c8236eSXiaojian Du
202441cec40bSWenyou Yang smu_program = (smu_version >> 24) & 0xff;
202541cec40bSWenyou Yang fw_version = smu_version & 0xffffff;
202641cec40bSWenyou Yang if (smu_program == 6) {
202741cec40bSWenyou Yang if (fw_version >= 0x3F0800)
202841cec40bSWenyou Yang ret = vangogh_get_gpu_metrics_v2_4(smu, table);
202941cec40bSWenyou Yang else
203041cec40bSWenyou Yang ret = vangogh_get_gpu_metrics_v2_3(smu, table);
203141cec40bSWenyou Yang
203241cec40bSWenyou Yang } else {
20330d6516efSLi Ma if (smu_version >= 0x043F3E00) {
20340d6516efSLi Ma if (if_version < 0x3)
20350d6516efSLi Ma ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
20360d6516efSLi Ma else
20370d6516efSLi Ma ret = vangogh_get_gpu_metrics_v2_3(smu, table);
20380d6516efSLi Ma } else {
203986c8236eSXiaojian Du if (if_version < 0x3)
204086c8236eSXiaojian Du ret = vangogh_get_legacy_gpu_metrics(smu, table);
204186c8236eSXiaojian Du else
204286c8236eSXiaojian Du ret = vangogh_get_gpu_metrics(smu, table);
20430d6516efSLi Ma }
204441cec40bSWenyou Yang }
204586c8236eSXiaojian Du
204686c8236eSXiaojian Du return ret;
204786c8236eSXiaojian Du }
204886c8236eSXiaojian Du
vangogh_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2049c98ee897SXiaojian Du static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2050c98ee897SXiaojian Du long input[], uint32_t size)
2051c98ee897SXiaojian Du {
2052c98ee897SXiaojian Du int ret = 0;
2053d7379efaSXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2054c98ee897SXiaojian Du
2055d7379efaSXiaojian Du if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
2056d7ef887fSXiaojian Du dev_warn(smu->adev->dev,
2057ce7c670dSColin Ian King "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
2058c98ee897SXiaojian Du return -EINVAL;
2059c98ee897SXiaojian Du }
2060c98ee897SXiaojian Du
2061c98ee897SXiaojian Du switch (type) {
20620d90d0ddSHuang Rui case PP_OD_EDIT_CCLK_VDDC_TABLE:
20630d90d0ddSHuang Rui if (size != 3) {
20640d90d0ddSHuang Rui dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
20650d90d0ddSHuang Rui return -EINVAL;
20660d90d0ddSHuang Rui }
20674aef0ebcSHuang Rui if (input[0] >= smu->cpu_core_num) {
20680d90d0ddSHuang Rui dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
20694aef0ebcSHuang Rui smu->cpu_core_num);
20700d90d0ddSHuang Rui }
20710d90d0ddSHuang Rui smu->cpu_core_id_select = input[0];
20720d90d0ddSHuang Rui if (input[1] == 0) {
20730d90d0ddSHuang Rui if (input[2] < smu->cpu_default_soft_min_freq) {
20740d90d0ddSHuang Rui dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
20750d90d0ddSHuang Rui input[2], smu->cpu_default_soft_min_freq);
20760d90d0ddSHuang Rui return -EINVAL;
20770d90d0ddSHuang Rui }
20780d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = input[2];
20790d90d0ddSHuang Rui } else if (input[1] == 1) {
20800d90d0ddSHuang Rui if (input[2] > smu->cpu_default_soft_max_freq) {
20810d90d0ddSHuang Rui dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
20820d90d0ddSHuang Rui input[2], smu->cpu_default_soft_max_freq);
20830d90d0ddSHuang Rui return -EINVAL;
20840d90d0ddSHuang Rui }
20850d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = input[2];
20860d90d0ddSHuang Rui } else {
20870d90d0ddSHuang Rui return -EINVAL;
20880d90d0ddSHuang Rui }
20890d90d0ddSHuang Rui break;
2090c98ee897SXiaojian Du case PP_OD_EDIT_SCLK_VDDC_TABLE:
2091c98ee897SXiaojian Du if (size != 2) {
2092c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
2093c98ee897SXiaojian Du return -EINVAL;
2094c98ee897SXiaojian Du }
2095c98ee897SXiaojian Du
2096c98ee897SXiaojian Du if (input[0] == 0) {
2097c98ee897SXiaojian Du if (input[1] < smu->gfx_default_hard_min_freq) {
2098307f049bSXiaojian Du dev_warn(smu->adev->dev,
2099307f049bSXiaojian Du "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2100c98ee897SXiaojian Du input[1], smu->gfx_default_hard_min_freq);
2101c98ee897SXiaojian Du return -EINVAL;
2102c98ee897SXiaojian Du }
2103c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = input[1];
2104c98ee897SXiaojian Du } else if (input[0] == 1) {
2105c98ee897SXiaojian Du if (input[1] > smu->gfx_default_soft_max_freq) {
2106307f049bSXiaojian Du dev_warn(smu->adev->dev,
2107307f049bSXiaojian Du "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2108c98ee897SXiaojian Du input[1], smu->gfx_default_soft_max_freq);
2109c98ee897SXiaojian Du return -EINVAL;
2110c98ee897SXiaojian Du }
2111c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = input[1];
2112c98ee897SXiaojian Du } else {
2113c98ee897SXiaojian Du return -EINVAL;
2114c98ee897SXiaojian Du }
2115c98ee897SXiaojian Du break;
2116c98ee897SXiaojian Du case PP_OD_RESTORE_DEFAULT_TABLE:
2117c98ee897SXiaojian Du if (size != 0) {
2118c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
2119c98ee897SXiaojian Du return -EINVAL;
2120c98ee897SXiaojian Du } else {
2121c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2122c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
21230d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
21240d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2125c98ee897SXiaojian Du }
2126c98ee897SXiaojian Du break;
2127c98ee897SXiaojian Du case PP_OD_COMMIT_DPM_TABLE:
2128c98ee897SXiaojian Du if (size != 0) {
2129c98ee897SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
2130c98ee897SXiaojian Du return -EINVAL;
2131c98ee897SXiaojian Du } else {
2132c98ee897SXiaojian Du if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2133307f049bSXiaojian Du dev_err(smu->adev->dev,
2134f5d8e164SColin Ian King "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2135307f049bSXiaojian Du smu->gfx_actual_hard_min_freq,
2136307f049bSXiaojian Du smu->gfx_actual_soft_max_freq);
2137c98ee897SXiaojian Du return -EINVAL;
2138c98ee897SXiaojian Du }
2139c98ee897SXiaojian Du
2140c98ee897SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2141c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq, NULL);
2142c98ee897SXiaojian Du if (ret) {
2143c98ee897SXiaojian Du dev_err(smu->adev->dev, "Set hard min sclk failed!");
2144c98ee897SXiaojian Du return ret;
2145c98ee897SXiaojian Du }
2146c98ee897SXiaojian Du
2147c98ee897SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2148c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq, NULL);
2149c98ee897SXiaojian Du if (ret) {
2150c98ee897SXiaojian Du dev_err(smu->adev->dev, "Set soft max sclk failed!");
2151c98ee897SXiaojian Du return ret;
2152c98ee897SXiaojian Du }
21530d90d0ddSHuang Rui
21540d90d0ddSHuang Rui if (smu->adev->pm.fw_version < 0x43f1b00) {
21550d90d0ddSHuang Rui dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
21560d90d0ddSHuang Rui break;
21570d90d0ddSHuang Rui }
21580d90d0ddSHuang Rui
21590d90d0ddSHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
21600d90d0ddSHuang Rui ((smu->cpu_core_id_select << 20)
21610d90d0ddSHuang Rui | smu->cpu_actual_soft_min_freq),
21620d90d0ddSHuang Rui NULL);
21630d90d0ddSHuang Rui if (ret) {
21640d90d0ddSHuang Rui dev_err(smu->adev->dev, "Set hard min cclk failed!");
21650d90d0ddSHuang Rui return ret;
21660d90d0ddSHuang Rui }
21670d90d0ddSHuang Rui
21680d90d0ddSHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
21690d90d0ddSHuang Rui ((smu->cpu_core_id_select << 20)
21700d90d0ddSHuang Rui | smu->cpu_actual_soft_max_freq),
21710d90d0ddSHuang Rui NULL);
21720d90d0ddSHuang Rui if (ret) {
21730d90d0ddSHuang Rui dev_err(smu->adev->dev, "Set soft max cclk failed!");
21740d90d0ddSHuang Rui return ret;
21750d90d0ddSHuang Rui }
2176c98ee897SXiaojian Du }
2177c98ee897SXiaojian Du break;
2178c98ee897SXiaojian Du default:
2179c98ee897SXiaojian Du return -ENOSYS;
2180c98ee897SXiaojian Du }
2181c98ee897SXiaojian Du
2182c98ee897SXiaojian Du return ret;
2183c98ee897SXiaojian Du }
2184c98ee897SXiaojian Du
vangogh_set_default_dpm_tables(struct smu_context * smu)2185fce8a4acSJinzhou Su static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2186c98ee897SXiaojian Du {
2187c98ee897SXiaojian Du struct smu_table_context *smu_table = &smu->smu_table;
2188c98ee897SXiaojian Du
2189c98ee897SXiaojian Du return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2190c98ee897SXiaojian Du }
2191c98ee897SXiaojian Du
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)2192c98ee897SXiaojian Du static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2193c98ee897SXiaojian Du {
2194c98ee897SXiaojian Du DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2195c98ee897SXiaojian Du
2196c98ee897SXiaojian Du smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2197c98ee897SXiaojian Du smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2198c98ee897SXiaojian Du smu->gfx_actual_hard_min_freq = 0;
2199c98ee897SXiaojian Du smu->gfx_actual_soft_max_freq = 0;
2200c98ee897SXiaojian Du
22010d90d0ddSHuang Rui smu->cpu_default_soft_min_freq = 1400;
22020d90d0ddSHuang Rui smu->cpu_default_soft_max_freq = 3500;
22030d90d0ddSHuang Rui smu->cpu_actual_soft_min_freq = 0;
22040d90d0ddSHuang Rui smu->cpu_actual_soft_max_freq = 0;
22050d90d0ddSHuang Rui
2206c98ee897SXiaojian Du return 0;
2207c98ee897SXiaojian Du }
2208c98ee897SXiaojian Du
vangogh_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)2209ae7b32e7SXiaojian Du static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2210ae7b32e7SXiaojian Du {
2211ae7b32e7SXiaojian Du DpmClocks_t *table = smu->smu_table.clocks_table;
2212ae7b32e7SXiaojian Du int i;
2213ae7b32e7SXiaojian Du
2214ae7b32e7SXiaojian Du if (!clock_table || !table)
2215ae7b32e7SXiaojian Du return -EINVAL;
2216ae7b32e7SXiaojian Du
2217ae7b32e7SXiaojian Du for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
2218ae7b32e7SXiaojian Du clock_table->SocClocks[i].Freq = table->SocClocks[i];
2219ae7b32e7SXiaojian Du clock_table->SocClocks[i].Vol = table->SocVoltage[i];
2220ae7b32e7SXiaojian Du }
2221ae7b32e7SXiaojian Du
2222ae7b32e7SXiaojian Du for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2223ae7b32e7SXiaojian Du clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
2224ae7b32e7SXiaojian Du clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
2225ae7b32e7SXiaojian Du }
2226ae7b32e7SXiaojian Du
2227ae7b32e7SXiaojian Du for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2228ae7b32e7SXiaojian Du clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
2229ae7b32e7SXiaojian Du clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
2230ae7b32e7SXiaojian Du }
2231ae7b32e7SXiaojian Du
2232ae7b32e7SXiaojian Du return 0;
2233ae7b32e7SXiaojian Du }
2234ae7b32e7SXiaojian Du
2235ae7b32e7SXiaojian Du
vangogh_system_features_control(struct smu_context * smu,bool en)2236a0f55287SXiaomeng Hou static int vangogh_system_features_control(struct smu_context *smu, bool en)
2237a0f55287SXiaomeng Hou {
22389e3a6ab7SXiaomeng Hou struct amdgpu_device *adev = smu->adev;
2239aedebd40SHuang Rui int ret = 0;
22409e3a6ab7SXiaomeng Hou
22415b2e2c09SAlex Deucher if (adev->pm.fw_version >= 0x43f1700 && !en)
2242aedebd40SHuang Rui ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
22435b2e2c09SAlex Deucher RLC_STATUS_OFF, NULL);
2244aedebd40SHuang Rui
2245aedebd40SHuang Rui return ret;
2246a0f55287SXiaomeng Hou }
2247a0f55287SXiaomeng Hou
vangogh_post_smu_init(struct smu_context * smu)2248eefdf047SJinzhou Su static int vangogh_post_smu_init(struct smu_context *smu)
2249eefdf047SJinzhou Su {
2250eefdf047SJinzhou Su struct amdgpu_device *adev = smu->adev;
2251eefdf047SJinzhou Su uint32_t tmp;
22523313ef18SJinzhou Su int ret = 0;
2253eefdf047SJinzhou Su uint8_t aon_bits = 0;
2254eefdf047SJinzhou Su /* Two CUs in one WGP */
2255eefdf047SJinzhou Su uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2256eefdf047SJinzhou Su uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2257eefdf047SJinzhou Su adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2258eefdf047SJinzhou Su
22593313ef18SJinzhou Su /* allow message will be sent after enable message on Vangogh*/
22607ade3ca9SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2261bb377febSJinzhou Su (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
22623313ef18SJinzhou Su ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
22633313ef18SJinzhou Su if (ret) {
22643313ef18SJinzhou Su dev_err(adev->dev, "Failed to Enable GfxOff!\n");
22653313ef18SJinzhou Su return ret;
22663313ef18SJinzhou Su }
2267bb377febSJinzhou Su } else {
2268bb377febSJinzhou Su adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2269bb377febSJinzhou Su dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2270bb377febSJinzhou Su }
22713313ef18SJinzhou Su
2272eefdf047SJinzhou Su /* if all CUs are active, no need to power off any WGPs */
2273eefdf047SJinzhou Su if (total_cu == adev->gfx.cu_info.number)
2274eefdf047SJinzhou Su return 0;
2275eefdf047SJinzhou Su
2276eefdf047SJinzhou Su /*
2277eefdf047SJinzhou Su * Calculate the total bits number of always on WGPs for all SA/SEs in
2278eefdf047SJinzhou Su * RLC_PG_ALWAYS_ON_WGP_MASK.
2279eefdf047SJinzhou Su */
2280eefdf047SJinzhou Su tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2281eefdf047SJinzhou Su tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2282eefdf047SJinzhou Su
2283eefdf047SJinzhou Su aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2284eefdf047SJinzhou Su
2285eefdf047SJinzhou Su /* Do not request any WGPs less than set in the AON_WGP_MASK */
2286eefdf047SJinzhou Su if (aon_bits > req_active_wgps) {
2287eefdf047SJinzhou Su dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2288eefdf047SJinzhou Su return 0;
2289eefdf047SJinzhou Su } else {
2290eefdf047SJinzhou Su return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2291eefdf047SJinzhou Su }
2292eefdf047SJinzhou Su }
2293eefdf047SJinzhou Su
vangogh_mode_reset(struct smu_context * smu,int type)229474353883SHuang Rui static int vangogh_mode_reset(struct smu_context *smu, int type)
229574353883SHuang Rui {
229674353883SHuang Rui int ret = 0, index = 0;
229774353883SHuang Rui
229874353883SHuang Rui index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
229974353883SHuang Rui SMU_MSG_GfxDeviceDriverReset);
230074353883SHuang Rui if (index < 0)
230174353883SHuang Rui return index == -EACCES ? 0 : index;
230274353883SHuang Rui
230374353883SHuang Rui mutex_lock(&smu->message_lock);
230474353883SHuang Rui
230574353883SHuang Rui ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
230674353883SHuang Rui
230774353883SHuang Rui mutex_unlock(&smu->message_lock);
230874353883SHuang Rui
230974353883SHuang Rui mdelay(10);
231074353883SHuang Rui
231174353883SHuang Rui return ret;
231274353883SHuang Rui }
231374353883SHuang Rui
vangogh_mode2_reset(struct smu_context * smu)231420e157c7SAlex Deucher static int vangogh_mode2_reset(struct smu_context *smu)
231520e157c7SAlex Deucher {
231674353883SHuang Rui return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
231720e157c7SAlex Deucher }
231820e157c7SAlex Deucher
231943195162SAndré Almeida /**
232043195162SAndré Almeida * vangogh_get_gfxoff_status - Get gfxoff status
232143195162SAndré Almeida *
232243195162SAndré Almeida * @smu: amdgpu_device pointer
232343195162SAndré Almeida *
232443195162SAndré Almeida * Get current gfxoff status
232543195162SAndré Almeida *
232643195162SAndré Almeida * Return:
232743195162SAndré Almeida * * 0 - GFXOFF (default if enabled).
232843195162SAndré Almeida * * 1 - Transition out of GFX State.
232943195162SAndré Almeida * * 2 - Not in GFXOFF.
233043195162SAndré Almeida * * 3 - Transition into GFXOFF.
233143195162SAndré Almeida */
vangogh_get_gfxoff_status(struct smu_context * smu)233243195162SAndré Almeida static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
233343195162SAndré Almeida {
233443195162SAndré Almeida struct amdgpu_device *adev = smu->adev;
233543195162SAndré Almeida u32 reg, gfxoff_status;
233643195162SAndré Almeida
233743195162SAndré Almeida reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
233843195162SAndré Almeida gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
233943195162SAndré Almeida >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
234043195162SAndré Almeida
234143195162SAndré Almeida return gfxoff_status;
234243195162SAndré Almeida }
234343195162SAndré Almeida
vangogh_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)2344488f211dSEvan Quan static int vangogh_get_power_limit(struct smu_context *smu,
2345488f211dSEvan Quan uint32_t *current_power_limit,
2346488f211dSEvan Quan uint32_t *default_power_limit,
2347488f211dSEvan Quan uint32_t *max_power_limit)
2348ae07970aSXiaomeng Hou {
2349ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context =
2350ae07970aSXiaomeng Hou smu->smu_power.power_context;
2351ae07970aSXiaomeng Hou uint32_t ppt_limit;
2352ae07970aSXiaomeng Hou int ret = 0;
2353ae07970aSXiaomeng Hou
2354ae07970aSXiaomeng Hou if (smu->adev->pm.fw_version < 0x43f1e00)
2355ae07970aSXiaomeng Hou return ret;
2356ae07970aSXiaomeng Hou
2357ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2358ae07970aSXiaomeng Hou if (ret) {
2359ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2360ae07970aSXiaomeng Hou return ret;
2361ae07970aSXiaomeng Hou }
2362ae07970aSXiaomeng Hou /* convert from milliwatt to watt */
2363488f211dSEvan Quan if (current_power_limit)
2364488f211dSEvan Quan *current_power_limit = ppt_limit / 1000;
2365488f211dSEvan Quan if (default_power_limit)
2366488f211dSEvan Quan *default_power_limit = ppt_limit / 1000;
2367488f211dSEvan Quan if (max_power_limit)
2368488f211dSEvan Quan *max_power_limit = 29;
2369ae07970aSXiaomeng Hou
2370ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2371ae07970aSXiaomeng Hou if (ret) {
2372ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2373ae07970aSXiaomeng Hou return ret;
2374ae07970aSXiaomeng Hou }
2375ae07970aSXiaomeng Hou /* convert from milliwatt to watt */
23766e58941cSEric Huang power_context->current_fast_ppt_limit =
23776e58941cSEric Huang power_context->default_fast_ppt_limit = ppt_limit / 1000;
2378ae07970aSXiaomeng Hou power_context->max_fast_ppt_limit = 30;
2379ae07970aSXiaomeng Hou
2380ae07970aSXiaomeng Hou return ret;
2381ae07970aSXiaomeng Hou }
2382ae07970aSXiaomeng Hou
vangogh_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)2383ae07970aSXiaomeng Hou static int vangogh_get_ppt_limit(struct smu_context *smu,
2384ae07970aSXiaomeng Hou uint32_t *ppt_limit,
2385ae07970aSXiaomeng Hou enum smu_ppt_limit_type type,
2386ae07970aSXiaomeng Hou enum smu_ppt_limit_level level)
2387ae07970aSXiaomeng Hou {
2388ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context =
2389ae07970aSXiaomeng Hou smu->smu_power.power_context;
2390ae07970aSXiaomeng Hou
2391ae07970aSXiaomeng Hou if (!power_context)
2392ae07970aSXiaomeng Hou return -EOPNOTSUPP;
2393ae07970aSXiaomeng Hou
2394ae07970aSXiaomeng Hou if (type == SMU_FAST_PPT_LIMIT) {
2395ae07970aSXiaomeng Hou switch (level) {
2396ae07970aSXiaomeng Hou case SMU_PPT_LIMIT_MAX:
2397ae07970aSXiaomeng Hou *ppt_limit = power_context->max_fast_ppt_limit;
2398ae07970aSXiaomeng Hou break;
2399ae07970aSXiaomeng Hou case SMU_PPT_LIMIT_CURRENT:
2400ae07970aSXiaomeng Hou *ppt_limit = power_context->current_fast_ppt_limit;
2401ae07970aSXiaomeng Hou break;
24026e58941cSEric Huang case SMU_PPT_LIMIT_DEFAULT:
24036e58941cSEric Huang *ppt_limit = power_context->default_fast_ppt_limit;
24046e58941cSEric Huang break;
2405ae07970aSXiaomeng Hou default:
2406ae07970aSXiaomeng Hou break;
2407ae07970aSXiaomeng Hou }
2408ae07970aSXiaomeng Hou }
2409ae07970aSXiaomeng Hou
2410ae07970aSXiaomeng Hou return 0;
2411ae07970aSXiaomeng Hou }
2412ae07970aSXiaomeng Hou
vangogh_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t ppt_limit)24132d1ac1cbSDarren Powell static int vangogh_set_power_limit(struct smu_context *smu,
24142d1ac1cbSDarren Powell enum smu_ppt_limit_type limit_type,
24152d1ac1cbSDarren Powell uint32_t ppt_limit)
2416ae07970aSXiaomeng Hou {
2417ae07970aSXiaomeng Hou struct smu_11_5_power_context *power_context =
2418ae07970aSXiaomeng Hou smu->smu_power.power_context;
2419ae07970aSXiaomeng Hou int ret = 0;
2420ae07970aSXiaomeng Hou
2421ae07970aSXiaomeng Hou if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2422ae07970aSXiaomeng Hou dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2423ae07970aSXiaomeng Hou return -EOPNOTSUPP;
2424ae07970aSXiaomeng Hou }
2425ae07970aSXiaomeng Hou
2426ae07970aSXiaomeng Hou switch (limit_type) {
2427ae07970aSXiaomeng Hou case SMU_DEFAULT_PPT_LIMIT:
2428ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg_with_param(smu,
2429ae07970aSXiaomeng Hou SMU_MSG_SetSlowPPTLimit,
2430ae07970aSXiaomeng Hou ppt_limit * 1000, /* convert from watt to milliwatt */
2431ae07970aSXiaomeng Hou NULL);
2432ae07970aSXiaomeng Hou if (ret)
2433ae07970aSXiaomeng Hou return ret;
2434ae07970aSXiaomeng Hou
2435ae07970aSXiaomeng Hou smu->current_power_limit = ppt_limit;
2436ae07970aSXiaomeng Hou break;
2437ae07970aSXiaomeng Hou case SMU_FAST_PPT_LIMIT:
2438ae07970aSXiaomeng Hou ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2439ae07970aSXiaomeng Hou if (ppt_limit > power_context->max_fast_ppt_limit) {
2440ae07970aSXiaomeng Hou dev_err(smu->adev->dev,
2441ae07970aSXiaomeng Hou "New power limit (%d) is over the max allowed %d\n",
2442ae07970aSXiaomeng Hou ppt_limit, power_context->max_fast_ppt_limit);
2443ae07970aSXiaomeng Hou return ret;
2444ae07970aSXiaomeng Hou }
2445ae07970aSXiaomeng Hou
2446ae07970aSXiaomeng Hou ret = smu_cmn_send_smc_msg_with_param(smu,
2447ae07970aSXiaomeng Hou SMU_MSG_SetFastPPTLimit,
2448ae07970aSXiaomeng Hou ppt_limit * 1000, /* convert from watt to milliwatt */
2449ae07970aSXiaomeng Hou NULL);
2450ae07970aSXiaomeng Hou if (ret)
2451ae07970aSXiaomeng Hou return ret;
2452ae07970aSXiaomeng Hou
2453ae07970aSXiaomeng Hou power_context->current_fast_ppt_limit = ppt_limit;
2454ae07970aSXiaomeng Hou break;
2455ae07970aSXiaomeng Hou default:
2456ae07970aSXiaomeng Hou return -EINVAL;
2457ae07970aSXiaomeng Hou }
2458ae07970aSXiaomeng Hou
2459ae07970aSXiaomeng Hou return ret;
2460ae07970aSXiaomeng Hou }
2461ae07970aSXiaomeng Hou
24621ed5a845SAndré Almeida /**
24631ed5a845SAndré Almeida * vangogh_set_gfxoff_residency
24641ed5a845SAndré Almeida *
24651ed5a845SAndré Almeida * @smu: amdgpu_device pointer
24661ed5a845SAndré Almeida * @start: start/stop residency log
24671ed5a845SAndré Almeida *
24681ed5a845SAndré Almeida * This function will be used to log gfxoff residency
24691ed5a845SAndré Almeida *
24701ed5a845SAndré Almeida *
24711ed5a845SAndré Almeida * Returns standard response codes.
24721ed5a845SAndré Almeida */
vangogh_set_gfxoff_residency(struct smu_context * smu,bool start)24731ed5a845SAndré Almeida static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
24741ed5a845SAndré Almeida {
24751ed5a845SAndré Almeida int ret = 0;
24761ed5a845SAndré Almeida u32 residency;
24771ed5a845SAndré Almeida struct amdgpu_device *adev = smu->adev;
24781ed5a845SAndré Almeida
24791ed5a845SAndré Almeida if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
24801ed5a845SAndré Almeida return 0;
24811ed5a845SAndré Almeida
24821ed5a845SAndré Almeida ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
24831ed5a845SAndré Almeida start, &residency);
24841ed5a845SAndré Almeida
24851ed5a845SAndré Almeida if (!start)
24861ed5a845SAndré Almeida adev->gfx.gfx_off_residency = residency;
24871ed5a845SAndré Almeida
24881ed5a845SAndré Almeida return ret;
24891ed5a845SAndré Almeida }
24901ed5a845SAndré Almeida
24911ed5a845SAndré Almeida /**
24921ed5a845SAndré Almeida * vangogh_get_gfxoff_residency
24931ed5a845SAndré Almeida *
24941ed5a845SAndré Almeida * @smu: amdgpu_device pointer
249563d99a34SLee Jones * @residency: placeholder for return value
24961ed5a845SAndré Almeida *
24971ed5a845SAndré Almeida * This function will be used to get gfxoff residency.
24981ed5a845SAndré Almeida *
24991ed5a845SAndré Almeida * Returns standard response codes.
25001ed5a845SAndré Almeida */
vangogh_get_gfxoff_residency(struct smu_context * smu,uint32_t * residency)25011ed5a845SAndré Almeida static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
25021ed5a845SAndré Almeida {
25031ed5a845SAndré Almeida struct amdgpu_device *adev = smu->adev;
25041ed5a845SAndré Almeida
25051ed5a845SAndré Almeida *residency = adev->gfx.gfx_off_residency;
25061ed5a845SAndré Almeida
25071ed5a845SAndré Almeida return 0;
25081ed5a845SAndré Almeida }
25091ed5a845SAndré Almeida
25101ed5a845SAndré Almeida /**
25111ed5a845SAndré Almeida * vangogh_get_gfxoff_entrycount - get gfxoff entry count
25121ed5a845SAndré Almeida *
25131ed5a845SAndré Almeida * @smu: amdgpu_device pointer
251463d99a34SLee Jones * @entrycount: placeholder for return value
25151ed5a845SAndré Almeida *
25161ed5a845SAndré Almeida * This function will be used to get gfxoff entry count
25171ed5a845SAndré Almeida *
25181ed5a845SAndré Almeida * Returns standard response codes.
25191ed5a845SAndré Almeida */
vangogh_get_gfxoff_entrycount(struct smu_context * smu,uint64_t * entrycount)25201ed5a845SAndré Almeida static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
25211ed5a845SAndré Almeida {
25221ed5a845SAndré Almeida int ret = 0, value = 0;
25231ed5a845SAndré Almeida struct amdgpu_device *adev = smu->adev;
25241ed5a845SAndré Almeida
25251ed5a845SAndré Almeida if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
25261ed5a845SAndré Almeida return 0;
25271ed5a845SAndré Almeida
25281ed5a845SAndré Almeida ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
25291ed5a845SAndré Almeida *entrycount = value + adev->gfx.gfx_off_entrycount;
25301ed5a845SAndré Almeida
25311ed5a845SAndré Almeida return ret;
25321ed5a845SAndré Almeida }
25331ed5a845SAndré Almeida
2534f46a221bSXiaojian Du static const struct pptable_funcs vangogh_ppt_funcs = {
2535271ab489SXiaojian Du
2536f46a221bSXiaojian Du .check_fw_status = smu_v11_0_check_fw_status,
2537f46a221bSXiaojian Du .check_fw_version = smu_v11_0_check_fw_version,
2538f46a221bSXiaojian Du .init_smc_tables = vangogh_init_smc_tables,
2539f46a221bSXiaojian Du .fini_smc_tables = smu_v11_0_fini_smc_tables,
2540f46a221bSXiaojian Du .init_power = smu_v11_0_init_power,
2541f46a221bSXiaojian Du .fini_power = smu_v11_0_fini_power,
2542f46a221bSXiaojian Du .register_irq_handler = smu_v11_0_register_irq_handler,
2543f46a221bSXiaojian Du .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2544f46a221bSXiaojian Du .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2545f46a221bSXiaojian Du .send_smc_msg = smu_cmn_send_smc_msg,
2546271ab489SXiaojian Du .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2547271ab489SXiaojian Du .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2548f46a221bSXiaojian Du .is_dpm_running = vangogh_is_dpm_running,
2549271ab489SXiaojian Du .read_sensor = vangogh_read_sensor,
25500c3c9936SKun Liu .get_apu_thermal_limit = vangogh_get_apu_thermal_limit,
25510c3c9936SKun Liu .set_apu_thermal_limit = vangogh_set_apu_thermal_limit,
25525af779adSEvan Quan .get_enabled_mask = smu_cmn_get_enabled_mask,
2553f46a221bSXiaojian Du .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2554271ab489SXiaojian Du .set_watermarks_table = vangogh_set_watermarks_table,
2555271ab489SXiaojian Du .set_driver_table_location = smu_v11_0_set_driver_table_location,
2556f46a221bSXiaojian Du .interrupt_work = smu_v11_0_interrupt_work,
255786c8236eSXiaojian Du .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2558c98ee897SXiaojian Du .od_edit_dpm_table = vangogh_od_edit_dpm_table,
255986c8236eSXiaojian Du .print_clk_levels = vangogh_common_print_clk_levels,
2560c98ee897SXiaojian Du .set_default_dpm_table = vangogh_set_default_dpm_tables,
2561c98ee897SXiaojian Du .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2562a0f55287SXiaomeng Hou .system_features_control = vangogh_system_features_control,
2563d0e4e112SXiaojian Du .feature_is_enabled = smu_cmn_feature_is_enabled,
2564d0e4e112SXiaojian Du .set_power_profile_mode = vangogh_set_power_profile_mode,
2565307f049bSXiaojian Du .get_power_profile_mode = vangogh_get_power_profile_mode,
2566ae7b32e7SXiaojian Du .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2567dd9e0b21SXiaojian Du .force_clk_levels = vangogh_force_clk_levels,
2568ea173d15SXiaojian Du .set_performance_level = vangogh_set_performance_level,
2569eefdf047SJinzhou Su .post_init = vangogh_post_smu_init,
257020e157c7SAlex Deucher .mode2_reset = vangogh_mode2_reset,
2571b58ce1feSJinzhou Su .gfx_off_control = smu_v11_0_gfx_off_control,
257243195162SAndré Almeida .get_gfx_off_status = vangogh_get_gfxoff_status,
25731ed5a845SAndré Almeida .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount,
25741ed5a845SAndré Almeida .get_gfx_off_residency = vangogh_get_gfxoff_residency,
25751ed5a845SAndré Almeida .set_gfx_off_residency = vangogh_set_gfxoff_residency,
2576ae07970aSXiaomeng Hou .get_ppt_limit = vangogh_get_ppt_limit,
2577ae07970aSXiaomeng Hou .get_power_limit = vangogh_get_power_limit,
2578ae07970aSXiaomeng Hou .set_power_limit = vangogh_set_power_limit,
25793495d3c3SXiaojian Du .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2580f46a221bSXiaojian Du };
2581f46a221bSXiaojian Du
vangogh_set_ppt_funcs(struct smu_context * smu)2582f46a221bSXiaojian Du void vangogh_set_ppt_funcs(struct smu_context *smu)
2583f46a221bSXiaojian Du {
2584f46a221bSXiaojian Du smu->ppt_funcs = &vangogh_ppt_funcs;
2585f46a221bSXiaojian Du smu->message_map = vangogh_message_map;
2586f46a221bSXiaojian Du smu->feature_map = vangogh_feature_mask_map;
2587f46a221bSXiaojian Du smu->table_map = vangogh_table_map;
2588ec3b35c8SXiaojian Du smu->workload_map = vangogh_workload_map;
2589f46a221bSXiaojian Du smu->is_apu = true;
2590da1db031SAlex Deucher smu_v11_0_set_smu_mailbox_registers(smu);
2591f46a221bSXiaojian Du }
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