155c89494STim Huang /*
255c89494STim Huang * Copyright 2022 Advanced Micro Devices, Inc.
355c89494STim Huang *
455c89494STim Huang * Permission is hereby granted, free of charge, to any person obtaining a
555c89494STim Huang * copy of this software and associated documentation files (the "Software"),
655c89494STim Huang * to deal in the Software without restriction, including without limitation
755c89494STim Huang * the rights to use, copy, modify, merge, publish, distribute, sublicense,
855c89494STim Huang * and/or sell copies of the Software, and to permit persons to whom the
955c89494STim Huang * Software is furnished to do so, subject to the following conditions:
1055c89494STim Huang *
1155c89494STim Huang * The above copyright notice and this permission notice shall be included in
1255c89494STim Huang * all copies or substantial portions of the Software.
1355c89494STim Huang *
1455c89494STim Huang * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
1555c89494STim Huang * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1655c89494STim Huang * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
1755c89494STim Huang * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
1855c89494STim Huang * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
1955c89494STim Huang * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2055c89494STim Huang * OTHER DEALINGS IN THE SOFTWARE.
2155c89494STim Huang *
2255c89494STim Huang */
2355c89494STim Huang
2455c89494STim Huang #include "smu_types.h"
2555c89494STim Huang #define SWSMU_CODE_LAYER_L2
2655c89494STim Huang
2755c89494STim Huang #include "amdgpu.h"
2855c89494STim Huang #include "amdgpu_smu.h"
2955c89494STim Huang #include "smu_v13_0.h"
3055c89494STim Huang #include "smu13_driver_if_v13_0_4.h"
3155c89494STim Huang #include "smu_v13_0_4_ppt.h"
3255c89494STim Huang #include "smu_v13_0_4_ppsmc.h"
3355c89494STim Huang #include "smu_v13_0_4_pmfw.h"
3455c89494STim Huang #include "smu_cmn.h"
3555c89494STim Huang
3655c89494STim Huang /*
3755c89494STim Huang * DO NOT use these for err/warn/info/debug messages.
3855c89494STim Huang * Use dev_err, dev_warn, dev_info and dev_dbg instead.
3955c89494STim Huang * They are more MGPU friendly.
4055c89494STim Huang */
4155c89494STim Huang #undef pr_err
4255c89494STim Huang #undef pr_warn
4355c89494STim Huang #undef pr_info
4455c89494STim Huang #undef pr_debug
4555c89494STim Huang
46da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_66 0x0282
47da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_66_BASE_IDX 1
48da1db031SAlex Deucher
49da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_82 0x0292
50da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_82_BASE_IDX 1
51da1db031SAlex Deucher
52da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_90 0x029a
53da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_90_BASE_IDX 1
54da1db031SAlex Deucher
5555c89494STim Huang #define FEATURE_MASK(feature) (1ULL << feature)
5655c89494STim Huang
5755682a89STim Huang #define SMU_13_0_4_UMD_PSTATE_GFXCLK 938
5855682a89STim Huang #define SMU_13_0_4_UMD_PSTATE_SOCCLK 938
5955682a89STim Huang #define SMU_13_0_4_UMD_PSTATE_FCLK 1875
6055682a89STim Huang
6155c89494STim Huang #define SMC_DPM_FEATURE ( \
6255c89494STim Huang FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
6355c89494STim Huang FEATURE_MASK(FEATURE_VCN_DPM_BIT) | \
6455c89494STim Huang FEATURE_MASK(FEATURE_FCLK_DPM_BIT) | \
6555c89494STim Huang FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT) | \
6655c89494STim Huang FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT) | \
6755c89494STim Huang FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
6855c89494STim Huang FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
6955c89494STim Huang FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT) | \
7055c89494STim Huang FEATURE_MASK(FEATURE_ISP_DPM_BIT) | \
7155c89494STim Huang FEATURE_MASK(FEATURE_IPU_DPM_BIT) | \
7255c89494STim Huang FEATURE_MASK(FEATURE_GFX_DPM_BIT))
7355c89494STim Huang
7455c89494STim Huang static struct cmn2asic_msg_mapping smu_v13_0_4_message_map[SMU_MSG_MAX_COUNT] = {
7555c89494STim Huang MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
7655c89494STim Huang MSG_MAP(GetSmuVersion, PPSMC_MSG_GetPmfwVersion, 1),
7755c89494STim Huang MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
7855c89494STim Huang MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 1),
7955c89494STim Huang MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 1),
8055c89494STim Huang MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
8155c89494STim Huang MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
8255c89494STim Huang MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
8355c89494STim Huang MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
8455c89494STim Huang MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
8555c89494STim Huang MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
8655c89494STim Huang MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
8755c89494STim Huang MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
8855c89494STim Huang MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
8955c89494STim Huang MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
9055c89494STim Huang MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
9155c89494STim Huang MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
9255c89494STim Huang MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
9355c89494STim Huang MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
9455c89494STim Huang MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
9555c89494STim Huang MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
9655c89494STim Huang MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
9755c89494STim Huang MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
9855c89494STim Huang MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
9955c89494STim Huang MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
10055c89494STim Huang MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
10155c89494STim Huang MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
10255c89494STim Huang MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
10355c89494STim Huang MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
10455c89494STim Huang MSG_MAP(EnableGfxImu, PPSMC_MSG_EnableGfxImu, 1),
10555c89494STim Huang MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
10655c89494STim Huang MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
10755c89494STim Huang };
10855c89494STim Huang
10955c89494STim Huang static struct cmn2asic_mapping smu_v13_0_4_feature_mask_map[SMU_FEATURE_COUNT] = {
11055c89494STim Huang FEA_MAP(CCLK_DPM),
11155c89494STim Huang FEA_MAP(FAN_CONTROLLER),
11255c89494STim Huang FEA_MAP(PPT),
11355c89494STim Huang FEA_MAP(TDC),
11455c89494STim Huang FEA_MAP(THERMAL),
11555c89494STim Huang FEA_MAP(VCN_DPM),
11655c89494STim Huang FEA_MAP_REVERSE(FCLK),
11755c89494STim Huang FEA_MAP_REVERSE(SOCCLK),
11855c89494STim Huang FEA_MAP(LCLK_DPM),
11955c89494STim Huang FEA_MAP(SHUBCLK_DPM),
12055c89494STim Huang FEA_MAP(DCFCLK_DPM),
12155c89494STim Huang FEA_MAP_HALF_REVERSE(GFX),
12255c89494STim Huang FEA_MAP(DS_GFXCLK),
12355c89494STim Huang FEA_MAP(DS_SOCCLK),
12455c89494STim Huang FEA_MAP(DS_LCLK),
12555c89494STim Huang FEA_MAP(DS_DCFCLK),
12655c89494STim Huang FEA_MAP(DS_FCLK),
12755c89494STim Huang FEA_MAP(DS_MP1CLK),
12855c89494STim Huang FEA_MAP(DS_MP0CLK),
12955c89494STim Huang FEA_MAP(GFX_DEM),
13055c89494STim Huang FEA_MAP(PSI),
13155c89494STim Huang FEA_MAP(PROCHOT),
13255c89494STim Huang FEA_MAP(CPUOFF),
13355c89494STim Huang FEA_MAP(STAPM),
13455c89494STim Huang FEA_MAP(S0I3),
13555c89494STim Huang FEA_MAP(PERF_LIMIT),
13655c89494STim Huang FEA_MAP(CORE_DLDO),
13755c89494STim Huang FEA_MAP(DS_VCN),
13855c89494STim Huang FEA_MAP(CPPC),
13955c89494STim Huang FEA_MAP(DF_CSTATES),
14055c89494STim Huang FEA_MAP(ATHUB_PG),
14155c89494STim Huang };
14255c89494STim Huang
14355c89494STim Huang static struct cmn2asic_mapping smu_v13_0_4_table_map[SMU_TABLE_COUNT] = {
14455c89494STim Huang TAB_MAP_VALID(WATERMARKS),
14555c89494STim Huang TAB_MAP_VALID(SMU_METRICS),
14655c89494STim Huang TAB_MAP_VALID(CUSTOM_DPM),
14755c89494STim Huang TAB_MAP_VALID(DPMCLOCKS),
14855c89494STim Huang };
14955c89494STim Huang
smu_v13_0_4_init_smc_tables(struct smu_context * smu)15055c89494STim Huang static int smu_v13_0_4_init_smc_tables(struct smu_context *smu)
15155c89494STim Huang {
15255c89494STim Huang struct smu_table_context *smu_table = &smu->smu_table;
15355c89494STim Huang struct smu_table *tables = smu_table->tables;
15455c89494STim Huang
15555c89494STim Huang SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
15655c89494STim Huang PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
15755c89494STim Huang SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
15855c89494STim Huang PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
15955c89494STim Huang SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
16055c89494STim Huang PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
16155c89494STim Huang
16255c89494STim Huang smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
16355c89494STim Huang if (!smu_table->clocks_table)
16455c89494STim Huang goto err0_out;
16555c89494STim Huang
16655c89494STim Huang smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
16755c89494STim Huang if (!smu_table->metrics_table)
16855c89494STim Huang goto err1_out;
16955c89494STim Huang smu_table->metrics_time = 0;
17055c89494STim Huang
17155c89494STim Huang smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
17255c89494STim Huang if (!smu_table->watermarks_table)
17355c89494STim Huang goto err2_out;
17455c89494STim Huang
17555c89494STim Huang smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
17655c89494STim Huang smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
17755c89494STim Huang if (!smu_table->gpu_metrics_table)
17855c89494STim Huang goto err3_out;
17955c89494STim Huang
18055c89494STim Huang return 0;
18155c89494STim Huang
18255c89494STim Huang err3_out:
18355c89494STim Huang kfree(smu_table->watermarks_table);
18455c89494STim Huang err2_out:
18555c89494STim Huang kfree(smu_table->metrics_table);
18655c89494STim Huang err1_out:
18755c89494STim Huang kfree(smu_table->clocks_table);
18855c89494STim Huang err0_out:
18955c89494STim Huang return -ENOMEM;
19055c89494STim Huang }
19155c89494STim Huang
smu_v13_0_4_fini_smc_tables(struct smu_context * smu)19255c89494STim Huang static int smu_v13_0_4_fini_smc_tables(struct smu_context *smu)
19355c89494STim Huang {
19455c89494STim Huang struct smu_table_context *smu_table = &smu->smu_table;
19555c89494STim Huang
19655c89494STim Huang kfree(smu_table->clocks_table);
19755c89494STim Huang smu_table->clocks_table = NULL;
19855c89494STim Huang
19955c89494STim Huang kfree(smu_table->metrics_table);
20055c89494STim Huang smu_table->metrics_table = NULL;
20155c89494STim Huang
20255c89494STim Huang kfree(smu_table->watermarks_table);
20355c89494STim Huang smu_table->watermarks_table = NULL;
20455c89494STim Huang
2055afb7652SZhen Ni kfree(smu_table->gpu_metrics_table);
2065afb7652SZhen Ni smu_table->gpu_metrics_table = NULL;
2075afb7652SZhen Ni
20855c89494STim Huang return 0;
20955c89494STim Huang }
21055c89494STim Huang
smu_v13_0_4_is_dpm_running(struct smu_context * smu)21155c89494STim Huang static bool smu_v13_0_4_is_dpm_running(struct smu_context *smu)
21255c89494STim Huang {
21355c89494STim Huang int ret = 0;
21455c89494STim Huang uint64_t feature_enabled;
21555c89494STim Huang
21655c89494STim Huang ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
21755c89494STim Huang
21855c89494STim Huang if (ret)
21955c89494STim Huang return false;
22055c89494STim Huang
22155c89494STim Huang return !!(feature_enabled & SMC_DPM_FEATURE);
22255c89494STim Huang }
22355c89494STim Huang
smu_v13_0_4_system_features_control(struct smu_context * smu,bool en)22455c89494STim Huang static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
22555c89494STim Huang {
22655c89494STim Huang struct amdgpu_device *adev = smu->adev;
22755c89494STim Huang int ret = 0;
228526e6ca5STim Huang
2297bc52dceSMario Limonciello if (!en && !adev->in_s0ix) {
2307bc52dceSMario Limonciello if (adev->in_s4) {
2311e3b8874STim Huang /* Adds a GFX reset as workaround just before sending the
2321e3b8874STim Huang * MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
2331e3b8874STim Huang * an invalid state.
2341e3b8874STim Huang */
2351e3b8874STim Huang ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
2361e3b8874STim Huang SMU_RESET_MODE_2, NULL);
2371e3b8874STim Huang if (ret)
2381e3b8874STim Huang return ret;
2397bc52dceSMario Limonciello }
2401e3b8874STim Huang
241526e6ca5STim Huang ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
2421e3b8874STim Huang }
243526e6ca5STim Huang
24455c89494STim Huang return ret;
24555c89494STim Huang }
24655c89494STim Huang
smu_v13_0_4_get_gpu_metrics(struct smu_context * smu,void ** table)24755c89494STim Huang static ssize_t smu_v13_0_4_get_gpu_metrics(struct smu_context *smu,
24855c89494STim Huang void **table)
24955c89494STim Huang {
25055c89494STim Huang struct smu_table_context *smu_table = &smu->smu_table;
25155c89494STim Huang struct gpu_metrics_v2_1 *gpu_metrics =
25255c89494STim Huang (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
25355c89494STim Huang SmuMetrics_t metrics;
25455c89494STim Huang int ret = 0;
25555c89494STim Huang
25655c89494STim Huang ret = smu_cmn_get_metrics_table(smu, &metrics, true);
25755c89494STim Huang if (ret)
25855c89494STim Huang return ret;
25955c89494STim Huang
26055c89494STim Huang smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
26155c89494STim Huang
26255c89494STim Huang gpu_metrics->temperature_gfx = metrics.GfxTemperature;
26355c89494STim Huang gpu_metrics->temperature_soc = metrics.SocTemperature;
26455c89494STim Huang memcpy(&gpu_metrics->temperature_core[0],
26555c89494STim Huang &metrics.CoreTemperature[0],
26655c89494STim Huang sizeof(uint16_t) * 8);
26755c89494STim Huang gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
26855c89494STim Huang
26955c89494STim Huang gpu_metrics->average_gfx_activity = metrics.GfxActivity;
27055c89494STim Huang gpu_metrics->average_mm_activity = metrics.UvdActivity;
27155c89494STim Huang
27262942567SMario Limonciello gpu_metrics->average_socket_power = metrics.AverageSocketPower;
27355c89494STim Huang gpu_metrics->average_gfx_power = metrics.Power[0];
27455c89494STim Huang gpu_metrics->average_soc_power = metrics.Power[1];
27555c89494STim Huang memcpy(&gpu_metrics->average_core_power[0],
27655c89494STim Huang &metrics.CorePower[0],
27755c89494STim Huang sizeof(uint16_t) * 8);
27855c89494STim Huang
27955c89494STim Huang gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
28055c89494STim Huang gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
28155c89494STim Huang gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
28255c89494STim Huang gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
28355c89494STim Huang gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
28455c89494STim Huang gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
28555c89494STim Huang
28655c89494STim Huang memcpy(&gpu_metrics->current_coreclk[0],
28755c89494STim Huang &metrics.CoreFrequency[0],
28855c89494STim Huang sizeof(uint16_t) * 8);
28955c89494STim Huang gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
29055c89494STim Huang
29155c89494STim Huang gpu_metrics->throttle_status = metrics.ThrottlerStatus;
29255c89494STim Huang
29355c89494STim Huang gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
29455c89494STim Huang
29555c89494STim Huang *table = (void *)gpu_metrics;
29655c89494STim Huang
29755c89494STim Huang return sizeof(struct gpu_metrics_v2_1);
29855c89494STim Huang }
29955c89494STim Huang
smu_v13_0_4_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)30055c89494STim Huang static int smu_v13_0_4_get_smu_metrics_data(struct smu_context *smu,
30155c89494STim Huang MetricsMember_t member,
30255c89494STim Huang uint32_t *value)
30355c89494STim Huang {
30455c89494STim Huang struct smu_table_context *smu_table = &smu->smu_table;
30555c89494STim Huang
30655c89494STim Huang SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
30755c89494STim Huang int ret = 0;
30855c89494STim Huang
30955c89494STim Huang ret = smu_cmn_get_metrics_table(smu, NULL, false);
31055c89494STim Huang if (ret)
31155c89494STim Huang return ret;
31255c89494STim Huang
31355c89494STim Huang switch (member) {
31455c89494STim Huang case METRICS_AVERAGE_GFXCLK:
31555c89494STim Huang *value = metrics->GfxclkFrequency;
31655c89494STim Huang break;
31755c89494STim Huang case METRICS_AVERAGE_SOCCLK:
31855c89494STim Huang *value = metrics->SocclkFrequency;
31955c89494STim Huang break;
32055c89494STim Huang case METRICS_AVERAGE_VCLK:
32155c89494STim Huang *value = metrics->VclkFrequency;
32255c89494STim Huang break;
32355c89494STim Huang case METRICS_AVERAGE_DCLK:
32455c89494STim Huang *value = metrics->DclkFrequency;
32555c89494STim Huang break;
32655c89494STim Huang case METRICS_AVERAGE_UCLK:
32755c89494STim Huang *value = metrics->MemclkFrequency;
32855c89494STim Huang break;
32955c89494STim Huang case METRICS_AVERAGE_GFXACTIVITY:
33055c89494STim Huang *value = metrics->GfxActivity / 100;
33155c89494STim Huang break;
33255c89494STim Huang case METRICS_AVERAGE_VCNACTIVITY:
33355c89494STim Huang *value = metrics->UvdActivity;
33455c89494STim Huang break;
33555c89494STim Huang case METRICS_AVERAGE_SOCKETPOWER:
33647f1724dSMario Limonciello *value = (metrics->AverageSocketPower << 8) / 1000;
33747f1724dSMario Limonciello break;
33847f1724dSMario Limonciello case METRICS_CURR_SOCKETPOWER:
33955c89494STim Huang *value = (metrics->CurrentSocketPower << 8) / 1000;
34055c89494STim Huang break;
34155c89494STim Huang case METRICS_TEMPERATURE_EDGE:
34255c89494STim Huang *value = metrics->GfxTemperature / 100 *
34355c89494STim Huang SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
34455c89494STim Huang break;
34555c89494STim Huang case METRICS_TEMPERATURE_HOTSPOT:
34655c89494STim Huang *value = metrics->SocTemperature / 100 *
34755c89494STim Huang SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
34855c89494STim Huang break;
34955c89494STim Huang case METRICS_THROTTLER_STATUS:
35055c89494STim Huang *value = metrics->ThrottlerStatus;
35155c89494STim Huang break;
35255c89494STim Huang case METRICS_VOLTAGE_VDDGFX:
35355c89494STim Huang *value = metrics->Voltage[0];
35455c89494STim Huang break;
35555c89494STim Huang case METRICS_VOLTAGE_VDDSOC:
35655c89494STim Huang *value = metrics->Voltage[1];
35755c89494STim Huang break;
35855c89494STim Huang case METRICS_SS_APU_SHARE:
35955c89494STim Huang /* return the percentage of APU power with respect to APU's power limit.
36055c89494STim Huang * percentage is reported, this isn't boost value. Smartshift power
36155c89494STim Huang * boost/shift is only when the percentage is more than 100.
36255c89494STim Huang */
36355c89494STim Huang if (metrics->StapmOpnLimit > 0)
36455c89494STim Huang *value = (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
36555c89494STim Huang else
36655c89494STim Huang *value = 0;
36755c89494STim Huang break;
36855c89494STim Huang case METRICS_SS_DGPU_SHARE:
36955c89494STim Huang /* return the percentage of dGPU power with respect to dGPU's power limit.
37055c89494STim Huang * percentage is reported, this isn't boost value. Smartshift power
37155c89494STim Huang * boost/shift is only when the percentage is more than 100.
37255c89494STim Huang */
37355c89494STim Huang if ((metrics->dGpuPower > 0) &&
37455c89494STim Huang (metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
37555c89494STim Huang *value = (metrics->dGpuPower * 100) /
37655c89494STim Huang (metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
37755c89494STim Huang else
37855c89494STim Huang *value = 0;
37955c89494STim Huang break;
38055c89494STim Huang default:
38155c89494STim Huang *value = UINT_MAX;
38255c89494STim Huang break;
38355c89494STim Huang }
38455c89494STim Huang
38555c89494STim Huang return ret;
38655c89494STim Huang }
38755c89494STim Huang
smu_v13_0_4_get_current_clk_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)38855c89494STim Huang static int smu_v13_0_4_get_current_clk_freq(struct smu_context *smu,
38955c89494STim Huang enum smu_clk_type clk_type,
39055c89494STim Huang uint32_t *value)
39155c89494STim Huang {
39255c89494STim Huang MetricsMember_t member_type;
39355c89494STim Huang
39455c89494STim Huang switch (clk_type) {
39555c89494STim Huang case SMU_SOCCLK:
39655c89494STim Huang member_type = METRICS_AVERAGE_SOCCLK;
39755c89494STim Huang break;
39855c89494STim Huang case SMU_VCLK:
39955c89494STim Huang member_type = METRICS_AVERAGE_VCLK;
40055c89494STim Huang break;
40155c89494STim Huang case SMU_DCLK:
40255c89494STim Huang member_type = METRICS_AVERAGE_DCLK;
40355c89494STim Huang break;
40455c89494STim Huang case SMU_MCLK:
40555c89494STim Huang member_type = METRICS_AVERAGE_UCLK;
40655c89494STim Huang break;
40755c89494STim Huang case SMU_FCLK:
40855c89494STim Huang return smu_cmn_send_smc_msg_with_param(smu,
40955c89494STim Huang SMU_MSG_GetFclkFrequency,
41055c89494STim Huang 0, value);
41155c89494STim Huang case SMU_GFXCLK:
41255c89494STim Huang case SMU_SCLK:
41355c89494STim Huang return smu_cmn_send_smc_msg_with_param(smu,
41455c89494STim Huang SMU_MSG_GetGfxclkFrequency,
41555c89494STim Huang 0, value);
41655c89494STim Huang break;
41755c89494STim Huang default:
41855c89494STim Huang return -EINVAL;
41955c89494STim Huang }
42055c89494STim Huang
42155c89494STim Huang return smu_v13_0_4_get_smu_metrics_data(smu, member_type, value);
42255c89494STim Huang }
42355c89494STim Huang
smu_v13_0_4_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)42455c89494STim Huang static int smu_v13_0_4_get_dpm_freq_by_index(struct smu_context *smu,
42555c89494STim Huang enum smu_clk_type clk_type,
42655c89494STim Huang uint32_t dpm_level,
42755c89494STim Huang uint32_t *freq)
42855c89494STim Huang {
42955c89494STim Huang DpmClocks_t *clk_table = smu->smu_table.clocks_table;
43055c89494STim Huang
43155c89494STim Huang if (!clk_table || clk_type >= SMU_CLK_COUNT)
43255c89494STim Huang return -EINVAL;
43355c89494STim Huang
43455c89494STim Huang switch (clk_type) {
43555c89494STim Huang case SMU_SOCCLK:
43655c89494STim Huang if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
43755c89494STim Huang return -EINVAL;
43855c89494STim Huang *freq = clk_table->SocClocks[dpm_level];
43955c89494STim Huang break;
44055c89494STim Huang case SMU_VCLK:
44155c89494STim Huang if (dpm_level >= clk_table->VcnClkLevelsEnabled)
44255c89494STim Huang return -EINVAL;
44355c89494STim Huang *freq = clk_table->VClocks[dpm_level];
44455c89494STim Huang break;
44555c89494STim Huang case SMU_DCLK:
44655c89494STim Huang if (dpm_level >= clk_table->VcnClkLevelsEnabled)
44755c89494STim Huang return -EINVAL;
44855c89494STim Huang *freq = clk_table->DClocks[dpm_level];
44955c89494STim Huang break;
45055c89494STim Huang case SMU_UCLK:
45155c89494STim Huang case SMU_MCLK:
45255c89494STim Huang if (dpm_level >= clk_table->NumDfPstatesEnabled)
45355c89494STim Huang return -EINVAL;
45455c89494STim Huang *freq = clk_table->DfPstateTable[dpm_level].MemClk;
45555c89494STim Huang break;
45655c89494STim Huang case SMU_FCLK:
45755c89494STim Huang if (dpm_level >= clk_table->NumDfPstatesEnabled)
45855c89494STim Huang return -EINVAL;
45955c89494STim Huang *freq = clk_table->DfPstateTable[dpm_level].FClk;
46055c89494STim Huang break;
46155c89494STim Huang default:
46255c89494STim Huang return -EINVAL;
46355c89494STim Huang }
46455c89494STim Huang
46555c89494STim Huang return 0;
46655c89494STim Huang }
46755c89494STim Huang
smu_v13_0_4_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * count)46855c89494STim Huang static int smu_v13_0_4_get_dpm_level_count(struct smu_context *smu,
46955c89494STim Huang enum smu_clk_type clk_type,
47055c89494STim Huang uint32_t *count)
47155c89494STim Huang {
47255c89494STim Huang DpmClocks_t *clk_table = smu->smu_table.clocks_table;
47355c89494STim Huang
47455c89494STim Huang switch (clk_type) {
47555c89494STim Huang case SMU_SOCCLK:
47655c89494STim Huang *count = clk_table->NumSocClkLevelsEnabled;
47755c89494STim Huang break;
47855c89494STim Huang case SMU_VCLK:
47955c89494STim Huang *count = clk_table->VcnClkLevelsEnabled;
48055c89494STim Huang break;
48155c89494STim Huang case SMU_DCLK:
48255c89494STim Huang *count = clk_table->VcnClkLevelsEnabled;
48355c89494STim Huang break;
48455c89494STim Huang case SMU_MCLK:
48555c89494STim Huang *count = clk_table->NumDfPstatesEnabled;
48655c89494STim Huang break;
48755c89494STim Huang case SMU_FCLK:
48855c89494STim Huang *count = clk_table->NumDfPstatesEnabled;
48955c89494STim Huang break;
49055c89494STim Huang default:
49155c89494STim Huang break;
49255c89494STim Huang }
49355c89494STim Huang
49455c89494STim Huang return 0;
49555c89494STim Huang }
49655c89494STim Huang
smu_v13_0_4_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)49755c89494STim Huang static int smu_v13_0_4_print_clk_levels(struct smu_context *smu,
49855c89494STim Huang enum smu_clk_type clk_type, char *buf)
49955c89494STim Huang {
500665d49c2STim Huang int i, idx, size = 0, ret = 0;
50155c89494STim Huang uint32_t cur_value = 0, value = 0, count = 0;
50255c89494STim Huang uint32_t min, max;
50355c89494STim Huang
50455c89494STim Huang smu_cmn_get_sysfs_buf(&buf, &size);
50555c89494STim Huang
50655c89494STim Huang switch (clk_type) {
50755c89494STim Huang case SMU_OD_SCLK:
50855c89494STim Huang size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
50955c89494STim Huang size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
51055c89494STim Huang (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
51155c89494STim Huang size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
51255c89494STim Huang (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
51355c89494STim Huang break;
51455c89494STim Huang case SMU_OD_RANGE:
51555c89494STim Huang size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
51655c89494STim Huang size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
51755c89494STim Huang smu->gfx_default_hard_min_freq,
51855c89494STim Huang smu->gfx_default_soft_max_freq);
51955c89494STim Huang break;
52055c89494STim Huang case SMU_SOCCLK:
52155c89494STim Huang case SMU_VCLK:
52255c89494STim Huang case SMU_DCLK:
52355c89494STim Huang case SMU_MCLK:
52455c89494STim Huang case SMU_FCLK:
52555c89494STim Huang ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
52655c89494STim Huang if (ret)
52755c89494STim Huang break;
52855c89494STim Huang
52955c89494STim Huang ret = smu_v13_0_4_get_dpm_level_count(smu, clk_type, &count);
53055c89494STim Huang if (ret)
53155c89494STim Huang break;
53255c89494STim Huang
53355c89494STim Huang for (i = 0; i < count; i++) {
534665d49c2STim Huang idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
535665d49c2STim Huang ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, idx, &value);
53655c89494STim Huang if (ret)
53755c89494STim Huang break;
53855c89494STim Huang
53955c89494STim Huang size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
54055c89494STim Huang cur_value == value ? "*" : "");
54155c89494STim Huang }
54255c89494STim Huang break;
54355c89494STim Huang case SMU_GFXCLK:
54455c89494STim Huang case SMU_SCLK:
54555c89494STim Huang ret = smu_v13_0_4_get_current_clk_freq(smu, clk_type, &cur_value);
54655c89494STim Huang if (ret)
54755c89494STim Huang break;
54855c89494STim Huang min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
54955c89494STim Huang max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
55055c89494STim Huang if (cur_value == max)
55155c89494STim Huang i = 2;
55255c89494STim Huang else if (cur_value == min)
55355c89494STim Huang i = 0;
55455c89494STim Huang else
55555c89494STim Huang i = 1;
55655c89494STim Huang size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
55755c89494STim Huang i == 0 ? "*" : "");
55855c89494STim Huang size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
55955c89494STim Huang i == 1 ? cur_value : 1100, /* UMD PSTATE GFXCLK 1100 */
56055c89494STim Huang i == 1 ? "*" : "");
56155c89494STim Huang size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
56255c89494STim Huang i == 2 ? "*" : "");
56355c89494STim Huang break;
56455c89494STim Huang default:
56555c89494STim Huang break;
56655c89494STim Huang }
56755c89494STim Huang
56855c89494STim Huang return size;
56955c89494STim Huang }
57055c89494STim Huang
smu_v13_0_4_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)57155c89494STim Huang static int smu_v13_0_4_read_sensor(struct smu_context *smu,
57255c89494STim Huang enum amd_pp_sensors sensor,
57355c89494STim Huang void *data, uint32_t *size)
57455c89494STim Huang {
57555c89494STim Huang int ret = 0;
57655c89494STim Huang
57755c89494STim Huang if (!data || !size)
57855c89494STim Huang return -EINVAL;
57955c89494STim Huang
58055c89494STim Huang switch (sensor) {
58155c89494STim Huang case AMDGPU_PP_SENSOR_GPU_LOAD:
58255c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
58355c89494STim Huang METRICS_AVERAGE_GFXACTIVITY,
58455c89494STim Huang (uint32_t *)data);
58555c89494STim Huang *size = 4;
58655c89494STim Huang break;
5879366c2e8SMario Limonciello case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
58855c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
58955c89494STim Huang METRICS_AVERAGE_SOCKETPOWER,
59055c89494STim Huang (uint32_t *)data);
59155c89494STim Huang *size = 4;
59255c89494STim Huang break;
59347f1724dSMario Limonciello case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
59447f1724dSMario Limonciello ret = smu_v13_0_4_get_smu_metrics_data(smu,
59547f1724dSMario Limonciello METRICS_CURR_SOCKETPOWER,
59647f1724dSMario Limonciello (uint32_t *)data);
59747f1724dSMario Limonciello *size = 4;
59847f1724dSMario Limonciello break;
59955c89494STim Huang case AMDGPU_PP_SENSOR_EDGE_TEMP:
60055c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
60155c89494STim Huang METRICS_TEMPERATURE_EDGE,
60255c89494STim Huang (uint32_t *)data);
60355c89494STim Huang *size = 4;
60455c89494STim Huang break;
60555c89494STim Huang case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
60655c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
60755c89494STim Huang METRICS_TEMPERATURE_HOTSPOT,
60855c89494STim Huang (uint32_t *)data);
60955c89494STim Huang *size = 4;
61055c89494STim Huang break;
61155c89494STim Huang case AMDGPU_PP_SENSOR_GFX_MCLK:
61255c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
61355c89494STim Huang METRICS_AVERAGE_UCLK,
61455c89494STim Huang (uint32_t *)data);
61555c89494STim Huang *(uint32_t *)data *= 100;
61655c89494STim Huang *size = 4;
61755c89494STim Huang break;
61855c89494STim Huang case AMDGPU_PP_SENSOR_GFX_SCLK:
61955c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
62055c89494STim Huang METRICS_AVERAGE_GFXCLK,
62155c89494STim Huang (uint32_t *)data);
62255c89494STim Huang *(uint32_t *)data *= 100;
62355c89494STim Huang *size = 4;
62455c89494STim Huang break;
62555c89494STim Huang case AMDGPU_PP_SENSOR_VDDGFX:
62655c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
62755c89494STim Huang METRICS_VOLTAGE_VDDGFX,
62855c89494STim Huang (uint32_t *)data);
62955c89494STim Huang *size = 4;
63055c89494STim Huang break;
63155c89494STim Huang case AMDGPU_PP_SENSOR_VDDNB:
63255c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
63355c89494STim Huang METRICS_VOLTAGE_VDDSOC,
63455c89494STim Huang (uint32_t *)data);
63555c89494STim Huang *size = 4;
63655c89494STim Huang break;
63755c89494STim Huang case AMDGPU_PP_SENSOR_SS_APU_SHARE:
63855c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
63955c89494STim Huang METRICS_SS_APU_SHARE,
64055c89494STim Huang (uint32_t *)data);
64155c89494STim Huang *size = 4;
64255c89494STim Huang break;
64355c89494STim Huang case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
64455c89494STim Huang ret = smu_v13_0_4_get_smu_metrics_data(smu,
64555c89494STim Huang METRICS_SS_DGPU_SHARE,
64655c89494STim Huang (uint32_t *)data);
64755c89494STim Huang *size = 4;
64855c89494STim Huang break;
64955c89494STim Huang default:
65055c89494STim Huang ret = -EOPNOTSUPP;
65155c89494STim Huang break;
65255c89494STim Huang }
65355c89494STim Huang
65455c89494STim Huang return ret;
65555c89494STim Huang }
65655c89494STim Huang
smu_v13_0_4_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)65755c89494STim Huang static int smu_v13_0_4_set_watermarks_table(struct smu_context *smu,
65855c89494STim Huang struct pp_smu_wm_range_sets *clock_ranges)
65955c89494STim Huang {
66055c89494STim Huang int i;
66155c89494STim Huang int ret = 0;
66255c89494STim Huang Watermarks_t *table = smu->smu_table.watermarks_table;
66355c89494STim Huang
66455c89494STim Huang if (!table || !clock_ranges)
66555c89494STim Huang return -EINVAL;
66655c89494STim Huang
66755c89494STim Huang if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
66855c89494STim Huang clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
66955c89494STim Huang return -EINVAL;
67055c89494STim Huang
67155c89494STim Huang for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
67255c89494STim Huang table->WatermarkRow[WM_DCFCLK][i].MinClock =
67355c89494STim Huang clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
67455c89494STim Huang table->WatermarkRow[WM_DCFCLK][i].MaxClock =
67555c89494STim Huang clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
67655c89494STim Huang table->WatermarkRow[WM_DCFCLK][i].MinMclk =
67755c89494STim Huang clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
67855c89494STim Huang table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
67955c89494STim Huang clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
68055c89494STim Huang
68155c89494STim Huang table->WatermarkRow[WM_DCFCLK][i].WmSetting =
68255c89494STim Huang clock_ranges->reader_wm_sets[i].wm_inst;
68355c89494STim Huang }
68455c89494STim Huang
68555c89494STim Huang for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
68655c89494STim Huang table->WatermarkRow[WM_SOCCLK][i].MinClock =
68755c89494STim Huang clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
68855c89494STim Huang table->WatermarkRow[WM_SOCCLK][i].MaxClock =
68955c89494STim Huang clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
69055c89494STim Huang table->WatermarkRow[WM_SOCCLK][i].MinMclk =
69155c89494STim Huang clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
69255c89494STim Huang table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
69355c89494STim Huang clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
69455c89494STim Huang
69555c89494STim Huang table->WatermarkRow[WM_SOCCLK][i].WmSetting =
69655c89494STim Huang clock_ranges->writer_wm_sets[i].wm_inst;
69755c89494STim Huang }
69855c89494STim Huang
69955c89494STim Huang smu->watermarks_bitmap |= WATERMARKS_EXIST;
70055c89494STim Huang
70155c89494STim Huang /* pass data to smu controller */
70255c89494STim Huang if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
70355c89494STim Huang !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
70455c89494STim Huang ret = smu_cmn_write_watermarks_table(smu);
70555c89494STim Huang if (ret) {
70655c89494STim Huang dev_err(smu->adev->dev, "Failed to update WMTABLE!");
70755c89494STim Huang return ret;
70855c89494STim Huang }
70955c89494STim Huang smu->watermarks_bitmap |= WATERMARKS_LOADED;
71055c89494STim Huang }
71155c89494STim Huang
71255c89494STim Huang return 0;
71355c89494STim Huang }
71455c89494STim Huang
smu_v13_0_4_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)71555c89494STim Huang static bool smu_v13_0_4_clk_dpm_is_enabled(struct smu_context *smu,
71655c89494STim Huang enum smu_clk_type clk_type)
71755c89494STim Huang {
71855c89494STim Huang enum smu_feature_mask feature_id = 0;
71955c89494STim Huang
72055c89494STim Huang switch (clk_type) {
72155c89494STim Huang case SMU_MCLK:
72255c89494STim Huang case SMU_UCLK:
72355c89494STim Huang case SMU_FCLK:
72455c89494STim Huang feature_id = SMU_FEATURE_DPM_FCLK_BIT;
72555c89494STim Huang break;
72655c89494STim Huang case SMU_GFXCLK:
72755c89494STim Huang case SMU_SCLK:
72855c89494STim Huang feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
72955c89494STim Huang break;
73055c89494STim Huang case SMU_SOCCLK:
73155c89494STim Huang feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
73255c89494STim Huang break;
73355c89494STim Huang case SMU_VCLK:
73455c89494STim Huang case SMU_DCLK:
73555c89494STim Huang feature_id = SMU_FEATURE_VCN_DPM_BIT;
73655c89494STim Huang break;
73755c89494STim Huang default:
73855c89494STim Huang return true;
73955c89494STim Huang }
74055c89494STim Huang
74155c89494STim Huang return smu_cmn_feature_is_enabled(smu, feature_id);
74255c89494STim Huang }
74355c89494STim Huang
smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)74455c89494STim Huang static int smu_v13_0_4_get_dpm_ultimate_freq(struct smu_context *smu,
74555c89494STim Huang enum smu_clk_type clk_type,
74655c89494STim Huang uint32_t *min,
74755c89494STim Huang uint32_t *max)
74855c89494STim Huang {
74955c89494STim Huang DpmClocks_t *clk_table = smu->smu_table.clocks_table;
75055c89494STim Huang uint32_t clock_limit;
75155c89494STim Huang uint32_t max_dpm_level, min_dpm_level;
75255c89494STim Huang int ret = 0;
75355c89494STim Huang
75455c89494STim Huang if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type)) {
75555c89494STim Huang switch (clk_type) {
75655c89494STim Huang case SMU_MCLK:
75755c89494STim Huang case SMU_UCLK:
75855c89494STim Huang clock_limit = smu->smu_table.boot_values.uclk;
75955c89494STim Huang break;
76055c89494STim Huang case SMU_FCLK:
76155c89494STim Huang clock_limit = smu->smu_table.boot_values.fclk;
76255c89494STim Huang break;
76355c89494STim Huang case SMU_GFXCLK:
76455c89494STim Huang case SMU_SCLK:
76555c89494STim Huang clock_limit = smu->smu_table.boot_values.gfxclk;
76655c89494STim Huang break;
76755c89494STim Huang case SMU_SOCCLK:
76855c89494STim Huang clock_limit = smu->smu_table.boot_values.socclk;
76955c89494STim Huang break;
77055c89494STim Huang case SMU_VCLK:
77155c89494STim Huang clock_limit = smu->smu_table.boot_values.vclk;
77255c89494STim Huang break;
77355c89494STim Huang case SMU_DCLK:
77455c89494STim Huang clock_limit = smu->smu_table.boot_values.dclk;
77555c89494STim Huang break;
77655c89494STim Huang default:
77755c89494STim Huang clock_limit = 0;
77855c89494STim Huang break;
77955c89494STim Huang }
78055c89494STim Huang
78155c89494STim Huang /* clock in Mhz unit */
78255c89494STim Huang if (min)
78355c89494STim Huang *min = clock_limit / 100;
78455c89494STim Huang if (max)
78555c89494STim Huang *max = clock_limit / 100;
78655c89494STim Huang
78755c89494STim Huang return 0;
78855c89494STim Huang }
78955c89494STim Huang
79055c89494STim Huang if (max) {
79155c89494STim Huang switch (clk_type) {
79255c89494STim Huang case SMU_GFXCLK:
79355c89494STim Huang case SMU_SCLK:
79455c89494STim Huang *max = clk_table->MaxGfxClk;
79555c89494STim Huang break;
79655c89494STim Huang case SMU_MCLK:
79755c89494STim Huang case SMU_UCLK:
79855c89494STim Huang case SMU_FCLK:
79955c89494STim Huang max_dpm_level = 0;
80055c89494STim Huang break;
80155c89494STim Huang case SMU_SOCCLK:
80255c89494STim Huang max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
80355c89494STim Huang break;
80455c89494STim Huang case SMU_VCLK:
80555c89494STim Huang case SMU_DCLK:
80655c89494STim Huang max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
80755c89494STim Huang break;
80855c89494STim Huang default:
80955c89494STim Huang return -EINVAL;
81055c89494STim Huang }
81155c89494STim Huang
81255c89494STim Huang if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
81355c89494STim Huang ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
81455c89494STim Huang max_dpm_level,
81555c89494STim Huang max);
81655c89494STim Huang if (ret)
81755c89494STim Huang return ret;
81855c89494STim Huang }
81955c89494STim Huang }
82055c89494STim Huang
82155c89494STim Huang if (min) {
82255c89494STim Huang switch (clk_type) {
82355c89494STim Huang case SMU_GFXCLK:
82455c89494STim Huang case SMU_SCLK:
82555c89494STim Huang *min = clk_table->MinGfxClk;
82655c89494STim Huang break;
82755c89494STim Huang case SMU_MCLK:
82855c89494STim Huang case SMU_UCLK:
82955c89494STim Huang case SMU_FCLK:
83055c89494STim Huang min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
83155c89494STim Huang break;
83255c89494STim Huang case SMU_SOCCLK:
83355c89494STim Huang min_dpm_level = 0;
83455c89494STim Huang break;
83555c89494STim Huang case SMU_VCLK:
83655c89494STim Huang case SMU_DCLK:
83755c89494STim Huang min_dpm_level = 0;
83855c89494STim Huang break;
83955c89494STim Huang default:
84055c89494STim Huang return -EINVAL;
84155c89494STim Huang }
84255c89494STim Huang
84355c89494STim Huang if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
84455c89494STim Huang ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type,
84555c89494STim Huang min_dpm_level,
84655c89494STim Huang min);
84755c89494STim Huang }
84855c89494STim Huang }
84955c89494STim Huang
85055c89494STim Huang return ret;
85155c89494STim Huang }
85255c89494STim Huang
smu_v13_0_4_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)85355c89494STim Huang static int smu_v13_0_4_set_soft_freq_limited_range(struct smu_context *smu,
85455c89494STim Huang enum smu_clk_type clk_type,
85555c89494STim Huang uint32_t min,
85655c89494STim Huang uint32_t max)
85755c89494STim Huang {
85855c89494STim Huang enum smu_message_type msg_set_min, msg_set_max;
85927d196c4STim Huang uint32_t min_clk = min;
86027d196c4STim Huang uint32_t max_clk = max;
86155c89494STim Huang int ret = 0;
86255c89494STim Huang
86355c89494STim Huang if (!smu_v13_0_4_clk_dpm_is_enabled(smu, clk_type))
86455c89494STim Huang return -EINVAL;
86555c89494STim Huang
86655c89494STim Huang switch (clk_type) {
86755c89494STim Huang case SMU_GFXCLK:
86855c89494STim Huang case SMU_SCLK:
86955c89494STim Huang msg_set_min = SMU_MSG_SetHardMinGfxClk;
87055c89494STim Huang msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
87155c89494STim Huang break;
87255c89494STim Huang case SMU_FCLK:
87355c89494STim Huang msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
87455c89494STim Huang msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
87555c89494STim Huang break;
87655c89494STim Huang case SMU_SOCCLK:
87755c89494STim Huang msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
87855c89494STim Huang msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
87955c89494STim Huang break;
88055c89494STim Huang case SMU_VCLK:
88155c89494STim Huang case SMU_DCLK:
88255c89494STim Huang msg_set_min = SMU_MSG_SetHardMinVcn;
88355c89494STim Huang msg_set_max = SMU_MSG_SetSoftMaxVcn;
88455c89494STim Huang break;
88555c89494STim Huang default:
88655c89494STim Huang return -EINVAL;
88755c89494STim Huang }
88855c89494STim Huang
88927d196c4STim Huang if (clk_type == SMU_VCLK) {
89027d196c4STim Huang min_clk = min << SMU_13_VCLK_SHIFT;
89127d196c4STim Huang max_clk = max << SMU_13_VCLK_SHIFT;
89227d196c4STim Huang }
89327d196c4STim Huang
89427d196c4STim Huang ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min_clk, NULL);
89555c89494STim Huang if (ret)
89655c89494STim Huang return ret;
89755c89494STim Huang
89855c89494STim Huang return smu_cmn_send_smc_msg_with_param(smu, msg_set_max,
89927d196c4STim Huang max_clk, NULL);
90055c89494STim Huang }
90155c89494STim Huang
smu_v13_0_4_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)90255c89494STim Huang static int smu_v13_0_4_force_clk_levels(struct smu_context *smu,
90355c89494STim Huang enum smu_clk_type clk_type,
90455c89494STim Huang uint32_t mask)
90555c89494STim Huang {
90655c89494STim Huang uint32_t soft_min_level = 0, soft_max_level = 0;
90755c89494STim Huang uint32_t min_freq = 0, max_freq = 0;
90855c89494STim Huang int ret = 0;
90955c89494STim Huang
91055c89494STim Huang soft_min_level = mask ? (ffs(mask) - 1) : 0;
91155c89494STim Huang soft_max_level = mask ? (fls(mask) - 1) : 0;
91255c89494STim Huang
91355c89494STim Huang switch (clk_type) {
91455c89494STim Huang case SMU_SOCCLK:
91555c89494STim Huang case SMU_FCLK:
91655c89494STim Huang case SMU_VCLK:
91755c89494STim Huang case SMU_DCLK:
91855c89494STim Huang ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
91955c89494STim Huang if (ret)
92055c89494STim Huang break;
92155c89494STim Huang
92255c89494STim Huang ret = smu_v13_0_4_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
92355c89494STim Huang if (ret)
92455c89494STim Huang break;
92555c89494STim Huang
92655c89494STim Huang ret = smu_v13_0_4_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
92755c89494STim Huang break;
92855c89494STim Huang default:
92955c89494STim Huang ret = -EINVAL;
93055c89494STim Huang break;
93155c89494STim Huang }
93255c89494STim Huang
93355c89494STim Huang return ret;
93455c89494STim Huang }
93555c89494STim Huang
smu_v13_0_4_get_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type,uint32_t * min_clk,uint32_t * max_clk)93655682a89STim Huang static int smu_v13_0_4_get_dpm_profile_freq(struct smu_context *smu,
93755682a89STim Huang enum amd_dpm_forced_level level,
93855682a89STim Huang enum smu_clk_type clk_type,
93955682a89STim Huang uint32_t *min_clk,
94055682a89STim Huang uint32_t *max_clk)
94155682a89STim Huang {
94255682a89STim Huang int ret = 0;
94355682a89STim Huang uint32_t clk_limit = 0;
94455682a89STim Huang
94555682a89STim Huang switch (clk_type) {
94655682a89STim Huang case SMU_GFXCLK:
94755682a89STim Huang case SMU_SCLK:
94855682a89STim Huang clk_limit = SMU_13_0_4_UMD_PSTATE_GFXCLK;
94955682a89STim Huang if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
95055682a89STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);
95155682a89STim Huang else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
95255682a89STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);
95355682a89STim Huang break;
95455682a89STim Huang case SMU_SOCCLK:
95555682a89STim Huang clk_limit = SMU_13_0_4_UMD_PSTATE_SOCCLK;
95655682a89STim Huang if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
95755682a89STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &clk_limit);
95855682a89STim Huang break;
95955682a89STim Huang case SMU_FCLK:
96055682a89STim Huang clk_limit = SMU_13_0_4_UMD_PSTATE_FCLK;
96155682a89STim Huang if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
96255682a89STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &clk_limit);
96355682a89STim Huang else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
96455682a89STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &clk_limit, NULL);
96555682a89STim Huang break;
96655682a89STim Huang case SMU_VCLK:
96755682a89STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);
96855682a89STim Huang break;
96955682a89STim Huang case SMU_DCLK:
97055682a89STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);
97155682a89STim Huang break;
97255682a89STim Huang default:
97355682a89STim Huang ret = -EINVAL;
97455682a89STim Huang break;
97555682a89STim Huang }
97655682a89STim Huang *min_clk = *max_clk = clk_limit;
97755682a89STim Huang return ret;
97855682a89STim Huang }
97955682a89STim Huang
smu_v13_0_4_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)98055c89494STim Huang static int smu_v13_0_4_set_performance_level(struct smu_context *smu,
98155c89494STim Huang enum amd_dpm_forced_level level)
98255c89494STim Huang {
98355c89494STim Huang struct amdgpu_device *adev = smu->adev;
98455c89494STim Huang uint32_t sclk_min = 0, sclk_max = 0;
98555c89494STim Huang uint32_t fclk_min = 0, fclk_max = 0;
98655c89494STim Huang uint32_t socclk_min = 0, socclk_max = 0;
9872d0ee64eSTim Huang uint32_t vclk_min = 0, vclk_max = 0;
9882d0ee64eSTim Huang uint32_t dclk_min = 0, dclk_max = 0;
98955c89494STim Huang int ret = 0;
99055c89494STim Huang
99155c89494STim Huang switch (level) {
99255c89494STim Huang case AMD_DPM_FORCED_LEVEL_HIGH:
99355c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
99455c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
99555c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
9962d0ee64eSTim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_max);
9972d0ee64eSTim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_max);
99855c89494STim Huang sclk_min = sclk_max;
99955c89494STim Huang fclk_min = fclk_max;
100055c89494STim Huang socclk_min = socclk_max;
10012d0ee64eSTim Huang vclk_min = vclk_max;
10022d0ee64eSTim Huang dclk_min = dclk_max;
100355c89494STim Huang break;
100455c89494STim Huang case AMD_DPM_FORCED_LEVEL_LOW:
100555c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
100655c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
100755c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
10082d0ee64eSTim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, NULL);
10092d0ee64eSTim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, NULL);
101055c89494STim Huang sclk_max = sclk_min;
101155c89494STim Huang fclk_max = fclk_min;
101255c89494STim Huang socclk_max = socclk_min;
10132d0ee64eSTim Huang vclk_max = vclk_min;
10142d0ee64eSTim Huang dclk_max = dclk_min;
101555c89494STim Huang break;
101655c89494STim Huang case AMD_DPM_FORCED_LEVEL_AUTO:
101755c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
101855c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
101955c89494STim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
10202d0ee64eSTim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_VCLK, &vclk_min, &vclk_max);
10212d0ee64eSTim Huang smu_v13_0_4_get_dpm_ultimate_freq(smu, SMU_DCLK, &dclk_min, &dclk_max);
102255c89494STim Huang break;
102355c89494STim Huang case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
102455c89494STim Huang case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
102555c89494STim Huang case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
102655c89494STim Huang case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
102755682a89STim Huang smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);
102855682a89STim Huang smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_FCLK, &fclk_min, &fclk_max);
102955682a89STim Huang smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_SOCCLK, &socclk_min, &socclk_max);
103055682a89STim Huang smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);
103155682a89STim Huang smu_v13_0_4_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);
103255c89494STim Huang break;
103355c89494STim Huang case AMD_DPM_FORCED_LEVEL_MANUAL:
103455c89494STim Huang case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
103555c89494STim Huang return 0;
103655c89494STim Huang default:
103755c89494STim Huang dev_err(adev->dev, "Invalid performance level %d\n", level);
103855c89494STim Huang return -EINVAL;
103955c89494STim Huang }
104055c89494STim Huang
104155c89494STim Huang if (sclk_min && sclk_max) {
104255c89494STim Huang ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
104355c89494STim Huang SMU_SCLK,
104455c89494STim Huang sclk_min,
104555c89494STim Huang sclk_max);
104655c89494STim Huang if (ret)
104755c89494STim Huang return ret;
104855c89494STim Huang
104955c89494STim Huang smu->gfx_actual_hard_min_freq = sclk_min;
105055c89494STim Huang smu->gfx_actual_soft_max_freq = sclk_max;
105155c89494STim Huang }
105255c89494STim Huang
105355c89494STim Huang if (fclk_min && fclk_max) {
105455c89494STim Huang ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
105555c89494STim Huang SMU_FCLK,
105655c89494STim Huang fclk_min,
105755c89494STim Huang fclk_max);
105855c89494STim Huang if (ret)
105955c89494STim Huang return ret;
106055c89494STim Huang }
106155c89494STim Huang
106255c89494STim Huang if (socclk_min && socclk_max) {
106355c89494STim Huang ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
106455c89494STim Huang SMU_SOCCLK,
106555c89494STim Huang socclk_min,
106655c89494STim Huang socclk_max);
106755c89494STim Huang if (ret)
106855c89494STim Huang return ret;
106955c89494STim Huang }
107055c89494STim Huang
10712d0ee64eSTim Huang if (vclk_min && vclk_max) {
10722d0ee64eSTim Huang ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
10732d0ee64eSTim Huang SMU_VCLK,
10742d0ee64eSTim Huang vclk_min,
10752d0ee64eSTim Huang vclk_max);
10762d0ee64eSTim Huang if (ret)
10772d0ee64eSTim Huang return ret;
10782d0ee64eSTim Huang }
10792d0ee64eSTim Huang
10802d0ee64eSTim Huang if (dclk_min && dclk_max) {
10812d0ee64eSTim Huang ret = smu_v13_0_4_set_soft_freq_limited_range(smu,
10822d0ee64eSTim Huang SMU_DCLK,
10832d0ee64eSTim Huang dclk_min,
10842d0ee64eSTim Huang dclk_max);
10852d0ee64eSTim Huang if (ret)
10862d0ee64eSTim Huang return ret;
10872d0ee64eSTim Huang }
108855c89494STim Huang return ret;
108955c89494STim Huang }
109055c89494STim Huang
smu_v13_0_4_mode2_reset(struct smu_context * smu)109155c89494STim Huang static int smu_v13_0_4_mode2_reset(struct smu_context *smu)
109255c89494STim Huang {
109355c89494STim Huang return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
109455c89494STim Huang SMU_RESET_MODE_2, NULL);
109555c89494STim Huang }
109655c89494STim Huang
smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)109755c89494STim Huang static int smu_v13_0_4_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
109855c89494STim Huang {
109955c89494STim Huang DpmClocks_t *clk_table = smu->smu_table.clocks_table;
110055c89494STim Huang
110155c89494STim Huang smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
110255c89494STim Huang smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
110355c89494STim Huang smu->gfx_actual_hard_min_freq = 0;
110455c89494STim Huang smu->gfx_actual_soft_max_freq = 0;
110555c89494STim Huang
110655c89494STim Huang return 0;
110755c89494STim Huang }
110855c89494STim Huang
110955c89494STim Huang static const struct pptable_funcs smu_v13_0_4_ppt_funcs = {
111055c89494STim Huang .check_fw_status = smu_v13_0_check_fw_status,
111155c89494STim Huang .check_fw_version = smu_v13_0_check_fw_version,
111255c89494STim Huang .init_smc_tables = smu_v13_0_4_init_smc_tables,
111355c89494STim Huang .fini_smc_tables = smu_v13_0_4_fini_smc_tables,
111455c89494STim Huang .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
111555c89494STim Huang .system_features_control = smu_v13_0_4_system_features_control,
111655c89494STim Huang .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
111755c89494STim Huang .send_smc_msg = smu_cmn_send_smc_msg,
111855c89494STim Huang .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
111955c89494STim Huang .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
112055c89494STim Huang .set_default_dpm_table = smu_v13_0_set_default_dpm_tables,
112155c89494STim Huang .read_sensor = smu_v13_0_4_read_sensor,
112255c89494STim Huang .is_dpm_running = smu_v13_0_4_is_dpm_running,
112355c89494STim Huang .set_watermarks_table = smu_v13_0_4_set_watermarks_table,
112455c89494STim Huang .get_gpu_metrics = smu_v13_0_4_get_gpu_metrics,
112555c89494STim Huang .get_enabled_mask = smu_cmn_get_enabled_mask,
112655c89494STim Huang .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
112755c89494STim Huang .set_driver_table_location = smu_v13_0_set_driver_table_location,
112855c89494STim Huang .gfx_off_control = smu_v13_0_gfx_off_control,
112955c89494STim Huang .mode2_reset = smu_v13_0_4_mode2_reset,
113055c89494STim Huang .get_dpm_ultimate_freq = smu_v13_0_4_get_dpm_ultimate_freq,
113155c89494STim Huang .od_edit_dpm_table = smu_v13_0_od_edit_dpm_table,
113255c89494STim Huang .print_clk_levels = smu_v13_0_4_print_clk_levels,
113355c89494STim Huang .force_clk_levels = smu_v13_0_4_force_clk_levels,
113455c89494STim Huang .set_performance_level = smu_v13_0_4_set_performance_level,
113555c89494STim Huang .set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters,
11367101ab97SHuang Rui .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu,
113755c89494STim Huang };
113855c89494STim Huang
smu_v13_0_4_set_smu_mailbox_registers(struct smu_context * smu)1139069a5af9STim Huang static void smu_v13_0_4_set_smu_mailbox_registers(struct smu_context *smu)
1140069a5af9STim Huang {
1141069a5af9STim Huang struct amdgpu_device *adev = smu->adev;
1142069a5af9STim Huang
1143069a5af9STim Huang smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1144069a5af9STim Huang smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1145069a5af9STim Huang smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
1146069a5af9STim Huang }
1147069a5af9STim Huang
smu_v13_0_4_set_ppt_funcs(struct smu_context * smu)114855c89494STim Huang void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)
114955c89494STim Huang {
1150da1db031SAlex Deucher struct amdgpu_device *adev = smu->adev;
1151da1db031SAlex Deucher
115255c89494STim Huang smu->ppt_funcs = &smu_v13_0_4_ppt_funcs;
115355c89494STim Huang smu->message_map = smu_v13_0_4_message_map;
115455c89494STim Huang smu->feature_map = smu_v13_0_4_feature_mask_map;
115555c89494STim Huang smu->table_map = smu_v13_0_4_table_map;
11569661bf68SLijo Lazar smu->smc_driver_if_version = SMU13_0_4_DRIVER_IF_VERSION;
115755c89494STim Huang smu->is_apu = true;
1158069a5af9STim Huang
1159069a5af9STim Huang if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 4))
1160069a5af9STim Huang smu_v13_0_4_set_smu_mailbox_registers(smu);
1161069a5af9STim Huang else
1162069a5af9STim Huang smu_v13_0_set_smu_mailbox_registers(smu);
116355c89494STim Huang }
1164