1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2019 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan *
22e098bc96SEvan Quan */
23e098bc96SEvan Quan
24e098bc96SEvan Quan #define SWSMU_CODE_LAYER_L2
25e098bc96SEvan Quan
26e098bc96SEvan Quan #include "amdgpu.h"
27e098bc96SEvan Quan #include "amdgpu_smu.h"
28e098bc96SEvan Quan #include "smu_v12_0_ppsmc.h"
29e098bc96SEvan Quan #include "smu12_driver_if.h"
30e098bc96SEvan Quan #include "smu_v12_0.h"
31e098bc96SEvan Quan #include "renoir_ppt.h"
32e098bc96SEvan Quan #include "smu_cmn.h"
33e098bc96SEvan Quan
34e098bc96SEvan Quan /*
35e098bc96SEvan Quan * DO NOT use these for err/warn/info/debug messages.
36e098bc96SEvan Quan * Use dev_err, dev_warn, dev_info and dev_dbg instead.
37e098bc96SEvan Quan * They are more MGPU friendly.
38e098bc96SEvan Quan */
39e098bc96SEvan Quan #undef pr_err
40e098bc96SEvan Quan #undef pr_warn
41e098bc96SEvan Quan #undef pr_info
42e098bc96SEvan Quan #undef pr_debug
43e098bc96SEvan Quan
44da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_66 0x0282
45da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
46da1db031SAlex Deucher
47da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_82 0x0292
48da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
49da1db031SAlex Deucher
50da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_90 0x029a
51da1db031SAlex Deucher #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
52da1db031SAlex Deucher
53e098bc96SEvan Quan static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
54e098bc96SEvan Quan MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
55e098bc96SEvan Quan MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
56e098bc96SEvan Quan MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
57e098bc96SEvan Quan MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1),
58e098bc96SEvan Quan MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
59e098bc96SEvan Quan MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
60e098bc96SEvan Quan MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
61e098bc96SEvan Quan MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
62e098bc96SEvan Quan MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
63e098bc96SEvan Quan MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
64e098bc96SEvan Quan MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1),
65e098bc96SEvan Quan MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1),
66e098bc96SEvan Quan MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1),
67e098bc96SEvan Quan MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
68e098bc96SEvan Quan MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1),
69e098bc96SEvan Quan MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
70e098bc96SEvan Quan MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
71e098bc96SEvan Quan MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1),
72e098bc96SEvan Quan MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1),
73e098bc96SEvan Quan MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1),
74e098bc96SEvan Quan MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1),
75e098bc96SEvan Quan MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
76e098bc96SEvan Quan MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
77e098bc96SEvan Quan MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
78e098bc96SEvan Quan MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
79e098bc96SEvan Quan MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
80e098bc96SEvan Quan MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1),
81e098bc96SEvan Quan MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1),
82e098bc96SEvan Quan MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
83e098bc96SEvan Quan MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1),
84e098bc96SEvan Quan MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
85e098bc96SEvan Quan MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1),
86e098bc96SEvan Quan MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1),
87e098bc96SEvan Quan MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1),
88e098bc96SEvan Quan MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1),
89e098bc96SEvan Quan MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
90e098bc96SEvan Quan MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
91e098bc96SEvan Quan MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
92e098bc96SEvan Quan MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
93e098bc96SEvan Quan MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1),
94e098bc96SEvan Quan MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1),
95e098bc96SEvan Quan MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1),
96e098bc96SEvan Quan MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1),
97e098bc96SEvan Quan MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
98e098bc96SEvan Quan MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
99e098bc96SEvan Quan MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
100e098bc96SEvan Quan MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
101e098bc96SEvan Quan MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
102e098bc96SEvan Quan MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1),
103e098bc96SEvan Quan MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1),
104e098bc96SEvan Quan MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
105e098bc96SEvan Quan MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
106e098bc96SEvan Quan MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1),
107e098bc96SEvan Quan MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
108e098bc96SEvan Quan MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
109e098bc96SEvan Quan MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
110e098bc96SEvan Quan MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1),
111e098bc96SEvan Quan MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1),
112e098bc96SEvan Quan MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
113e098bc96SEvan Quan };
114e098bc96SEvan Quan
115e098bc96SEvan Quan static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
116e098bc96SEvan Quan CLK_MAP(GFXCLK, CLOCK_GFXCLK),
117e098bc96SEvan Quan CLK_MAP(SCLK, CLOCK_GFXCLK),
118e098bc96SEvan Quan CLK_MAP(SOCCLK, CLOCK_SOCCLK),
119e098bc96SEvan Quan CLK_MAP(UCLK, CLOCK_FCLK),
120e098bc96SEvan Quan CLK_MAP(MCLK, CLOCK_FCLK),
12178842457SDavid M Nieto CLK_MAP(VCLK, CLOCK_VCLK),
12278842457SDavid M Nieto CLK_MAP(DCLK, CLOCK_DCLK),
123e098bc96SEvan Quan };
124e098bc96SEvan Quan
125e098bc96SEvan Quan static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
126e098bc96SEvan Quan TAB_MAP_VALID(WATERMARKS),
127e098bc96SEvan Quan TAB_MAP_INVALID(CUSTOM_DPM),
128e098bc96SEvan Quan TAB_MAP_VALID(DPMCLOCKS),
129e098bc96SEvan Quan TAB_MAP_VALID(SMU_METRICS),
130e098bc96SEvan Quan };
131e098bc96SEvan Quan
132e098bc96SEvan Quan static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
133e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
134e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
135e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
136e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
137e098bc96SEvan Quan WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
138e098bc96SEvan Quan };
139e098bc96SEvan Quan
140d4c9b03fSGraham Sider static const uint8_t renoir_throttler_map[] = {
141d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
142d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
143d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
144d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
145d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
146d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
147d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
148d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
149d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
150d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_PROCHOT_CPU] = (SMU_THROTTLER_PROCHOT_CPU_BIT),
151d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_PROCHOT_GFX] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
152d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_EDC_CPU] = (SMU_THROTTLER_EDC_CPU_BIT),
153d4c9b03fSGraham Sider [THROTTLER_STATUS_BIT_EDC_GFX] = (SMU_THROTTLER_EDC_GFX_BIT),
154d4c9b03fSGraham Sider };
155d4c9b03fSGraham Sider
renoir_init_smc_tables(struct smu_context * smu)156e098bc96SEvan Quan static int renoir_init_smc_tables(struct smu_context *smu)
157e098bc96SEvan Quan {
158e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table;
159e098bc96SEvan Quan struct smu_table *tables = smu_table->tables;
160e098bc96SEvan Quan
161e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
162e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
163e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
164e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
165e098bc96SEvan Quan SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
166e098bc96SEvan Quan PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
167e098bc96SEvan Quan
168e098bc96SEvan Quan smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
169e098bc96SEvan Quan if (!smu_table->clocks_table)
170e098bc96SEvan Quan goto err0_out;
171e098bc96SEvan Quan
172e098bc96SEvan Quan smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
173e098bc96SEvan Quan if (!smu_table->metrics_table)
174e098bc96SEvan Quan goto err1_out;
175e098bc96SEvan Quan smu_table->metrics_time = 0;
176e098bc96SEvan Quan
177e098bc96SEvan Quan smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
178e098bc96SEvan Quan if (!smu_table->watermarks_table)
179e098bc96SEvan Quan goto err2_out;
180e098bc96SEvan Quan
181d4c9b03fSGraham Sider smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
182e098bc96SEvan Quan smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
183e098bc96SEvan Quan if (!smu_table->gpu_metrics_table)
184e098bc96SEvan Quan goto err3_out;
185e098bc96SEvan Quan
186e098bc96SEvan Quan return 0;
187e098bc96SEvan Quan
188e098bc96SEvan Quan err3_out:
189e098bc96SEvan Quan kfree(smu_table->watermarks_table);
190e098bc96SEvan Quan err2_out:
191e098bc96SEvan Quan kfree(smu_table->metrics_table);
192e098bc96SEvan Quan err1_out:
193e098bc96SEvan Quan kfree(smu_table->clocks_table);
194e098bc96SEvan Quan err0_out:
195e098bc96SEvan Quan return -ENOMEM;
196e098bc96SEvan Quan }
197e098bc96SEvan Quan
198fecc72f1SLee Jones /*
199e098bc96SEvan Quan * This interface just for getting uclk ultimate freq and should't introduce
200e098bc96SEvan Quan * other likewise function result in overmuch callback.
201e098bc96SEvan Quan */
renoir_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)202e098bc96SEvan Quan static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
203e098bc96SEvan Quan uint32_t dpm_level, uint32_t *freq)
204e098bc96SEvan Quan {
205e098bc96SEvan Quan DpmClocks_t *clk_table = smu->smu_table.clocks_table;
206e098bc96SEvan Quan
207e098bc96SEvan Quan if (!clk_table || clk_type >= SMU_CLK_COUNT)
208e098bc96SEvan Quan return -EINVAL;
209e098bc96SEvan Quan
210e098bc96SEvan Quan switch (clk_type) {
211e098bc96SEvan Quan case SMU_SOCCLK:
212e098bc96SEvan Quan if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
213e098bc96SEvan Quan return -EINVAL;
214e098bc96SEvan Quan *freq = clk_table->SocClocks[dpm_level].Freq;
215e098bc96SEvan Quan break;
216d45af863SXiaojian Du case SMU_UCLK:
217e098bc96SEvan Quan case SMU_MCLK:
218e098bc96SEvan Quan if (dpm_level >= NUM_FCLK_DPM_LEVELS)
219e098bc96SEvan Quan return -EINVAL;
220e098bc96SEvan Quan *freq = clk_table->FClocks[dpm_level].Freq;
221e098bc96SEvan Quan break;
222e098bc96SEvan Quan case SMU_DCEFCLK:
223e098bc96SEvan Quan if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
224e098bc96SEvan Quan return -EINVAL;
225e098bc96SEvan Quan *freq = clk_table->DcfClocks[dpm_level].Freq;
226e098bc96SEvan Quan break;
227e098bc96SEvan Quan case SMU_FCLK:
228e098bc96SEvan Quan if (dpm_level >= NUM_FCLK_DPM_LEVELS)
229e098bc96SEvan Quan return -EINVAL;
230e098bc96SEvan Quan *freq = clk_table->FClocks[dpm_level].Freq;
231e098bc96SEvan Quan break;
23278842457SDavid M Nieto case SMU_VCLK:
23378842457SDavid M Nieto if (dpm_level >= NUM_VCN_DPM_LEVELS)
23478842457SDavid M Nieto return -EINVAL;
23578842457SDavid M Nieto *freq = clk_table->VClocks[dpm_level].Freq;
23678842457SDavid M Nieto break;
23778842457SDavid M Nieto case SMU_DCLK:
23878842457SDavid M Nieto if (dpm_level >= NUM_VCN_DPM_LEVELS)
23978842457SDavid M Nieto return -EINVAL;
24078842457SDavid M Nieto *freq = clk_table->DClocks[dpm_level].Freq;
24178842457SDavid M Nieto break;
24278842457SDavid M Nieto
243e098bc96SEvan Quan default:
244e098bc96SEvan Quan return -EINVAL;
245e098bc96SEvan Quan }
246e098bc96SEvan Quan
247e098bc96SEvan Quan return 0;
248e098bc96SEvan Quan }
249e098bc96SEvan Quan
renoir_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)250e098bc96SEvan Quan static int renoir_get_profiling_clk_mask(struct smu_context *smu,
251e098bc96SEvan Quan enum amd_dpm_forced_level level,
252e098bc96SEvan Quan uint32_t *sclk_mask,
253e098bc96SEvan Quan uint32_t *mclk_mask,
254e098bc96SEvan Quan uint32_t *soc_mask)
255e098bc96SEvan Quan {
256e098bc96SEvan Quan
257e098bc96SEvan Quan if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
258e098bc96SEvan Quan if (sclk_mask)
259e098bc96SEvan Quan *sclk_mask = 0;
260e098bc96SEvan Quan } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
261e098bc96SEvan Quan if (mclk_mask)
262485d531cSAlex Deucher /* mclk levels are in reverse order */
263485d531cSAlex Deucher *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
264e098bc96SEvan Quan } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
265e098bc96SEvan Quan if (sclk_mask)
266e098bc96SEvan Quan /* The sclk as gfxclk and has three level about max/min/current */
267e098bc96SEvan Quan *sclk_mask = 3 - 1;
268e098bc96SEvan Quan
269e098bc96SEvan Quan if (mclk_mask)
270485d531cSAlex Deucher /* mclk levels are in reverse order */
271485d531cSAlex Deucher *mclk_mask = 0;
272e098bc96SEvan Quan
273e098bc96SEvan Quan if (soc_mask)
274e098bc96SEvan Quan *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
275e098bc96SEvan Quan }
276e098bc96SEvan Quan
277e098bc96SEvan Quan return 0;
278e098bc96SEvan Quan }
279e098bc96SEvan Quan
renoir_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)280e098bc96SEvan Quan static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
281e098bc96SEvan Quan enum smu_clk_type clk_type,
282e098bc96SEvan Quan uint32_t *min,
283e098bc96SEvan Quan uint32_t *max)
284e098bc96SEvan Quan {
285e098bc96SEvan Quan int ret = 0;
286e098bc96SEvan Quan uint32_t mclk_mask, soc_mask;
287e098bc96SEvan Quan uint32_t clock_limit;
288e098bc96SEvan Quan
289e098bc96SEvan Quan if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
290e098bc96SEvan Quan switch (clk_type) {
291e098bc96SEvan Quan case SMU_MCLK:
292e098bc96SEvan Quan case SMU_UCLK:
293e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.uclk;
294e098bc96SEvan Quan break;
295e098bc96SEvan Quan case SMU_GFXCLK:
296e098bc96SEvan Quan case SMU_SCLK:
297e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.gfxclk;
298e098bc96SEvan Quan break;
299e098bc96SEvan Quan case SMU_SOCCLK:
300e098bc96SEvan Quan clock_limit = smu->smu_table.boot_values.socclk;
301e098bc96SEvan Quan break;
302e098bc96SEvan Quan default:
303e098bc96SEvan Quan clock_limit = 0;
304e098bc96SEvan Quan break;
305e098bc96SEvan Quan }
306e098bc96SEvan Quan
307e098bc96SEvan Quan /* clock in Mhz unit */
308e098bc96SEvan Quan if (min)
309e098bc96SEvan Quan *min = clock_limit / 100;
310e098bc96SEvan Quan if (max)
311e098bc96SEvan Quan *max = clock_limit / 100;
312e098bc96SEvan Quan
313e098bc96SEvan Quan return 0;
314e098bc96SEvan Quan }
315e098bc96SEvan Quan
316e098bc96SEvan Quan if (max) {
317e098bc96SEvan Quan ret = renoir_get_profiling_clk_mask(smu,
318e098bc96SEvan Quan AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
319e098bc96SEvan Quan NULL,
320e098bc96SEvan Quan &mclk_mask,
321e098bc96SEvan Quan &soc_mask);
322e098bc96SEvan Quan if (ret)
323e098bc96SEvan Quan goto failed;
324e098bc96SEvan Quan
325e098bc96SEvan Quan switch (clk_type) {
326e098bc96SEvan Quan case SMU_GFXCLK:
327e098bc96SEvan Quan case SMU_SCLK:
328e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
329e098bc96SEvan Quan if (ret) {
330e098bc96SEvan Quan dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
331e098bc96SEvan Quan goto failed;
332e098bc96SEvan Quan }
333e098bc96SEvan Quan break;
334e098bc96SEvan Quan case SMU_UCLK:
335e098bc96SEvan Quan case SMU_FCLK:
336e098bc96SEvan Quan case SMU_MCLK:
337e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
338e098bc96SEvan Quan if (ret)
339e098bc96SEvan Quan goto failed;
340e098bc96SEvan Quan break;
341e098bc96SEvan Quan case SMU_SOCCLK:
342e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
343e098bc96SEvan Quan if (ret)
344e098bc96SEvan Quan goto failed;
345e098bc96SEvan Quan break;
346e098bc96SEvan Quan default:
347e098bc96SEvan Quan ret = -EINVAL;
348e098bc96SEvan Quan goto failed;
349e098bc96SEvan Quan }
350e098bc96SEvan Quan }
351e098bc96SEvan Quan
352e098bc96SEvan Quan if (min) {
353e098bc96SEvan Quan switch (clk_type) {
354e098bc96SEvan Quan case SMU_GFXCLK:
355e098bc96SEvan Quan case SMU_SCLK:
356e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
357e098bc96SEvan Quan if (ret) {
358e098bc96SEvan Quan dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
359e098bc96SEvan Quan goto failed;
360e098bc96SEvan Quan }
361e098bc96SEvan Quan break;
362e098bc96SEvan Quan case SMU_UCLK:
363e098bc96SEvan Quan case SMU_FCLK:
364e098bc96SEvan Quan case SMU_MCLK:
365485d531cSAlex Deucher ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
366e098bc96SEvan Quan if (ret)
367e098bc96SEvan Quan goto failed;
368e098bc96SEvan Quan break;
369e098bc96SEvan Quan case SMU_SOCCLK:
370e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
371e098bc96SEvan Quan if (ret)
372e098bc96SEvan Quan goto failed;
373e098bc96SEvan Quan break;
374e098bc96SEvan Quan default:
375e098bc96SEvan Quan ret = -EINVAL;
376e098bc96SEvan Quan goto failed;
377e098bc96SEvan Quan }
378e098bc96SEvan Quan }
379e098bc96SEvan Quan failed:
380e098bc96SEvan Quan return ret;
381e098bc96SEvan Quan }
382e098bc96SEvan Quan
renoir_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)383ca55f459SXiaojian Du static int renoir_od_edit_dpm_table(struct smu_context *smu,
384ca55f459SXiaojian Du enum PP_OD_DPM_TABLE_COMMAND type,
385ca55f459SXiaojian Du long input[], uint32_t size)
386ca55f459SXiaojian Du {
387ca55f459SXiaojian Du int ret = 0;
388e017fb66SXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
389ca55f459SXiaojian Du
390e017fb66SXiaojian Du if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
391d7ef887fSXiaojian Du dev_warn(smu->adev->dev,
392ce7c670dSColin Ian King "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
393ca55f459SXiaojian Du return -EINVAL;
394ca55f459SXiaojian Du }
395ca55f459SXiaojian Du
396ca55f459SXiaojian Du switch (type) {
397ca55f459SXiaojian Du case PP_OD_EDIT_SCLK_VDDC_TABLE:
398ca55f459SXiaojian Du if (size != 2) {
399ca55f459SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
400ca55f459SXiaojian Du return -EINVAL;
401ca55f459SXiaojian Du }
402ca55f459SXiaojian Du
403ca55f459SXiaojian Du if (input[0] == 0) {
404ca55f459SXiaojian Du if (input[1] < smu->gfx_default_hard_min_freq) {
40508da4fcdSXiaojian Du dev_warn(smu->adev->dev,
40608da4fcdSXiaojian Du "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
407ca55f459SXiaojian Du input[1], smu->gfx_default_hard_min_freq);
408ca55f459SXiaojian Du return -EINVAL;
409ca55f459SXiaojian Du }
410ca55f459SXiaojian Du smu->gfx_actual_hard_min_freq = input[1];
411ca55f459SXiaojian Du } else if (input[0] == 1) {
412ca55f459SXiaojian Du if (input[1] > smu->gfx_default_soft_max_freq) {
41308da4fcdSXiaojian Du dev_warn(smu->adev->dev,
41408da4fcdSXiaojian Du "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
415ca55f459SXiaojian Du input[1], smu->gfx_default_soft_max_freq);
416ca55f459SXiaojian Du return -EINVAL;
417ca55f459SXiaojian Du }
418ca55f459SXiaojian Du smu->gfx_actual_soft_max_freq = input[1];
419ca55f459SXiaojian Du } else {
420ca55f459SXiaojian Du return -EINVAL;
421ca55f459SXiaojian Du }
422ca55f459SXiaojian Du break;
423ca55f459SXiaojian Du case PP_OD_RESTORE_DEFAULT_TABLE:
424ca55f459SXiaojian Du if (size != 0) {
425ca55f459SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
426ca55f459SXiaojian Du return -EINVAL;
427ca55f459SXiaojian Du }
428ca55f459SXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
429ca55f459SXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
430ca55f459SXiaojian Du break;
431ca55f459SXiaojian Du case PP_OD_COMMIT_DPM_TABLE:
432ca55f459SXiaojian Du if (size != 0) {
433ca55f459SXiaojian Du dev_err(smu->adev->dev, "Input parameter number not correct\n");
434ca55f459SXiaojian Du return -EINVAL;
435ca55f459SXiaojian Du } else {
436ca55f459SXiaojian Du if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
43708da4fcdSXiaojian Du dev_err(smu->adev->dev,
438f5d8e164SColin Ian King "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
43908da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq,
44008da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq);
441ca55f459SXiaojian Du return -EINVAL;
442ca55f459SXiaojian Du }
443ca55f459SXiaojian Du
444ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
445ca55f459SXiaojian Du SMU_MSG_SetHardMinGfxClk,
446ca55f459SXiaojian Du smu->gfx_actual_hard_min_freq,
447ca55f459SXiaojian Du NULL);
448ca55f459SXiaojian Du if (ret) {
449ca55f459SXiaojian Du dev_err(smu->adev->dev, "Set hard min sclk failed!");
450ca55f459SXiaojian Du return ret;
451ca55f459SXiaojian Du }
452ca55f459SXiaojian Du
453ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
454ca55f459SXiaojian Du SMU_MSG_SetSoftMaxGfxClk,
455ca55f459SXiaojian Du smu->gfx_actual_soft_max_freq,
456ca55f459SXiaojian Du NULL);
457ca55f459SXiaojian Du if (ret) {
458ca55f459SXiaojian Du dev_err(smu->adev->dev, "Set soft max sclk failed!");
459ca55f459SXiaojian Du return ret;
460ca55f459SXiaojian Du }
461ca55f459SXiaojian Du }
462ca55f459SXiaojian Du break;
463ca55f459SXiaojian Du default:
464ca55f459SXiaojian Du return -ENOSYS;
465ca55f459SXiaojian Du }
466ca55f459SXiaojian Du
467ca55f459SXiaojian Du return ret;
468ca55f459SXiaojian Du }
469ca55f459SXiaojian Du
renoir_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)470ca55f459SXiaojian Du static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
471ca55f459SXiaojian Du {
472ca55f459SXiaojian Du uint32_t min = 0, max = 0;
473ca55f459SXiaojian Du uint32_t ret = 0;
474ca55f459SXiaojian Du
475ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
476ca55f459SXiaojian Du SMU_MSG_GetMinGfxclkFrequency,
477ca55f459SXiaojian Du 0, &min);
478ca55f459SXiaojian Du if (ret)
479ca55f459SXiaojian Du return ret;
480ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
481ca55f459SXiaojian Du SMU_MSG_GetMaxGfxclkFrequency,
482ca55f459SXiaojian Du 0, &max);
483ca55f459SXiaojian Du if (ret)
484ca55f459SXiaojian Du return ret;
485ca55f459SXiaojian Du
486ca55f459SXiaojian Du smu->gfx_default_hard_min_freq = min;
487ca55f459SXiaojian Du smu->gfx_default_soft_max_freq = max;
488ca55f459SXiaojian Du smu->gfx_actual_hard_min_freq = 0;
489ca55f459SXiaojian Du smu->gfx_actual_soft_max_freq = 0;
490ca55f459SXiaojian Du
491ca55f459SXiaojian Du return 0;
492ca55f459SXiaojian Du }
493ca55f459SXiaojian Du
renoir_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)494e098bc96SEvan Quan static int renoir_print_clk_levels(struct smu_context *smu,
495e098bc96SEvan Quan enum smu_clk_type clk_type, char *buf)
496e098bc96SEvan Quan {
497d48a4f2cSTim Huang int i, idx, size = 0, ret = 0;
498e098bc96SEvan Quan uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
499e098bc96SEvan Quan SmuMetrics_t metrics;
500e017fb66SXiaojian Du struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
501e098bc96SEvan Quan bool cur_value_match_level = false;
502e098bc96SEvan Quan
503e098bc96SEvan Quan memset(&metrics, 0, sizeof(metrics));
504e098bc96SEvan Quan
505e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, false);
506e098bc96SEvan Quan if (ret)
507e098bc96SEvan Quan return ret;
508e098bc96SEvan Quan
5098f48ba30SLang Yu smu_cmn_get_sysfs_buf(&buf, &size);
5108f48ba30SLang Yu
511e098bc96SEvan Quan switch (clk_type) {
512ca55f459SXiaojian Du case SMU_OD_RANGE:
513e017fb66SXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
514ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
515ca55f459SXiaojian Du SMU_MSG_GetMinGfxclkFrequency,
516ca55f459SXiaojian Du 0, &min);
517ca55f459SXiaojian Du if (ret)
518ca55f459SXiaojian Du return ret;
519ca55f459SXiaojian Du ret = smu_cmn_send_smc_msg_with_param(smu,
520ca55f459SXiaojian Du SMU_MSG_GetMaxGfxclkFrequency,
521ca55f459SXiaojian Du 0, &max);
522ca55f459SXiaojian Du if (ret)
523ca55f459SXiaojian Du return ret;
524e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max);
525ca55f459SXiaojian Du }
526ca55f459SXiaojian Du break;
527ca55f459SXiaojian Du case SMU_OD_SCLK:
528e017fb66SXiaojian Du if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
529ca55f459SXiaojian Du min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
530ca55f459SXiaojian Du max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
531e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "OD_SCLK\n");
532e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "0:%10uMhz\n", min);
533e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "1:%10uMhz\n", max);
53408da4fcdSXiaojian Du }
535ca55f459SXiaojian Du break;
536e098bc96SEvan Quan case SMU_GFXCLK:
537e098bc96SEvan Quan case SMU_SCLK:
538e098bc96SEvan Quan /* retirve table returned paramters unit is MHz */
539e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
540e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
541e098bc96SEvan Quan if (!ret) {
542e098bc96SEvan Quan /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
543e098bc96SEvan Quan if (cur_value == max)
544e098bc96SEvan Quan i = 2;
545e098bc96SEvan Quan else if (cur_value == min)
546e098bc96SEvan Quan i = 0;
547e098bc96SEvan Quan else
548e098bc96SEvan Quan i = 1;
549e098bc96SEvan Quan
550e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
551e098bc96SEvan Quan i == 0 ? "*" : "");
552e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
553e098bc96SEvan Quan i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
554e098bc96SEvan Quan i == 1 ? "*" : "");
555e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
556e098bc96SEvan Quan i == 2 ? "*" : "");
557e098bc96SEvan Quan }
558e098bc96SEvan Quan return size;
559e098bc96SEvan Quan case SMU_SOCCLK:
560e098bc96SEvan Quan count = NUM_SOCCLK_DPM_LEVELS;
561e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
562e098bc96SEvan Quan break;
563e098bc96SEvan Quan case SMU_MCLK:
564e098bc96SEvan Quan count = NUM_MEMCLK_DPM_LEVELS;
565e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_FCLK];
566e098bc96SEvan Quan break;
567e098bc96SEvan Quan case SMU_DCEFCLK:
568e098bc96SEvan Quan count = NUM_DCFCLK_DPM_LEVELS;
569e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
570e098bc96SEvan Quan break;
571e098bc96SEvan Quan case SMU_FCLK:
572e098bc96SEvan Quan count = NUM_FCLK_DPM_LEVELS;
573e098bc96SEvan Quan cur_value = metrics.ClockFrequency[CLOCK_FCLK];
574e098bc96SEvan Quan break;
57578842457SDavid M Nieto case SMU_VCLK:
57678842457SDavid M Nieto count = NUM_VCN_DPM_LEVELS;
57778842457SDavid M Nieto cur_value = metrics.ClockFrequency[CLOCK_VCLK];
57878842457SDavid M Nieto break;
57978842457SDavid M Nieto case SMU_DCLK:
58078842457SDavid M Nieto count = NUM_VCN_DPM_LEVELS;
58178842457SDavid M Nieto cur_value = metrics.ClockFrequency[CLOCK_DCLK];
58278842457SDavid M Nieto break;
583e098bc96SEvan Quan default:
584ca55f459SXiaojian Du break;
585e098bc96SEvan Quan }
586e098bc96SEvan Quan
587ca55f459SXiaojian Du switch (clk_type) {
588ca55f459SXiaojian Du case SMU_GFXCLK:
589ca55f459SXiaojian Du case SMU_SCLK:
590ca55f459SXiaojian Du case SMU_SOCCLK:
591ca55f459SXiaojian Du case SMU_MCLK:
592ca55f459SXiaojian Du case SMU_DCEFCLK:
593ca55f459SXiaojian Du case SMU_FCLK:
59478842457SDavid M Nieto case SMU_VCLK:
59578842457SDavid M Nieto case SMU_DCLK:
596e098bc96SEvan Quan for (i = 0; i < count; i++) {
597d48a4f2cSTim Huang idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
598d48a4f2cSTim Huang ret = renoir_get_dpm_clk_limited(smu, clk_type, idx, &value);
599e098bc96SEvan Quan if (ret)
600e098bc96SEvan Quan return ret;
601e098bc96SEvan Quan if (!value)
602e098bc96SEvan Quan continue;
603e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
604e098bc96SEvan Quan cur_value == value ? "*" : "");
605e098bc96SEvan Quan if (cur_value == value)
606e098bc96SEvan Quan cur_value_match_level = true;
607e098bc96SEvan Quan }
608e098bc96SEvan Quan
609e098bc96SEvan Quan if (!cur_value_match_level)
610e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
611e098bc96SEvan Quan
612ca55f459SXiaojian Du break;
613ca55f459SXiaojian Du default:
614ca55f459SXiaojian Du break;
615ca55f459SXiaojian Du }
616ca55f459SXiaojian Du
617e098bc96SEvan Quan return size;
618e098bc96SEvan Quan }
619e098bc96SEvan Quan
renoir_get_current_power_state(struct smu_context * smu)620e098bc96SEvan Quan static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
621e098bc96SEvan Quan {
622e098bc96SEvan Quan enum amd_pm_state_type pm_type;
623e098bc96SEvan Quan struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
624e098bc96SEvan Quan
625e098bc96SEvan Quan if (!smu_dpm_ctx->dpm_context ||
626e098bc96SEvan Quan !smu_dpm_ctx->dpm_current_power_state)
627e098bc96SEvan Quan return -EINVAL;
628e098bc96SEvan Quan
629e098bc96SEvan Quan switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
630e098bc96SEvan Quan case SMU_STATE_UI_LABEL_BATTERY:
631e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_BATTERY;
632e098bc96SEvan Quan break;
633e098bc96SEvan Quan case SMU_STATE_UI_LABEL_BALLANCED:
634e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_BALANCED;
635e098bc96SEvan Quan break;
636e098bc96SEvan Quan case SMU_STATE_UI_LABEL_PERFORMANCE:
637e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_PERFORMANCE;
638e098bc96SEvan Quan break;
639e098bc96SEvan Quan default:
640e098bc96SEvan Quan if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
641e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
642e098bc96SEvan Quan else
643e098bc96SEvan Quan pm_type = POWER_STATE_TYPE_DEFAULT;
644e098bc96SEvan Quan break;
645e098bc96SEvan Quan }
646e098bc96SEvan Quan
647e098bc96SEvan Quan return pm_type;
648e098bc96SEvan Quan }
649e098bc96SEvan Quan
renoir_dpm_set_vcn_enable(struct smu_context * smu,bool enable)650e098bc96SEvan Quan static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
651e098bc96SEvan Quan {
652e098bc96SEvan Quan int ret = 0;
653e098bc96SEvan Quan
654e098bc96SEvan Quan if (enable) {
655e098bc96SEvan Quan /* vcn dpm on is a prerequisite for vcn power gate messages */
656e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
657e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
658e098bc96SEvan Quan if (ret)
659e098bc96SEvan Quan return ret;
660e098bc96SEvan Quan }
661e098bc96SEvan Quan } else {
662e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
663e098bc96SEvan Quan ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
664e098bc96SEvan Quan if (ret)
665e098bc96SEvan Quan return ret;
666e098bc96SEvan Quan }
667e098bc96SEvan Quan }
668e098bc96SEvan Quan
669e098bc96SEvan Quan return ret;
670e098bc96SEvan Quan }
671e098bc96SEvan Quan
renoir_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)672e098bc96SEvan Quan static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
673e098bc96SEvan Quan {
674e098bc96SEvan Quan int ret = 0;
675e098bc96SEvan Quan
676e098bc96SEvan Quan if (enable) {
677e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
678e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
679e098bc96SEvan Quan if (ret)
680e098bc96SEvan Quan return ret;
681e098bc96SEvan Quan }
682e098bc96SEvan Quan } else {
683e098bc96SEvan Quan if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
684e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
685e098bc96SEvan Quan if (ret)
686e098bc96SEvan Quan return ret;
687e098bc96SEvan Quan }
688e098bc96SEvan Quan }
689e098bc96SEvan Quan
690e098bc96SEvan Quan return ret;
691e098bc96SEvan Quan }
692e098bc96SEvan Quan
renoir_force_dpm_limit_value(struct smu_context * smu,bool highest)693e098bc96SEvan Quan static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
694e098bc96SEvan Quan {
695e098bc96SEvan Quan int ret = 0, i = 0;
696e098bc96SEvan Quan uint32_t min_freq, max_freq, force_freq;
697e098bc96SEvan Quan enum smu_clk_type clk_type;
698e098bc96SEvan Quan
699e098bc96SEvan Quan enum smu_clk_type clks[] = {
700e098bc96SEvan Quan SMU_GFXCLK,
701e098bc96SEvan Quan SMU_MCLK,
702e098bc96SEvan Quan SMU_SOCCLK,
703e098bc96SEvan Quan };
704e098bc96SEvan Quan
705e098bc96SEvan Quan for (i = 0; i < ARRAY_SIZE(clks); i++) {
706e098bc96SEvan Quan clk_type = clks[i];
707e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
708e098bc96SEvan Quan if (ret)
709e098bc96SEvan Quan return ret;
710e098bc96SEvan Quan
711e098bc96SEvan Quan force_freq = highest ? max_freq : min_freq;
712e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
713e098bc96SEvan Quan if (ret)
714e098bc96SEvan Quan return ret;
715e098bc96SEvan Quan }
716e098bc96SEvan Quan
717e098bc96SEvan Quan return ret;
718e098bc96SEvan Quan }
719e098bc96SEvan Quan
renoir_unforce_dpm_levels(struct smu_context * smu)720e098bc96SEvan Quan static int renoir_unforce_dpm_levels(struct smu_context *smu) {
721e098bc96SEvan Quan
722e098bc96SEvan Quan int ret = 0, i = 0;
723e098bc96SEvan Quan uint32_t min_freq, max_freq;
724e098bc96SEvan Quan enum smu_clk_type clk_type;
725e098bc96SEvan Quan
726e098bc96SEvan Quan struct clk_feature_map {
727e098bc96SEvan Quan enum smu_clk_type clk_type;
728e098bc96SEvan Quan uint32_t feature;
729e098bc96SEvan Quan } clk_feature_map[] = {
730e098bc96SEvan Quan {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
731e098bc96SEvan Quan {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
732e098bc96SEvan Quan {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
733e098bc96SEvan Quan };
734e098bc96SEvan Quan
735e098bc96SEvan Quan for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
736e098bc96SEvan Quan if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
737e098bc96SEvan Quan continue;
738e098bc96SEvan Quan
739e098bc96SEvan Quan clk_type = clk_feature_map[i].clk_type;
740e098bc96SEvan Quan
741e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
742e098bc96SEvan Quan if (ret)
743e098bc96SEvan Quan return ret;
744e098bc96SEvan Quan
745e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
746e098bc96SEvan Quan if (ret)
747e098bc96SEvan Quan return ret;
748e098bc96SEvan Quan }
749e098bc96SEvan Quan
750e098bc96SEvan Quan return ret;
751e098bc96SEvan Quan }
752e098bc96SEvan Quan
753fecc72f1SLee Jones /*
754e098bc96SEvan Quan * This interface get dpm clock table for dc
755e098bc96SEvan Quan */
renoir_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)756e098bc96SEvan Quan static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
757e098bc96SEvan Quan {
758e098bc96SEvan Quan DpmClocks_t *table = smu->smu_table.clocks_table;
759e098bc96SEvan Quan int i;
760e098bc96SEvan Quan
761e098bc96SEvan Quan if (!clock_table || !table)
762e098bc96SEvan Quan return -EINVAL;
763e098bc96SEvan Quan
764e098bc96SEvan Quan for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
765e098bc96SEvan Quan clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
766e098bc96SEvan Quan clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
767e098bc96SEvan Quan }
768e098bc96SEvan Quan
769e098bc96SEvan Quan for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
770e098bc96SEvan Quan clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
771e098bc96SEvan Quan clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
772e098bc96SEvan Quan }
773e098bc96SEvan Quan
774e098bc96SEvan Quan for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
775e098bc96SEvan Quan clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
776e098bc96SEvan Quan clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
777e098bc96SEvan Quan }
778e098bc96SEvan Quan
779e098bc96SEvan Quan for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) {
780e098bc96SEvan Quan clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
781e098bc96SEvan Quan clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
782e098bc96SEvan Quan }
783e098bc96SEvan Quan
78478842457SDavid M Nieto for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
78578842457SDavid M Nieto clock_table->VClocks[i].Freq = table->VClocks[i].Freq;
78678842457SDavid M Nieto clock_table->VClocks[i].Vol = table->VClocks[i].Vol;
78778842457SDavid M Nieto }
78878842457SDavid M Nieto
78978842457SDavid M Nieto for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
79078842457SDavid M Nieto clock_table->DClocks[i].Freq = table->DClocks[i].Freq;
79178842457SDavid M Nieto clock_table->DClocks[i].Vol = table->DClocks[i].Vol;
79278842457SDavid M Nieto }
79378842457SDavid M Nieto
794e098bc96SEvan Quan return 0;
795e098bc96SEvan Quan }
796e098bc96SEvan Quan
renoir_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)797e098bc96SEvan Quan static int renoir_force_clk_levels(struct smu_context *smu,
798e098bc96SEvan Quan enum smu_clk_type clk_type, uint32_t mask)
799e098bc96SEvan Quan {
800e098bc96SEvan Quan
801e098bc96SEvan Quan int ret = 0 ;
802e098bc96SEvan Quan uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
803e098bc96SEvan Quan
804e098bc96SEvan Quan soft_min_level = mask ? (ffs(mask) - 1) : 0;
805e098bc96SEvan Quan soft_max_level = mask ? (fls(mask) - 1) : 0;
806e098bc96SEvan Quan
807e098bc96SEvan Quan switch (clk_type) {
808e098bc96SEvan Quan case SMU_GFXCLK:
809e098bc96SEvan Quan case SMU_SCLK:
810e098bc96SEvan Quan if (soft_min_level > 2 || soft_max_level > 2) {
811e098bc96SEvan Quan dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
812e098bc96SEvan Quan return -EINVAL;
813e098bc96SEvan Quan }
814e098bc96SEvan Quan
815e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
816e098bc96SEvan Quan if (ret)
817e098bc96SEvan Quan return ret;
818e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
819e098bc96SEvan Quan soft_max_level == 0 ? min_freq :
820e098bc96SEvan Quan soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
821e098bc96SEvan Quan NULL);
822e098bc96SEvan Quan if (ret)
823e098bc96SEvan Quan return ret;
824e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
825e098bc96SEvan Quan soft_min_level == 2 ? max_freq :
826e098bc96SEvan Quan soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
827e098bc96SEvan Quan NULL);
828e098bc96SEvan Quan if (ret)
829e098bc96SEvan Quan return ret;
830e098bc96SEvan Quan break;
831e098bc96SEvan Quan case SMU_SOCCLK:
832e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
833e098bc96SEvan Quan if (ret)
834e098bc96SEvan Quan return ret;
835e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
836e098bc96SEvan Quan if (ret)
837e098bc96SEvan Quan return ret;
838e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
839e098bc96SEvan Quan if (ret)
840e098bc96SEvan Quan return ret;
841e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
842e098bc96SEvan Quan if (ret)
843e098bc96SEvan Quan return ret;
844e098bc96SEvan Quan break;
845e098bc96SEvan Quan case SMU_MCLK:
846e098bc96SEvan Quan case SMU_FCLK:
847e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
848e098bc96SEvan Quan if (ret)
849e098bc96SEvan Quan return ret;
850e098bc96SEvan Quan ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
851e098bc96SEvan Quan if (ret)
852e098bc96SEvan Quan return ret;
853e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
854e098bc96SEvan Quan if (ret)
855e098bc96SEvan Quan return ret;
856e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
857e098bc96SEvan Quan if (ret)
858e098bc96SEvan Quan return ret;
859e098bc96SEvan Quan break;
860e098bc96SEvan Quan default:
861e098bc96SEvan Quan break;
862e098bc96SEvan Quan }
863e098bc96SEvan Quan
864e098bc96SEvan Quan return ret;
865e098bc96SEvan Quan }
866e098bc96SEvan Quan
renoir_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)867e098bc96SEvan Quan static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
868e098bc96SEvan Quan {
869e098bc96SEvan Quan int workload_type, ret;
870e098bc96SEvan Quan uint32_t profile_mode = input[size];
871e098bc96SEvan Quan
872e098bc96SEvan Quan if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
873e098bc96SEvan Quan dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
874e098bc96SEvan Quan return -EINVAL;
875e098bc96SEvan Quan }
876e098bc96SEvan Quan
87779af0681SXiaojian Du if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
87879af0681SXiaojian Du profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
87979af0681SXiaojian Du return 0;
88079af0681SXiaojian Du
881e098bc96SEvan Quan /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
882e098bc96SEvan Quan workload_type = smu_cmn_to_asic_specific_index(smu,
883e098bc96SEvan Quan CMN2ASIC_MAPPING_WORKLOAD,
884e098bc96SEvan Quan profile_mode);
885e098bc96SEvan Quan if (workload_type < 0) {
886e098bc96SEvan Quan /*
887e098bc96SEvan Quan * TODO: If some case need switch to powersave/default power mode
888e098bc96SEvan Quan * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
889e098bc96SEvan Quan */
8909d489afdSAlex Deucher dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
891e098bc96SEvan Quan return -EINVAL;
892e098bc96SEvan Quan }
893e098bc96SEvan Quan
894e098bc96SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
895e098bc96SEvan Quan 1 << workload_type,
896e098bc96SEvan Quan NULL);
897e098bc96SEvan Quan if (ret) {
898e098bc96SEvan Quan dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
899e098bc96SEvan Quan return ret;
900e098bc96SEvan Quan }
901e098bc96SEvan Quan
902e098bc96SEvan Quan smu->power_profile_mode = profile_mode;
903e098bc96SEvan Quan
904e098bc96SEvan Quan return 0;
905e098bc96SEvan Quan }
906e098bc96SEvan Quan
renoir_set_peak_clock_by_device(struct smu_context * smu)907e098bc96SEvan Quan static int renoir_set_peak_clock_by_device(struct smu_context *smu)
908e098bc96SEvan Quan {
909e098bc96SEvan Quan int ret = 0;
910e098bc96SEvan Quan uint32_t sclk_freq = 0, uclk_freq = 0;
911e098bc96SEvan Quan
912e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
913e098bc96SEvan Quan if (ret)
914e098bc96SEvan Quan return ret;
915e098bc96SEvan Quan
916e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
917e098bc96SEvan Quan if (ret)
918e098bc96SEvan Quan return ret;
919e098bc96SEvan Quan
920e098bc96SEvan Quan ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
921e098bc96SEvan Quan if (ret)
922e098bc96SEvan Quan return ret;
923e098bc96SEvan Quan
924e098bc96SEvan Quan ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
925e098bc96SEvan Quan if (ret)
926e098bc96SEvan Quan return ret;
927e098bc96SEvan Quan
928e098bc96SEvan Quan return ret;
929e098bc96SEvan Quan }
930e098bc96SEvan Quan
renoir_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)931e098bc96SEvan Quan static int renoir_set_performance_level(struct smu_context *smu,
932e098bc96SEvan Quan enum amd_dpm_forced_level level)
933e098bc96SEvan Quan {
934e098bc96SEvan Quan int ret = 0;
935e098bc96SEvan Quan uint32_t sclk_mask, mclk_mask, soc_mask;
936e098bc96SEvan Quan
937e098bc96SEvan Quan switch (level) {
938e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_HIGH:
93908da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
94008da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
94108da4fcdSXiaojian Du
942e098bc96SEvan Quan ret = renoir_force_dpm_limit_value(smu, true);
943e098bc96SEvan Quan break;
944e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_LOW:
94508da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
94608da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
94708da4fcdSXiaojian Du
948e098bc96SEvan Quan ret = renoir_force_dpm_limit_value(smu, false);
949e098bc96SEvan Quan break;
950e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_AUTO:
95108da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
95208da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
95308da4fcdSXiaojian Du
954e098bc96SEvan Quan ret = renoir_unforce_dpm_levels(smu);
955e098bc96SEvan Quan break;
95692e00593SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
95708da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
95808da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
95908da4fcdSXiaojian Du
96092e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
96192e00593SEvan Quan SMU_MSG_SetHardMinGfxClk,
96292e00593SEvan Quan RENOIR_UMD_PSTATE_GFXCLK,
96392e00593SEvan Quan NULL);
96492e00593SEvan Quan if (ret)
96592e00593SEvan Quan return ret;
96692e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
96792e00593SEvan Quan SMU_MSG_SetHardMinFclkByFreq,
96892e00593SEvan Quan RENOIR_UMD_PSTATE_FCLK,
96992e00593SEvan Quan NULL);
97092e00593SEvan Quan if (ret)
97192e00593SEvan Quan return ret;
97292e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
97392e00593SEvan Quan SMU_MSG_SetHardMinSocclkByFreq,
97492e00593SEvan Quan RENOIR_UMD_PSTATE_SOCCLK,
97592e00593SEvan Quan NULL);
97692e00593SEvan Quan if (ret)
97792e00593SEvan Quan return ret;
97892e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
97992e00593SEvan Quan SMU_MSG_SetHardMinVcn,
98092e00593SEvan Quan RENOIR_UMD_PSTATE_VCNCLK,
98192e00593SEvan Quan NULL);
98292e00593SEvan Quan if (ret)
98392e00593SEvan Quan return ret;
98492e00593SEvan Quan
98592e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
98692e00593SEvan Quan SMU_MSG_SetSoftMaxGfxClk,
98792e00593SEvan Quan RENOIR_UMD_PSTATE_GFXCLK,
98892e00593SEvan Quan NULL);
98992e00593SEvan Quan if (ret)
99092e00593SEvan Quan return ret;
99192e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
99292e00593SEvan Quan SMU_MSG_SetSoftMaxFclkByFreq,
99392e00593SEvan Quan RENOIR_UMD_PSTATE_FCLK,
99492e00593SEvan Quan NULL);
99592e00593SEvan Quan if (ret)
99692e00593SEvan Quan return ret;
99792e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
99892e00593SEvan Quan SMU_MSG_SetSoftMaxSocclkByFreq,
99992e00593SEvan Quan RENOIR_UMD_PSTATE_SOCCLK,
100092e00593SEvan Quan NULL);
100192e00593SEvan Quan if (ret)
100292e00593SEvan Quan return ret;
100392e00593SEvan Quan ret = smu_cmn_send_smc_msg_with_param(smu,
100492e00593SEvan Quan SMU_MSG_SetSoftMaxVcn,
100592e00593SEvan Quan RENOIR_UMD_PSTATE_VCNCLK,
100692e00593SEvan Quan NULL);
100792e00593SEvan Quan if (ret)
100892e00593SEvan Quan return ret;
100992e00593SEvan Quan break;
1010e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1011e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
101208da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
101308da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
101408da4fcdSXiaojian Du
1015e098bc96SEvan Quan ret = renoir_get_profiling_clk_mask(smu, level,
1016e098bc96SEvan Quan &sclk_mask,
1017e098bc96SEvan Quan &mclk_mask,
1018e098bc96SEvan Quan &soc_mask);
1019e098bc96SEvan Quan if (ret)
1020e098bc96SEvan Quan return ret;
1021e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_SCLK, 1 << sclk_mask);
1022e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_MCLK, 1 << mclk_mask);
1023e098bc96SEvan Quan renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1024e098bc96SEvan Quan break;
1025e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
102608da4fcdSXiaojian Du smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
102708da4fcdSXiaojian Du smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
102808da4fcdSXiaojian Du
1029e098bc96SEvan Quan ret = renoir_set_peak_clock_by_device(smu);
1030e098bc96SEvan Quan break;
1031e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_MANUAL:
1032e098bc96SEvan Quan case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1033e098bc96SEvan Quan default:
1034e098bc96SEvan Quan break;
1035e098bc96SEvan Quan }
1036e098bc96SEvan Quan return ret;
1037e098bc96SEvan Quan }
1038e098bc96SEvan Quan
1039e098bc96SEvan Quan /* save watermark settings into pplib smu structure,
1040e098bc96SEvan Quan * also pass data to smu controller
1041e098bc96SEvan Quan */
renoir_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1042e098bc96SEvan Quan static int renoir_set_watermarks_table(
1043e098bc96SEvan Quan struct smu_context *smu,
10447b9c7e30SEvan Quan struct pp_smu_wm_range_sets *clock_ranges)
1045e098bc96SEvan Quan {
1046e098bc96SEvan Quan Watermarks_t *table = smu->smu_table.watermarks_table;
1047e098bc96SEvan Quan int ret = 0;
1048e098bc96SEvan Quan int i;
1049e098bc96SEvan Quan
1050e098bc96SEvan Quan if (clock_ranges) {
10517b9c7e30SEvan Quan if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
10527b9c7e30SEvan Quan clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1053e098bc96SEvan Quan return -EINVAL;
1054e098bc96SEvan Quan
1055e098bc96SEvan Quan /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
10567b9c7e30SEvan Quan for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1057e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MinClock =
10587b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1059e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MaxClock =
10607b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1061e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MinMclk =
10627b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1063e098bc96SEvan Quan table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
10647b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
10657b9c7e30SEvan Quan
10667b9c7e30SEvan Quan table->WatermarkRow[WM_DCFCLK][i].WmSetting =
10677b9c7e30SEvan Quan clock_ranges->reader_wm_sets[i].wm_inst;
1068ce2c0006SEvan Quan table->WatermarkRow[WM_DCFCLK][i].WmType =
1069ce2c0006SEvan Quan clock_ranges->reader_wm_sets[i].wm_type;
1070e098bc96SEvan Quan }
1071e098bc96SEvan Quan
10727b9c7e30SEvan Quan for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1073e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MinClock =
10747b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1075e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MaxClock =
10767b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1077e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MinMclk =
10787b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1079e098bc96SEvan Quan table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
10807b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
10817b9c7e30SEvan Quan
10827b9c7e30SEvan Quan table->WatermarkRow[WM_SOCCLK][i].WmSetting =
10837b9c7e30SEvan Quan clock_ranges->writer_wm_sets[i].wm_inst;
1084ce2c0006SEvan Quan table->WatermarkRow[WM_SOCCLK][i].WmType =
1085ce2c0006SEvan Quan clock_ranges->writer_wm_sets[i].wm_type;
1086e098bc96SEvan Quan }
1087e098bc96SEvan Quan
1088e098bc96SEvan Quan smu->watermarks_bitmap |= WATERMARKS_EXIST;
1089e098bc96SEvan Quan }
1090e098bc96SEvan Quan
1091e098bc96SEvan Quan /* pass data to smu controller */
1092e098bc96SEvan Quan if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1093e098bc96SEvan Quan !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1094e098bc96SEvan Quan ret = smu_cmn_write_watermarks_table(smu);
1095e098bc96SEvan Quan if (ret) {
1096e098bc96SEvan Quan dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1097e098bc96SEvan Quan return ret;
1098e098bc96SEvan Quan }
1099e098bc96SEvan Quan smu->watermarks_bitmap |= WATERMARKS_LOADED;
1100e098bc96SEvan Quan }
1101e098bc96SEvan Quan
1102e098bc96SEvan Quan return 0;
1103e098bc96SEvan Quan }
1104e098bc96SEvan Quan
renoir_get_power_profile_mode(struct smu_context * smu,char * buf)1105e098bc96SEvan Quan static int renoir_get_power_profile_mode(struct smu_context *smu,
1106e098bc96SEvan Quan char *buf)
1107e098bc96SEvan Quan {
1108e098bc96SEvan Quan uint32_t i, size = 0;
1109e098bc96SEvan Quan int16_t workload_type = 0;
1110e098bc96SEvan Quan
1111e098bc96SEvan Quan if (!buf)
1112e098bc96SEvan Quan return -EINVAL;
1113e098bc96SEvan Quan
1114e098bc96SEvan Quan for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1115e098bc96SEvan Quan /*
1116e098bc96SEvan Quan * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1117e098bc96SEvan Quan * Not all profile modes are supported on arcturus.
1118e098bc96SEvan Quan */
1119e098bc96SEvan Quan workload_type = smu_cmn_to_asic_specific_index(smu,
1120e098bc96SEvan Quan CMN2ASIC_MAPPING_WORKLOAD,
1121e098bc96SEvan Quan i);
1122e098bc96SEvan Quan if (workload_type < 0)
1123e098bc96SEvan Quan continue;
1124e098bc96SEvan Quan
1125e738c2f0SDarren Powell size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
112694a80b5bSDarren Powell i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1127e098bc96SEvan Quan }
1128e098bc96SEvan Quan
1129e098bc96SEvan Quan return size;
1130e098bc96SEvan Quan }
1131e098bc96SEvan Quan
renoir_get_ss_power_percent(SmuMetrics_t * metrics,uint32_t * apu_percent,uint32_t * dgpu_percent)1132138292f1SSathishkumar S static void renoir_get_ss_power_percent(SmuMetrics_t *metrics,
1133138292f1SSathishkumar S uint32_t *apu_percent, uint32_t *dgpu_percent)
1134138292f1SSathishkumar S {
1135138292f1SSathishkumar S uint32_t apu_boost = 0;
1136138292f1SSathishkumar S uint32_t dgpu_boost = 0;
1137138292f1SSathishkumar S uint16_t apu_limit = 0;
1138138292f1SSathishkumar S uint16_t dgpu_limit = 0;
1139138292f1SSathishkumar S uint16_t apu_power = 0;
1140138292f1SSathishkumar S uint16_t dgpu_power = 0;
1141138292f1SSathishkumar S
1142138292f1SSathishkumar S apu_power = metrics->ApuPower;
1143138292f1SSathishkumar S apu_limit = metrics->StapmOriginalLimit;
1144138292f1SSathishkumar S if (apu_power > apu_limit && apu_limit != 0)
1145138292f1SSathishkumar S apu_boost = ((apu_power - apu_limit) * 100) / apu_limit;
1146138292f1SSathishkumar S apu_boost = (apu_boost > 100) ? 100 : apu_boost;
1147138292f1SSathishkumar S
1148138292f1SSathishkumar S dgpu_power = metrics->dGpuPower;
1149138292f1SSathishkumar S if (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit)
1150138292f1SSathishkumar S dgpu_limit = metrics->StapmCurrentLimit - metrics->StapmOriginalLimit;
1151138292f1SSathishkumar S if (dgpu_power > dgpu_limit && dgpu_limit != 0)
1152138292f1SSathishkumar S dgpu_boost = ((dgpu_power - dgpu_limit) * 100) / dgpu_limit;
1153138292f1SSathishkumar S dgpu_boost = (dgpu_boost > 100) ? 100 : dgpu_boost;
1154138292f1SSathishkumar S
1155138292f1SSathishkumar S if (dgpu_boost >= apu_boost)
1156138292f1SSathishkumar S apu_boost = 0;
1157138292f1SSathishkumar S else
1158138292f1SSathishkumar S dgpu_boost = 0;
1159138292f1SSathishkumar S
1160138292f1SSathishkumar S *apu_percent = apu_boost;
1161138292f1SSathishkumar S *dgpu_percent = dgpu_boost;
1162138292f1SSathishkumar S }
1163138292f1SSathishkumar S
1164138292f1SSathishkumar S
renoir_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)116522ca75eaSAlex Deucher static int renoir_get_smu_metrics_data(struct smu_context *smu,
116622ca75eaSAlex Deucher MetricsMember_t member,
116722ca75eaSAlex Deucher uint32_t *value)
116822ca75eaSAlex Deucher {
116922ca75eaSAlex Deucher struct smu_table_context *smu_table = &smu->smu_table;
117022ca75eaSAlex Deucher
117122ca75eaSAlex Deucher SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
117222ca75eaSAlex Deucher int ret = 0;
1173138292f1SSathishkumar S uint32_t apu_percent = 0;
1174138292f1SSathishkumar S uint32_t dgpu_percent = 0;
1175c7bae4aaSjie1zhan struct amdgpu_device *adev = smu->adev;
1176138292f1SSathishkumar S
117722ca75eaSAlex Deucher
1178da11407fSEvan Quan ret = smu_cmn_get_metrics_table(smu,
117922ca75eaSAlex Deucher NULL,
118022ca75eaSAlex Deucher false);
1181da11407fSEvan Quan if (ret)
118222ca75eaSAlex Deucher return ret;
118322ca75eaSAlex Deucher
118422ca75eaSAlex Deucher switch (member) {
118522ca75eaSAlex Deucher case METRICS_AVERAGE_GFXCLK:
118622ca75eaSAlex Deucher *value = metrics->ClockFrequency[CLOCK_GFXCLK];
118722ca75eaSAlex Deucher break;
118822ca75eaSAlex Deucher case METRICS_AVERAGE_SOCCLK:
118922ca75eaSAlex Deucher *value = metrics->ClockFrequency[CLOCK_SOCCLK];
119022ca75eaSAlex Deucher break;
119122ca75eaSAlex Deucher case METRICS_AVERAGE_UCLK:
119222ca75eaSAlex Deucher *value = metrics->ClockFrequency[CLOCK_FCLK];
119322ca75eaSAlex Deucher break;
119422ca75eaSAlex Deucher case METRICS_AVERAGE_GFXACTIVITY:
119522ca75eaSAlex Deucher *value = metrics->AverageGfxActivity / 100;
119622ca75eaSAlex Deucher break;
119722ca75eaSAlex Deucher case METRICS_AVERAGE_VCNACTIVITY:
119822ca75eaSAlex Deucher *value = metrics->AverageUvdActivity / 100;
119922ca75eaSAlex Deucher break;
120047f1724dSMario Limonciello case METRICS_CURR_SOCKETPOWER:
1201c7bae4aaSjie1zhan if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1)) && (adev->pm.fw_version >= 0x40000f)) ||
1202c7bae4aaSjie1zhan ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0)) && (adev->pm.fw_version >= 0x373200)))
1203c7bae4aaSjie1zhan *value = metrics->CurrentSocketPower << 8;
1204c7bae4aaSjie1zhan else
1205137aac26SAlex Deucher *value = (metrics->CurrentSocketPower << 8) / 1000;
120622ca75eaSAlex Deucher break;
120722ca75eaSAlex Deucher case METRICS_TEMPERATURE_EDGE:
120822ca75eaSAlex Deucher *value = (metrics->GfxTemperature / 100) *
120922ca75eaSAlex Deucher SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
121022ca75eaSAlex Deucher break;
121122ca75eaSAlex Deucher case METRICS_TEMPERATURE_HOTSPOT:
121222ca75eaSAlex Deucher *value = (metrics->SocTemperature / 100) *
121322ca75eaSAlex Deucher SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
121422ca75eaSAlex Deucher break;
121522ca75eaSAlex Deucher case METRICS_THROTTLER_STATUS:
121622ca75eaSAlex Deucher *value = metrics->ThrottlerStatus;
121722ca75eaSAlex Deucher break;
121822ca75eaSAlex Deucher case METRICS_VOLTAGE_VDDGFX:
121922ca75eaSAlex Deucher *value = metrics->Voltage[0];
122022ca75eaSAlex Deucher break;
122122ca75eaSAlex Deucher case METRICS_VOLTAGE_VDDSOC:
122222ca75eaSAlex Deucher *value = metrics->Voltage[1];
122322ca75eaSAlex Deucher break;
12247b32dd0bSSathishkumar S case METRICS_SS_APU_SHARE:
1225138292f1SSathishkumar S /* return the percentage of APU power boost
1226138292f1SSathishkumar S * with respect to APU's power limit.
12277b32dd0bSSathishkumar S */
1228138292f1SSathishkumar S renoir_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
1229138292f1SSathishkumar S *value = apu_percent;
12307b32dd0bSSathishkumar S break;
12317b32dd0bSSathishkumar S case METRICS_SS_DGPU_SHARE:
1232138292f1SSathishkumar S /* return the percentage of dGPU power boost
1233138292f1SSathishkumar S * with respect to dGPU's power limit.
12347b32dd0bSSathishkumar S */
1235138292f1SSathishkumar S renoir_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
1236138292f1SSathishkumar S *value = dgpu_percent;
12377b32dd0bSSathishkumar S break;
123822ca75eaSAlex Deucher default:
123922ca75eaSAlex Deucher *value = UINT_MAX;
124022ca75eaSAlex Deucher break;
124122ca75eaSAlex Deucher }
124222ca75eaSAlex Deucher
124322ca75eaSAlex Deucher return ret;
124422ca75eaSAlex Deucher }
124522ca75eaSAlex Deucher
renoir_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1246e098bc96SEvan Quan static int renoir_read_sensor(struct smu_context *smu,
1247e098bc96SEvan Quan enum amd_pp_sensors sensor,
1248e098bc96SEvan Quan void *data, uint32_t *size)
1249e098bc96SEvan Quan {
1250e098bc96SEvan Quan int ret = 0;
1251e098bc96SEvan Quan
1252e098bc96SEvan Quan if (!data || !size)
1253e098bc96SEvan Quan return -EINVAL;
1254e098bc96SEvan Quan
1255e098bc96SEvan Quan switch (sensor) {
1256e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GPU_LOAD:
125722ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu,
125822ca75eaSAlex Deucher METRICS_AVERAGE_GFXACTIVITY,
125922ca75eaSAlex Deucher (uint32_t *)data);
1260e098bc96SEvan Quan *size = 4;
1261e098bc96SEvan Quan break;
126222ca75eaSAlex Deucher case AMDGPU_PP_SENSOR_EDGE_TEMP:
126322ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu,
126422ca75eaSAlex Deucher METRICS_TEMPERATURE_EDGE,
126522ca75eaSAlex Deucher (uint32_t *)data);
126622ca75eaSAlex Deucher *size = 4;
126722ca75eaSAlex Deucher break;
126822ca75eaSAlex Deucher case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
126922ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu,
127022ca75eaSAlex Deucher METRICS_TEMPERATURE_HOTSPOT,
127122ca75eaSAlex Deucher (uint32_t *)data);
1272e098bc96SEvan Quan *size = 4;
1273e098bc96SEvan Quan break;
1274e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GFX_MCLK:
127522ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu,
127622ca75eaSAlex Deucher METRICS_AVERAGE_UCLK,
127722ca75eaSAlex Deucher (uint32_t *)data);
1278e098bc96SEvan Quan *(uint32_t *)data *= 100;
1279e098bc96SEvan Quan *size = 4;
1280e098bc96SEvan Quan break;
1281e098bc96SEvan Quan case AMDGPU_PP_SENSOR_GFX_SCLK:
128222ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu,
128322ca75eaSAlex Deucher METRICS_AVERAGE_GFXCLK,
128422ca75eaSAlex Deucher (uint32_t *)data);
1285e098bc96SEvan Quan *(uint32_t *)data *= 100;
1286e098bc96SEvan Quan *size = 4;
1287e098bc96SEvan Quan break;
128861426114SAlex Deucher case AMDGPU_PP_SENSOR_VDDGFX:
128922ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu,
129022ca75eaSAlex Deucher METRICS_VOLTAGE_VDDGFX,
129122ca75eaSAlex Deucher (uint32_t *)data);
129261426114SAlex Deucher *size = 4;
129361426114SAlex Deucher break;
129461426114SAlex Deucher case AMDGPU_PP_SENSOR_VDDNB:
129522ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu,
129622ca75eaSAlex Deucher METRICS_VOLTAGE_VDDSOC,
129722ca75eaSAlex Deucher (uint32_t *)data);
129861426114SAlex Deucher *size = 4;
129961426114SAlex Deucher break;
130047f1724dSMario Limonciello case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
130122ca75eaSAlex Deucher ret = renoir_get_smu_metrics_data(smu,
130247f1724dSMario Limonciello METRICS_CURR_SOCKETPOWER,
130322ca75eaSAlex Deucher (uint32_t *)data);
1304b49dc928SAlex Deucher *size = 4;
1305b49dc928SAlex Deucher break;
13067b32dd0bSSathishkumar S case AMDGPU_PP_SENSOR_SS_APU_SHARE:
13077b32dd0bSSathishkumar S ret = renoir_get_smu_metrics_data(smu,
13087b32dd0bSSathishkumar S METRICS_SS_APU_SHARE,
13097b32dd0bSSathishkumar S (uint32_t *)data);
13107b32dd0bSSathishkumar S *size = 4;
13117b32dd0bSSathishkumar S break;
13127b32dd0bSSathishkumar S case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
13137b32dd0bSSathishkumar S ret = renoir_get_smu_metrics_data(smu,
13147b32dd0bSSathishkumar S METRICS_SS_DGPU_SHARE,
13157b32dd0bSSathishkumar S (uint32_t *)data);
13167b32dd0bSSathishkumar S *size = 4;
13177b32dd0bSSathishkumar S break;
1318*9366c2e8SMario Limonciello case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1319e098bc96SEvan Quan default:
1320e098bc96SEvan Quan ret = -EOPNOTSUPP;
1321e098bc96SEvan Quan break;
1322e098bc96SEvan Quan }
1323e098bc96SEvan Quan
1324e098bc96SEvan Quan return ret;
1325e098bc96SEvan Quan }
1326e098bc96SEvan Quan
renoir_is_dpm_running(struct smu_context * smu)1327e098bc96SEvan Quan static bool renoir_is_dpm_running(struct smu_context *smu)
1328e098bc96SEvan Quan {
1329e098bc96SEvan Quan struct amdgpu_device *adev = smu->adev;
1330e098bc96SEvan Quan
1331e098bc96SEvan Quan /*
1332e098bc96SEvan Quan * Until now, the pmfw hasn't exported the interface of SMU
1333e098bc96SEvan Quan * feature mask to APU SKU so just force on all the feature
1334e098bc96SEvan Quan * at early initial stage.
1335e098bc96SEvan Quan */
1336e098bc96SEvan Quan if (adev->in_suspend)
1337e098bc96SEvan Quan return false;
1338e098bc96SEvan Quan else
1339e098bc96SEvan Quan return true;
1340e098bc96SEvan Quan
1341e098bc96SEvan Quan }
1342e098bc96SEvan Quan
renoir_get_gpu_metrics(struct smu_context * smu,void ** table)1343e098bc96SEvan Quan static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1344e098bc96SEvan Quan void **table)
1345e098bc96SEvan Quan {
1346e098bc96SEvan Quan struct smu_table_context *smu_table = &smu->smu_table;
1347d4c9b03fSGraham Sider struct gpu_metrics_v2_2 *gpu_metrics =
1348d4c9b03fSGraham Sider (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1349e098bc96SEvan Quan SmuMetrics_t metrics;
1350e098bc96SEvan Quan int ret = 0;
1351e098bc96SEvan Quan
1352e098bc96SEvan Quan ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1353e098bc96SEvan Quan if (ret)
1354e098bc96SEvan Quan return ret;
1355e098bc96SEvan Quan
1356d4c9b03fSGraham Sider smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1357e098bc96SEvan Quan
1358e098bc96SEvan Quan gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1359e098bc96SEvan Quan gpu_metrics->temperature_soc = metrics.SocTemperature;
1360e098bc96SEvan Quan memcpy(&gpu_metrics->temperature_core[0],
1361e098bc96SEvan Quan &metrics.CoreTemperature[0],
1362e098bc96SEvan Quan sizeof(uint16_t) * 8);
1363e098bc96SEvan Quan gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1364e098bc96SEvan Quan gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1365e098bc96SEvan Quan
1366e098bc96SEvan Quan gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1367e098bc96SEvan Quan gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1368e098bc96SEvan Quan
1369e098bc96SEvan Quan gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1370e098bc96SEvan Quan gpu_metrics->average_cpu_power = metrics.Power[0];
1371e098bc96SEvan Quan gpu_metrics->average_soc_power = metrics.Power[1];
1372e098bc96SEvan Quan memcpy(&gpu_metrics->average_core_power[0],
1373e098bc96SEvan Quan &metrics.CorePower[0],
1374e098bc96SEvan Quan sizeof(uint16_t) * 8);
1375e098bc96SEvan Quan
1376e098bc96SEvan Quan gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1377e098bc96SEvan Quan gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1378e098bc96SEvan Quan gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1379e098bc96SEvan Quan gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1380e098bc96SEvan Quan
1381e098bc96SEvan Quan gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1382e098bc96SEvan Quan gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1383e098bc96SEvan Quan gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1384e098bc96SEvan Quan gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1385e098bc96SEvan Quan gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1386e098bc96SEvan Quan gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1387e098bc96SEvan Quan memcpy(&gpu_metrics->current_coreclk[0],
1388e098bc96SEvan Quan &metrics.CoreFrequency[0],
1389e098bc96SEvan Quan sizeof(uint16_t) * 8);
1390e098bc96SEvan Quan gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1391e098bc96SEvan Quan gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1392e098bc96SEvan Quan
1393e098bc96SEvan Quan gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1394d4c9b03fSGraham Sider gpu_metrics->indep_throttle_status =
1395d4c9b03fSGraham Sider smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1396d4c9b03fSGraham Sider renoir_throttler_map);
1397e098bc96SEvan Quan
1398e098bc96SEvan Quan gpu_metrics->fan_pwm = metrics.FanPwm;
1399e098bc96SEvan Quan
1400de4b7cd8SKevin Wang gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1401de4b7cd8SKevin Wang
1402e098bc96SEvan Quan *table = (void *)gpu_metrics;
1403e098bc96SEvan Quan
1404d4c9b03fSGraham Sider return sizeof(struct gpu_metrics_v2_2);
1405e098bc96SEvan Quan }
1406e098bc96SEvan Quan
renoir_gfx_state_change_set(struct smu_context * smu,uint32_t state)14078279bb4eSPrike Liang static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
14088279bb4eSPrike Liang {
14098279bb4eSPrike Liang
1410d96dd7efSPrike Liang return 0;
14118279bb4eSPrike Liang }
14128279bb4eSPrike Liang
renoir_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)1413f141e251SPrike Liang static int renoir_get_enabled_mask(struct smu_context *smu,
1414f141e251SPrike Liang uint64_t *feature_mask)
1415f141e251SPrike Liang {
1416f141e251SPrike Liang if (!feature_mask)
1417f141e251SPrike Liang return -EINVAL;
1418f141e251SPrike Liang memset(feature_mask, 0xff, sizeof(*feature_mask));
1419f141e251SPrike Liang
1420f141e251SPrike Liang return 0;
1421f141e251SPrike Liang }
1422f141e251SPrike Liang
1423e098bc96SEvan Quan static const struct pptable_funcs renoir_ppt_funcs = {
1424e098bc96SEvan Quan .set_power_state = NULL,
1425e098bc96SEvan Quan .print_clk_levels = renoir_print_clk_levels,
1426e098bc96SEvan Quan .get_current_power_state = renoir_get_current_power_state,
1427e098bc96SEvan Quan .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1428e098bc96SEvan Quan .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1429e098bc96SEvan Quan .force_clk_levels = renoir_force_clk_levels,
1430e098bc96SEvan Quan .set_power_profile_mode = renoir_set_power_profile_mode,
1431e098bc96SEvan Quan .set_performance_level = renoir_set_performance_level,
1432e098bc96SEvan Quan .get_dpm_clock_table = renoir_get_dpm_clock_table,
1433e098bc96SEvan Quan .set_watermarks_table = renoir_set_watermarks_table,
1434e098bc96SEvan Quan .get_power_profile_mode = renoir_get_power_profile_mode,
1435e098bc96SEvan Quan .read_sensor = renoir_read_sensor,
1436e098bc96SEvan Quan .check_fw_status = smu_v12_0_check_fw_status,
1437e098bc96SEvan Quan .check_fw_version = smu_v12_0_check_fw_version,
1438e098bc96SEvan Quan .powergate_sdma = smu_v12_0_powergate_sdma,
1439e098bc96SEvan Quan .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1440e098bc96SEvan Quan .send_smc_msg = smu_cmn_send_smc_msg,
1441e098bc96SEvan Quan .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1442e098bc96SEvan Quan .gfx_off_control = smu_v12_0_gfx_off_control,
1443e098bc96SEvan Quan .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1444e098bc96SEvan Quan .init_smc_tables = renoir_init_smc_tables,
1445e098bc96SEvan Quan .fini_smc_tables = smu_v12_0_fini_smc_tables,
1446e098bc96SEvan Quan .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1447f141e251SPrike Liang .get_enabled_mask = renoir_get_enabled_mask,
1448e098bc96SEvan Quan .feature_is_enabled = smu_cmn_feature_is_enabled,
1449e098bc96SEvan Quan .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1450e098bc96SEvan Quan .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1451e098bc96SEvan Quan .mode2_reset = smu_v12_0_mode2_reset,
1452e098bc96SEvan Quan .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1453e098bc96SEvan Quan .set_driver_table_location = smu_v12_0_set_driver_table_location,
1454e098bc96SEvan Quan .is_dpm_running = renoir_is_dpm_running,
1455e098bc96SEvan Quan .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1456e098bc96SEvan Quan .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1457e098bc96SEvan Quan .get_gpu_metrics = renoir_get_gpu_metrics,
14588279bb4eSPrike Liang .gfx_state_change_set = renoir_gfx_state_change_set,
1459ca55f459SXiaojian Du .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters,
1460ca55f459SXiaojian Du .od_edit_dpm_table = renoir_od_edit_dpm_table,
1461eb607a00SXiaojian Du .get_vbios_bootup_values = smu_v12_0_get_vbios_bootup_values,
1462e098bc96SEvan Quan };
1463e098bc96SEvan Quan
renoir_set_ppt_funcs(struct smu_context * smu)1464e098bc96SEvan Quan void renoir_set_ppt_funcs(struct smu_context *smu)
1465e098bc96SEvan Quan {
1466da1db031SAlex Deucher struct amdgpu_device *adev = smu->adev;
1467da1db031SAlex Deucher
1468e098bc96SEvan Quan smu->ppt_funcs = &renoir_ppt_funcs;
1469e098bc96SEvan Quan smu->message_map = renoir_message_map;
1470e098bc96SEvan Quan smu->clock_map = renoir_clk_map;
1471e098bc96SEvan Quan smu->table_map = renoir_table_map;
1472e098bc96SEvan Quan smu->workload_map = renoir_workload_map;
1473e098bc96SEvan Quan smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1474e098bc96SEvan Quan smu->is_apu = true;
1475da1db031SAlex Deucher smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1476da1db031SAlex Deucher smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1477da1db031SAlex Deucher smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
1478e098bc96SEvan Quan }
1479