Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45 |
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#
9366c2e8 |
| 10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWER
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <ale
drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWER
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead.
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
47f1724d |
| 10-Aug-2023 |
Mario Limonciello <mario.limonciello@amd.com> |
drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`
Some GPUs have been overloading average power values and input power values. To disambiguate these, introduce a new `AMDGPU_PP_SENSOR_GPU_INPUT_
drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`
Some GPUs have been overloading average power values and input power values. To disambiguate these, introduce a new `AMDGPU_PP_SENSOR_GPU_INPUT_POWER` and the GPUs that share input power update to use this instead of average power.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2746 Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.44, v6.1.43 |
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#
20e688a8 |
| 31-Jul-2023 |
Ran Sun <sunran001@208suo.com> |
drm/amd/pm: Clean up errors in smu_v13_0_5_ppt.c
Fix the following errors reported by checkpatch:
ERROR: space prohibited before that ',' (ctx:WxW)
Signed-off-by: Ran Sun <sunran001@208suo.com> Si
drm/amd/pm: Clean up errors in smu_v13_0_5_ppt.c
Fix the following errors reported by checkpatch:
ERROR: space prohibited before that ',' (ctx:WxW)
Signed-off-by: Ran Sun <sunran001@208suo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33 |
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#
121f17ac |
| 09-Jun-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: enable more Pstates profile levels for SMU v13.0.5
This patch enables following UMD stable Pstates profile levels for power_dpm_force_performance_level interface.
- profile_peak - profi
drm/amd/pm: enable more Pstates profile levels for SMU v13.0.5
This patch enables following UMD stable Pstates profile levels for power_dpm_force_performance_level interface.
- profile_peak - profile_min_sclk - profile_standard
Signed-off-by: Tim Huang <Tim.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
fcdb3832 |
| 09-Jun-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: enable vclk and dclk Pstates for SMU v13.0.5
Add the ability to control the vclk and dclk frequency by power_dpm_force_performance_level interface.
Signed-off-by: Tim Huang <Tim.Huang@a
drm/amd/pm: enable vclk and dclk Pstates for SMU v13.0.5
Add the ability to control the vclk and dclk frequency by power_dpm_force_performance_level interface.
Signed-off-by: Tim Huang <Tim.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
e22821e6 |
| 09-Jun-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: fix vclk setting failed for SMU v13.0.5
PMFW use the left-shifted 16 bits argument to set the VCLK DPM frequency for SMU v13.0.5.
Signed-off-by: Tim Huang <Tim.Huang@amd.com> Acked-by:
drm/amd/pm: fix vclk setting failed for SMU v13.0.5
PMFW use the left-shifted 16 bits argument to set the VCLK DPM frequency for SMU v13.0.5.
Signed-off-by: Tim Huang <Tim.Huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.32, v6.1.31, v6.1.30 |
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#
d9ed111b |
| 20-May-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: reverse mclk clocks levels for SMU v13.0.5
This patch reverses the DPM clocks levels output of pp_dpm_mclk.
On dGPUs and older APUs we expose the levels from lowest clocks to highest cl
drm/amd/pm: reverse mclk clocks levels for SMU v13.0.5
This patch reverses the DPM clocks levels output of pp_dpm_mclk.
On dGPUs and older APUs we expose the levels from lowest clocks to highest clocks. But for some APUs, the clocks levels that from the DFPstateTable are given the reversed orders by PMFW. Like the memory DPM clocks that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools and software that talks to the driver then has to know different ways to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the driver consistently.
Signed-off-by: Tim Huang <Tim.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13 |
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#
9661bf68 |
| 21-Feb-2023 |
Lijo Lazar <lijo.lazar@amd.com> |
drm/amd/pm: Keep interface version in PMFW header
Use the interface version directly from PMFW interface header file rather than keeping another definition in common smu13 file.
Signed-off-by: Lijo
drm/amd/pm: Keep interface version in PMFW header
Use the interface version directly from PMFW interface header file rather than keeping another definition in common smu13 file.
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c1d35412 |
| 20-May-2023 |
Tim Huang <Tim.Huang@amd.com> |
drm/amd/pm: reverse mclk clocks levels for SMU v13.0.5
This patch reverses the DPM clocks levels output of pp_dpm_mclk.
On dGPUs and older APUs we expose the levels from lowest clocks to highest cl
drm/amd/pm: reverse mclk clocks levels for SMU v13.0.5
This patch reverses the DPM clocks levels output of pp_dpm_mclk.
On dGPUs and older APUs we expose the levels from lowest clocks to highest clocks. But for some APUs, the clocks levels that from the DFPstateTable are given the reversed orders by PMFW. Like the memory DPM clocks that are exposed by pp_dpm_mclk.
It's not intuitive that they are reversed on these APUs. All tools and software that talks to the driver then has to know different ways to interpret the data depending on the asic.
So we need to reverse them to expose the clocks levels from the driver consistently.
Signed-off-by: Tim Huang <Tim.Huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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Revision tags: v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59 |
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#
541d54e4 |
| 03-Aug-2022 |
Zhen Ni <nizhen@uniontech.com> |
drm/amd/pm: Fix a potential gpu_metrics_table memory leak
Memory is allocated for gpu_metrics_table in smu_v13_0_5_init_smc_tables(), but not freed in smu_v13_0_5_fini_smc_tables(). This may cause m
drm/amd/pm: Fix a potential gpu_metrics_table memory leak
Memory is allocated for gpu_metrics_table in smu_v13_0_5_init_smc_tables(), but not freed in smu_v13_0_5_fini_smc_tables(). This may cause memory leaks, fix it.
Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Zhen Ni <nizhen@uniontech.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44 |
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#
da1db031 |
| 26-May-2022 |
Alex Deucher <alexander.deucher@amd.com> |
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for accessing the SMU mailboxes without needing a lot of per asic logic in the common
drm/amdgpu/swsmu: add SMU mailbox registers in SMU context
So we can eventaully use them in the common smu code for accessing the SMU mailboxes without needing a lot of per asic logic in the common code.
Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29 |
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#
60d61f4e |
| 15-Mar-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amdgpu/pm: fix the Stable pstate Test in amdgpu_test
If GFX DPM is disbaled, Stable pstate Test in amdgpu_test fails. Check GFX DPM statue before change clock level
Log: [ 46.595274] [drm] In
drm/amdgpu/pm: fix the Stable pstate Test in amdgpu_test
If GFX DPM is disbaled, Stable pstate Test in amdgpu_test fails. Check GFX DPM statue before change clock level
Log: [ 46.595274] [drm] Initialized amdgpu 3.46.0 20150101 for 0000:02:00.0 on minor 0 [ 46.599929] fbcon: amdgpudrmfb (fb0) is primary device [ 46.785753] Console: switching to colour frame buffer device 240x67 [ 46.811765] amdgpu 0000:02:00.0: [drm] fb0: amdgpudrmfb frame buffer device [ 131.398407] amdgpu 0000:02:00.0: amdgpu: Failed to set performance level!
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.28, v5.15.27, v5.15.26, v5.15.25 |
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#
cefbe724 |
| 23-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amd/pm: refine smu 13.0.5 pp table code
Based on smu 13.0.5 features, refine pp table code.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-o
drm/amd/pm: refine smu 13.0.5 pp table code
Based on smu 13.0.5 features, refine pp table code.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0bb319e7 |
| 23-Feb-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amd/pm: fix mode2 reset fail for smu 13.0.5
SMU MSG index should be used as parameter.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Revie
drm/amd/pm: fix mode2 reset fail for smu 13.0.5
SMU MSG index should be used as parameter.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17 |
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#
068ea8bd |
| 21-Jan-2022 |
Yifan Zhang <yifan1.zhang@amd.com> |
drm/amd/pm: add smu_v13_0_5_ppt implementation
this patch adds smu_v13_0_5_ppt implementation.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com
drm/amd/pm: add smu_v13_0_5_ppt implementation
this patch adds smu_v13_0_5_ppt implementation.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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