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Searched refs:SOC15_REG_OFFSET (Results 1 – 25 of 95) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c67 return RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR)); in vce_v4_0_ring_get_rptr()
115 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), in vce_v4_0_ring_set_wptr()
118 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), in vce_v4_0_ring_set_wptr()
121 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), in vce_v4_0_ring_set_wptr()
132 RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS)); in vce_v4_0_firmware_loaded()
140 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_firmware_loaded()
271 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
274 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
277 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, in vce_v4_0_sriov_start()
395 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_stop()
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H A Dnbio_v7_2.c257 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regCPM_CONTROL), data); in nbio_v7_2_update_medium_grain_clock_gating()
276 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); in nbio_v7_2_update_medium_grain_light_sleep()
278 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, in nbio_v7_2_update_medium_grain_light_sleep()
303 WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data); in nbio_v7_2_update_medium_grain_light_sleep()
319 data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2)); in nbio_v7_2_get_clockgating_state()
326 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); in nbio_v7_2_get_hdp_flush_req_offset()
336 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); in nbio_v7_2_get_pcie_index_offset()
341 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); in nbio_v7_2_get_pcie_data_offset()
346 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); in nbio_v7_2_get_pcie_port_index_offset()
351 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); in nbio_v7_2_get_pcie_port_data_offset()
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H A Djpeg_v1_0.c64 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW); in jpeg_v1_0_decode_ring_set_patch_ring()
70 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH); in jpeg_v1_0_decode_ring_set_patch_ring()
82 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
88 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA); in jpeg_v1_0_decode_ring_set_patch_ring()
94 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
121 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_RPTR); in jpeg_v1_0_decode_ring_set_patch_ring()
127 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_CNTL); in jpeg_v1_0_decode_ring_set_patch_ring()
247 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JPEG_GPCOM_CMD), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
313 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
325 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_IB_SIZE), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
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H A Dumc_v6_1.c48 rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0, in umc_v6_1_enable_umc_index_mode()
63 rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0, in umc_v6_1_disable_umc_index_mode()
78 rsmu_umc_addr = SOC15_REG_OFFSET(RSMU, 0, in umc_v6_1_get_umc_index_mode_state()
103 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()
106 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()
111 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()
114 SOC15_REG_OFFSET(UMC, 0, in umc_v6_1_clear_error_count_per_channel()
189 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); in umc_v6_1_query_correctable_error_count()
191 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCnt); in umc_v6_1_query_correctable_error_count()
406 SOC15_REG_OFFSET(UMC, 0, mmUMCCH0_0_EccErrCntSel); in umc_v6_1_err_cnt_init_per_channel()
[all …]
H A Damdgpu_amdkfd_gfx_v9.c123 while (!(RREG32(SOC15_REG_OFFSET( in kgd_gfx_v9_set_pasid_vmid_mapping()
129 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_set_pasid_vmid_mapping()
134 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, in kgd_gfx_v9_set_pasid_vmid_mapping()
140 while (!(RREG32(SOC15_REG_OFFSET( in kgd_gfx_v9_set_pasid_vmid_mapping()
146 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_set_pasid_vmid_mapping()
194 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
198 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
693 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL)); in kgd_gfx_v9_set_wave_launch_stall()
856 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
874 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
[all …]
H A Duvd_v7_0.c551 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
556 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
561 tmp = PACKET0(SOC15_REG_OFFSET(UVD, j, in uvd_v7_0_hw_init()
824 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
827 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, in uvd_v7_0_sriov_start()
977 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
985 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), in uvd_v7_0_start()
1057 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), in uvd_v7_0_start()
1072 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), in uvd_v7_0_start()
1077 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, in uvd_v7_0_start()
[all …]
H A Damdgpu_amdkfd_gfx_v10.c116 while (!(RREG32(SOC15_REG_OFFSET( in kgd_set_pasid_vmid_mapping()
123 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_set_pasid_vmid_mapping()
165 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
173 SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
920 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_set_address_watch()
938 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_set_address_watch()
952 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_clear_address_watch()
1011 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO), in program_trap_handler_settings()
1013 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI), in program_trap_handler_settings()
1020 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO), in program_trap_handler_settings()
[all …]
H A Damdgpu_amdkfd_gc_9_4_3.c48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
242 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
246 while (!(RREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
256 WREG32(SOC15_REG_OFFSET(ATHUB, 0, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
266 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
268 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
270 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_LUT_INDEX), in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
272 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT_MM) + vmid, in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
345 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_hqd_load()
497 WREG32_RLC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_set_address_watch()
[all …]
H A Damdgpu_amdkfd_gfx_v11.c134 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
138 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
195 hqd_base = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_load_v11()
234 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_LO), in hqd_load_v11()
236 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI), in hqd_load_v11()
244 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_PQ_WPTR_POLL_CNTL1), in hqd_load_v11()
249 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_EOP_RPTR), in hqd_load_v11()
254 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data); in hqd_load_v11()
332 for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR); in hqd_dump_v11()
457 act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE)); in hqd_is_occupied_v11()
[all …]
H A Dpsp_v12_0.c87 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sysdrv()
105 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sysdrv()
126 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v12_0_bootloader_load_sos()
143 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v12_0_bootloader_load_sos()
165 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_reroute_ih()
177 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_reroute_ih()
207 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v12_0_ring_create()
229 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_ring_create()
258 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v12_0_ring_stop()
288 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); in psp_v12_0_mode1_reset()
[all …]
H A Dpsp_v3_1.c93 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sysdrv()
111 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sysdrv()
132 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35), in psp_v3_1_bootloader_load_sos()
149 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81), in psp_v3_1_bootloader_load_sos()
170 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_reroute_ih()
182 psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_reroute_ih()
220 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, in psp_v3_1_ring_create()
243 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, in psp_v3_1_ring_create()
273 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v3_1_ring_stop()
312 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64); in psp_v3_1_mode1_reset()
[all …]
H A Dmxgpu_ai.c58 return RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_peek_msg()
68 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_rcv_msg()
140 reg = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_mailbox_trans_msg()
144 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0), in xgpu_ai_mailbox_trans_msg()
146 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1), in xgpu_ai_mailbox_trans_msg()
148 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2), in xgpu_ai_mailbox_trans_msg()
150 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3), in xgpu_ai_mailbox_trans_msg()
182 RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, in xgpu_ai_send_access_requests()
243 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL)); in xgpu_ai_set_mailbox_ack_irq()
247 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp); in xgpu_ai_set_mailbox_ack_irq()
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H A Dvega10_ih.c53 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega10_ih_init_register_offset()
54 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega10_ih_init_register_offset()
55 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega10_ih_init_register_offset()
56 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega10_ih_init_register_offset()
57 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega10_ih_init_register_offset()
66 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega10_ih_init_register_offset()
68 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega10_ih_init_register_offset()
69 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in vega10_ih_init_register_offset()
70 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in vega10_ih_init_register_offset()
77 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in vega10_ih_init_register_offset()
[all …]
H A Damdgpu_amdkfd_arcturus.c82 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
86 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, in get_sdma_rlc_reg_offset()
90 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA2, 0, in get_sdma_rlc_reg_offset()
94 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA3, 0, in get_sdma_rlc_reg_offset()
98 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA4, 0, in get_sdma_rlc_reg_offset()
102 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA5, 0, in get_sdma_rlc_reg_offset()
106 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA6, 0, in get_sdma_rlc_reg_offset()
110 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA7, 0, in get_sdma_rlc_reg_offset()
329 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG)); in set_barrier_auto_waitcnt()
332 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CONFIG), data); in set_barrier_auto_waitcnt()
[all …]
H A Dvega20_ih.c61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in vega20_ih_init_register_offset()
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in vega20_ih_init_register_offset()
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in vega20_ih_init_register_offset()
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in vega20_ih_init_register_offset()
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in vega20_ih_init_register_offset()
74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in vega20_ih_init_register_offset()
76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in vega20_ih_init_register_offset()
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in vega20_ih_init_register_offset()
78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in vega20_ih_init_register_offset()
85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in vega20_ih_init_register_offset()
[all …]
H A Dnavi10_ih.c55 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE); in navi10_ih_init_register_offset()
56 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI); in navi10_ih_init_register_offset()
57 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL); in navi10_ih_init_register_offset()
58 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR); in navi10_ih_init_register_offset()
59 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR); in navi10_ih_init_register_offset()
68 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1); in navi10_ih_init_register_offset()
70 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1); in navi10_ih_init_register_offset()
71 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1); in navi10_ih_init_register_offset()
72 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1); in navi10_ih_init_register_offset()
79 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2); in navi10_ih_init_register_offset()
[all …]
H A Dhdp_v4_0.c59 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v4_0_invalidate_hdp()
99 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_update_clock_gating()
107 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); in hdp_v4_0_update_clock_gating()
109 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); in hdp_v4_0_update_clock_gating()
123 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in hdp_v4_0_update_clock_gating()
133 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in hdp_v4_0_get_clockgating_state()
H A Dumc_v6_7.c74 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_IPIDT0); in umc_v6_7_query_error_status_helper()
81 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_SYNDT0); in umc_v6_7_query_error_status_helper()
88 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_MISC0T0); in umc_v6_7_query_error_status_helper()
274 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCntSel); in umc_v6_7_query_correctable_error_count()
276 SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_EccErrCnt); in umc_v6_7_query_correctable_error_count()
278 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); in umc_v6_7_query_correctable_error_count()
316 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v6_7_query_correctable_error_count()
371 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()
374 SOC15_REG_OFFSET(UMC, 0, in umc_v6_7_reset_error_count_per_channel()
454 SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); in umc_v6_7_query_error_address()
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H A Damdgpu_amdkfd_gfx_v10_3.c143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
210 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in hqd_load_v10_3()
264 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), in hqd_load_v10_3()
598 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); in wave_control_execute_v10_3()
641 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO), in program_trap_handler_settings_v10_3()
643 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI), in program_trap_handler_settings_v10_3()
650 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO), in program_trap_handler_settings_v10_3()
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H A Dnbio_v7_0.c71 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) : in nbio_v7_0_sdma_doorbell_range()
72 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE); in nbio_v7_0_sdma_doorbell_range()
88 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE); in nbio_v7_0_vcn_doorbell_range()
241 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ); in nbio_v7_0_get_hdp_flush_req_offset()
246 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE); in nbio_v7_0_get_hdp_flush_done_offset()
251 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); in nbio_v7_0_get_pcie_index_offset()
256 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); in nbio_v7_0_get_pcie_data_offset()
278 SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2; in nbio_v7_0_init_registers()
H A Dvcn_v2_5.c1239 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start()
1246 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1250 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1258 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1262 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1275 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1279 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1289 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1294 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1321 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
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H A Dpsp_v11_0_8.c44 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_8_ring_stop()
53 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v11_0_8_ring_stop()
90 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101), in psp_v11_0_8_ring_create()
95 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v11_0_8_ring_create()
120 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64), in psp_v11_0_8_ring_create()
H A Dvcn_v2_0.c1884 SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in vcn_v2_0_start_sriov()
1890 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
1894 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
1900 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
1904 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
1918 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
1922 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
1933 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
1938 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
1966 SOC15_REG_OFFSET(UVD, i, in vcn_v2_0_start_sriov()
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H A Dnbio_v7_7.c69 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_CSDMA_DOORBELL_RANGE); in nbio_v7_7_sdma_doorbell_range()
91 u32 reg = SOC15_REG_OFFSET(NBIO, 0, regGDC0_BIF_VCN0_DOORBELL_RANGE); in nbio_v7_7_vcn_doorbell_range()
194 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ); in nbio_v7_7_get_hdp_flush_req_offset()
199 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE); in nbio_v7_7_get_hdp_flush_done_offset()
204 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2); in nbio_v7_7_get_pcie_index_offset()
209 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2); in nbio_v7_7_get_pcie_data_offset()
214 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_INDEX); in nbio_v7_7_get_pcie_port_index_offset()
219 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_RSMU_DATA); in nbio_v7_7_get_pcie_port_data_offset()
H A Dvcn_v1_0.c131 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); in vcn_v1_0_sw_init()
133 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); in vcn_v1_0_sw_init()
135 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); in vcn_v1_0_sw_init()
137 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); in vcn_v1_0_sw_init()
139 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); in vcn_v1_0_sw_init()
898 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v1_0_start_spg_mode()
902 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), in vcn_v1_0_start_spg_mode()
1133 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), in vcn_v1_0_stop_spg_mode()
1146 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
1150 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), in vcn_v1_0_stop_spg_mode()
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