Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71 |
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#
cdbb816b |
| 26-Sep-2022 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: remove check for CE in RAS error address query
Only RAS UE error address is queried currently, no need to check CE status.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawki
drm/amdgpu: remove check for CE in RAS error address query
Only RAS UE error address is queried currently, no need to check CE status.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16 |
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#
400013b2 |
| 19-Jan-2022 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: add umc_fill_error_record to make code more simple
Create common amdgpu_umc_fill_error_record function for all versions of UMC and clean up related codes.
Signed-off-by: Tao Zhou <tao.z
drm/amdgpu: add umc_fill_error_record to make code more simple
Create common amdgpu_umc_fill_error_record function for all versions of UMC and clean up related codes.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.15, v5.16 |
|
#
efe17d5a |
| 06-Jan-2022 |
yipechai <YiPeng.Chai@amd.com> |
drm/amdgpu: Modify umc block to fit for the unified ras block data and ops
1.Modify umc block to fit for the unified ras block data and ops. 2.Change amdgpu_umc_ras_funcs to amdgpu_umc_ras, and the
drm/amdgpu: Modify umc block to fit for the unified ras block data and ops
1.Modify umc block to fit for the unified ras block data and ops. 2.Change amdgpu_umc_ras_funcs to amdgpu_umc_ras, and the corresponding variable name remove _funcs suffix. 3.Remove the const flag of umc ras variable so that umc ras block can be able to be inserted into amdgpu device ras block link list. 4.Invoke amdgpu_ras_register_ras_block function to register umc ras block into amdgpu device ras block link list. 5.Remove the redundant code about umc in amdgpu_ras.c after using the unified ras block. 6.Fill unified ras block .name .block .ras_late_init and .ras_fini for all of umc versions. If .ras_late_init and .ras_fini had been defined by the selected umc version, the defined functions will take effect; if not defined, default fill them with amdgpu_umc_ras_late_init and amdgpu_umc_ras_fini.
Signed-off-by: yipechai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: John Clements <john.clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61, v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24 |
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#
49070c4e |
| 17-Mar-2021 |
Hawking Zhang <Hawking.Zhang@amd.com> |
drm/amdgpu: split umc callbacks to ras and non-ras ones
umc ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split umc callbacks into ras and non-ras ones so gpu driver on
drm/amdgpu: split umc callbacks to ras and non-ras ones
umc ras is not managed by gpu driver when gpu is connected to cpu through xgmi. split umc callbacks into ras and non-ras ones so gpu driver only initializes umc ras callbacks when it manages umc ras.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10 |
|
#
58b5a793 |
| 02-Nov-2020 |
Deepak R Varma <mh12gx2825@gmail.com> |
drm/amdgpu/umc: use "*" adjacent to data name
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reporte
drm/amdgpu/umc: use "*" adjacent to data name
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)"
Signed-off-by: Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54 |
|
#
c5a4ef3e |
| 23-Jul-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: move umc specific macros to header
certain umc macros are common across umc versions
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.c
drm/amdgpu: move umc specific macros to header
certain umc macros are common across umc versions
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36 |
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#
fd90456c |
| 26-Apr-2020 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: decouple EccErrCnt query and clear operation
Due to hardware bug that when RSMU UMC index is disabled, clear EccErrCnt at the first UMC instance will clean up all other EccErrCnt registe
drm/amdgpu: decouple EccErrCnt query and clear operation
Due to hardware bug that when RSMU UMC index is disabled, clear EccErrCnt at the first UMC instance will clean up all other EccErrCnt registes from other instances at the same time. This will break the correctable error count log in EccErrCnt register once querying it. So decouple both to make error count query workable.
Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
40e73314 |
| 26-Apr-2020 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: switch to SMN interface to operate RSMU index mode
This makes consistent with other regsiters' access in this module.
Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Tao Z
drm/amdgpu: switch to SMN interface to operate RSMU index mode
This makes consistent with other regsiters' access in this module.
Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28, v5.4.27, v5.4.26, v5.4.25, v5.4.24 |
|
#
1a2172b5 |
| 05-Mar-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: update page retirement sequence
check UMC status and exit prior to making and erroneus register access
this resolved unexpected behaviour with UMC indexing mode broadcasting writes
Rev
drm/amdgpu: update page retirement sequence
check UMC status and exit prior to making and erroneus register access
this resolved unexpected behaviour with UMC indexing mode broadcasting writes
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
d38c3ac7 |
| 04-Mar-2020 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: toggle DF-Cstate when accessing UMC ras error related registers
On arcturus, DF-Cstate needs to be toggled off/on before and after accessing UMC error counter and error address registers
drm/amdgpu: toggle DF-Cstate when accessing UMC ras error related registers
On arcturus, DF-Cstate needs to be toggled off/on before and after accessing UMC error counter and error address registers, otherwise, clearing such registers may fail.
Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: John Clements <John.Clements@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11 |
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#
eee2eaba |
| 10-Jan-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: preserve RSMU UMC index mode state
between UMC RAS err register access restore previous RSMU UMC index mode state
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John
drm/amdgpu: preserve RSMU UMC index mode state
between UMC RAS err register access restore previous RSMU UMC index mode state
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.10, v5.4.9 |
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#
5d4667ec |
| 07-Jan-2020 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: calculate MCUMC_ADDRT0 per asic's UMC offset
Hardcoded offset is not friendly. And another benifit of this patch is to keep read and write access to this register be consistent with othe
drm/amdgpu: calculate MCUMC_ADDRT0 per asic's UMC offset
Hardcoded offset is not friendly. And another benifit of this patch is to keep read and write access to this register be consistent with other similar UMC regsiters in this file.
Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
c8aa6ae3 |
| 07-Jan-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: updated UMC error address record with correct channel index
defined macros for repetitive for loops
Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: John Clements <john.cle
drm/amdgpu: updated UMC error address record with correct channel index
defined macros for repetitive for loops
Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
0ee51f1d |
| 07-Jan-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: resolved bug in UMC RAS CE query
switch CE counter register access' to use SMN
disable UMC indexing mode
Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: John Clements <john.cl
drm/amdgpu: resolved bug in UMC RAS CE query
switch CE counter register access' to use SMN
disable UMC indexing mode
Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.8 |
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#
bd68fb94 |
| 02-Jan-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: resolve bug in UMC 6 error counter query
iterate over all error counter registers in SMN space
removed support error counter access via MMIO
Reviewed-by: Guchun Chen <guchun.chen@amd.c
drm/amdgpu: resolve bug in UMC 6 error counter query
iterate over all error counter registers in SMN space
removed support error counter access via MMIO
Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
955c7120 |
| 01-Jan-2020 |
John Clements <john.clements@amd.com> |
drm/amdgpu: update UMC 6.1 RAS error counter register access path
use proper method for SMN register access
Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: John Clements <john.clements@amd
drm/amdgpu: update UMC 6.1 RAS error counter register access path
use proper method for SMN register access
Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.7, v5.4.6, v5.4.5, v5.4.4 |
|
#
fb71a336 |
| 17-Dec-2019 |
Guchun Chen <guchun.chen@amd.com> |
drm/amdgpu: move umc offset to one new header file for Arcturus
Code refactor and no functional change.
Fixes: 4cf781c24c3b ("drm/amdgpu: Added RAS UMC error query support for Arcturus") Signed-off
drm/amdgpu: move umc offset to one new header file for Arcturus
Code refactor and no functional change.
Fixes: 4cf781c24c3b ("drm/amdgpu: Added RAS UMC error query support for Arcturus") Signed-off-by: Guchun Chen <guchun.chen@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.4.3 |
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#
4cf781c2 |
| 10-Dec-2019 |
John Clements <john.clements@amd.com> |
drm/amdgpu: Added RAS UMC error query support for Arcturus
Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: J
drm/amdgpu: Added RAS UMC error query support for Arcturus
Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1 |
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#
afa44809 |
| 16-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: use GPU PAGE SHIFT for umc retired page
umc retired page belongs to vram and it should be aligned to gpu page size
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <
drm/amdgpu: use GPU PAGE SHIFT for umc retired page
umc retired page belongs to vram and it should be aligned to gpu page size
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12 |
|
#
d99659a0 |
| 06-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: rename umc ras_init to err_cnt_init
this interface is related to specific version of umc, distinguish it from ras_late_init
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guch
drm/amdgpu: rename umc ras_init to err_cnt_init
this interface is related to specific version of umc, distinguish it from ras_late_init
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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#
86edcc7d |
| 05-Sep-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: move umc late init from gmc to umc block
umc late init is umc specific, it's more suitable to be put in umc block
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <g
drm/amdgpu: move umc late init from gmc to umc block
umc late init is umc specific, it's more suitable to be put in umc block
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.11, v5.2.10, v5.2.9 |
|
#
87d2b92f |
| 15-Aug-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: save umc error records
save umc error records to ras bad page array
v2: add bad pages before gpu reset v3: add NULL check for adev->umc.funcs
Signed-off-by: Tao Zhou <tao.zhou1@amd.com
drm/amdgpu: save umc error records
save umc error records to ras bad page array
v2: add bad pages before gpu reset v3: add NULL check for adev->umc.funcs
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.8 |
|
#
dd21a572 |
| 09-Aug-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: implement UMC 64 bits REG operations
implement 64 bits operations via 32 bits interface
v2: make use of lower_32_bits() and upper_32_bits() macros
Reviewed-by: Christian König <christi
drm/amdgpu: implement UMC 64 bits REG operations
implement 64 bits operations via 32 bits interface
v2: make use of lower_32_bits() and upper_32_bits() macros
Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Revision tags: v5.2.7, v5.2.6, v5.2.5 |
|
#
b1a58953 |
| 29-Jul-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: update the calc algorithm of umc ecc error count
the initial value of ecc error count can be adjusted
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zha
drm/amdgpu: update the calc algorithm of umc ecc error count
the initial value of ecc error count can be adjusted
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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b7f92097 |
| 29-Jul-2019 |
Tao Zhou <tao.zhou1@amd.com> |
drm/amdgpu: implement umc ras init function
enable umc ce interrupt and initialize ecc error count
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Rev
drm/amdgpu: implement umc ras init function
enable umc ce interrupt and initialize ecc error count
Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
show more ...
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