16a7a0bdbSAaron Liu /*
26a7a0bdbSAaron Liu * Copyright 2019 Advanced Micro Devices, Inc.
36a7a0bdbSAaron Liu *
46a7a0bdbSAaron Liu * Permission is hereby granted, free of charge, to any person obtaining a
56a7a0bdbSAaron Liu * copy of this software and associated documentation files (the "Software"),
66a7a0bdbSAaron Liu * to deal in the Software without restriction, including without limitation
76a7a0bdbSAaron Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense,
86a7a0bdbSAaron Liu * and/or sell copies of the Software, and to permit persons to whom the
96a7a0bdbSAaron Liu * Software is furnished to do so, subject to the following conditions:
106a7a0bdbSAaron Liu *
116a7a0bdbSAaron Liu * The above copyright notice and this permission notice shall be included in
126a7a0bdbSAaron Liu * all copies or substantial portions of the Software.
136a7a0bdbSAaron Liu *
146a7a0bdbSAaron Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
156a7a0bdbSAaron Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
166a7a0bdbSAaron Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
176a7a0bdbSAaron Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
186a7a0bdbSAaron Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
196a7a0bdbSAaron Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
206a7a0bdbSAaron Liu * OTHER DEALINGS IN THE SOFTWARE.
216a7a0bdbSAaron Liu */
226a7a0bdbSAaron Liu
236a7a0bdbSAaron Liu #include <linux/firmware.h>
242568cedcSStephen Rothwell #include <linux/module.h>
256a7a0bdbSAaron Liu #include "amdgpu.h"
266a7a0bdbSAaron Liu #include "amdgpu_psp.h"
276a7a0bdbSAaron Liu #include "amdgpu_ucode.h"
286a7a0bdbSAaron Liu #include "soc15_common.h"
296a7a0bdbSAaron Liu #include "psp_v12_0.h"
306a7a0bdbSAaron Liu
316a7a0bdbSAaron Liu #include "mp/mp_12_0_0_offset.h"
326a7a0bdbSAaron Liu #include "mp/mp_12_0_0_sh_mask.h"
336a7a0bdbSAaron Liu #include "gc/gc_9_0_offset.h"
346a7a0bdbSAaron Liu #include "sdma0/sdma0_4_0_offset.h"
356a7a0bdbSAaron Liu #include "nbio/nbio_7_4_offset.h"
366a7a0bdbSAaron Liu
376a7a0bdbSAaron Liu #include "oss/osssys_4_0_offset.h"
386a7a0bdbSAaron Liu #include "oss/osssys_4_0_sh_mask.h"
396a7a0bdbSAaron Liu
406a7a0bdbSAaron Liu MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
416627d1c1SChangfeng MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
4268697982SAaron Liu MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
4326642192SRoman Li MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
446627d1c1SChangfeng
456a7a0bdbSAaron Liu /* address block */
466a7a0bdbSAaron Liu #define smnMP1_FIRMWARE_FLAGS 0x3010024
476a7a0bdbSAaron Liu
psp_v12_0_init_microcode(struct psp_context * psp)486a7a0bdbSAaron Liu static int psp_v12_0_init_microcode(struct psp_context *psp)
496a7a0bdbSAaron Liu {
506a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev;
51994a9744SMario Limonciello char ucode_prefix[30];
526a7a0bdbSAaron Liu int err = 0;
536627d1c1SChangfeng DRM_DEBUG("\n");
546a7a0bdbSAaron Liu
55994a9744SMario Limonciello amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
566a7a0bdbSAaron Liu
57*2d39c7aeSMario Limonciello err = psp_init_asd_microcode(psp, ucode_prefix);
586627d1c1SChangfeng if (err)
5936f5f9d3SJiri Kosina return err;
606627d1c1SChangfeng
61994a9744SMario Limonciello err = psp_init_ta_microcode(psp, ucode_prefix);
626627d1c1SChangfeng if (err)
63994a9744SMario Limonciello return err;
646627d1c1SChangfeng
65994a9744SMario Limonciello /* only supported on renoir */
66994a9744SMario Limonciello if (!(adev->apu_flags & AMD_APU_IS_RENOIR))
67994a9744SMario Limonciello adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
686627d1c1SChangfeng
696627d1c1SChangfeng return 0;
706a7a0bdbSAaron Liu }
716a7a0bdbSAaron Liu
psp_v12_0_bootloader_load_sysdrv(struct psp_context * psp)726a7a0bdbSAaron Liu static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
736a7a0bdbSAaron Liu {
746a7a0bdbSAaron Liu int ret;
756a7a0bdbSAaron Liu uint32_t psp_gfxdrv_command_reg = 0;
766a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev;
776a7a0bdbSAaron Liu uint32_t sol_reg;
786a7a0bdbSAaron Liu
796a7a0bdbSAaron Liu /* Check sOS sign of life register to confirm sys driver and sOS
806a7a0bdbSAaron Liu * are already been loaded.
816a7a0bdbSAaron Liu */
826a7a0bdbSAaron Liu sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
83d4d27897SHawking Zhang if (sol_reg)
846a7a0bdbSAaron Liu return 0;
856a7a0bdbSAaron Liu
866a7a0bdbSAaron Liu /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
876a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
886a7a0bdbSAaron Liu 0x80000000, 0x80000000, false);
896a7a0bdbSAaron Liu if (ret)
906a7a0bdbSAaron Liu return ret;
916a7a0bdbSAaron Liu
926a7a0bdbSAaron Liu /* Copy PSP System Driver binary to memory */
93222e0a71SCandice Li psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
946a7a0bdbSAaron Liu
956a7a0bdbSAaron Liu /* Provide the sys driver to bootloader */
966a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
976a7a0bdbSAaron Liu (uint32_t)(psp->fw_pri_mc_addr >> 20));
986a7a0bdbSAaron Liu psp_gfxdrv_command_reg = 1 << 16;
996a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
1006a7a0bdbSAaron Liu psp_gfxdrv_command_reg);
1016a7a0bdbSAaron Liu
1026a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */
1036a7a0bdbSAaron Liu mdelay(20);
1046a7a0bdbSAaron Liu
1056a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
1066a7a0bdbSAaron Liu 0x80000000, 0x80000000, false);
1076a7a0bdbSAaron Liu
1086a7a0bdbSAaron Liu return ret;
1096a7a0bdbSAaron Liu }
1106a7a0bdbSAaron Liu
psp_v12_0_bootloader_load_sos(struct psp_context * psp)1116a7a0bdbSAaron Liu static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
1126a7a0bdbSAaron Liu {
1136a7a0bdbSAaron Liu int ret;
1146a7a0bdbSAaron Liu unsigned int psp_gfxdrv_command_reg = 0;
1156a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev;
1166a7a0bdbSAaron Liu uint32_t sol_reg;
1176a7a0bdbSAaron Liu
1186a7a0bdbSAaron Liu /* Check sOS sign of life register to confirm sys driver and sOS
1196a7a0bdbSAaron Liu * are already been loaded.
1206a7a0bdbSAaron Liu */
1216a7a0bdbSAaron Liu sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
1226a7a0bdbSAaron Liu if (sol_reg)
1236a7a0bdbSAaron Liu return 0;
1246a7a0bdbSAaron Liu
1256a7a0bdbSAaron Liu /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
1266a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
1276a7a0bdbSAaron Liu 0x80000000, 0x80000000, false);
1286a7a0bdbSAaron Liu if (ret)
1296a7a0bdbSAaron Liu return ret;
1306a7a0bdbSAaron Liu
1316a7a0bdbSAaron Liu /* Copy Secure OS binary to PSP memory */
132222e0a71SCandice Li psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
1336a7a0bdbSAaron Liu
1346a7a0bdbSAaron Liu /* Provide the PSP secure OS to bootloader */
1356a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
1366a7a0bdbSAaron Liu (uint32_t)(psp->fw_pri_mc_addr >> 20));
1376a7a0bdbSAaron Liu psp_gfxdrv_command_reg = 2 << 16;
1386a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
1396a7a0bdbSAaron Liu psp_gfxdrv_command_reg);
1406a7a0bdbSAaron Liu
1416a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */
1426a7a0bdbSAaron Liu mdelay(20);
1436a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
1446a7a0bdbSAaron Liu RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
1456a7a0bdbSAaron Liu 0, true);
1466a7a0bdbSAaron Liu
1476a7a0bdbSAaron Liu return ret;
1486a7a0bdbSAaron Liu }
1496a7a0bdbSAaron Liu
psp_v12_0_reroute_ih(struct psp_context * psp)1506a7a0bdbSAaron Liu static void psp_v12_0_reroute_ih(struct psp_context *psp)
1516a7a0bdbSAaron Liu {
1526a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev;
1536a7a0bdbSAaron Liu uint32_t tmp;
1546a7a0bdbSAaron Liu
1556a7a0bdbSAaron Liu /* Change IH ring for VMC */
1566a7a0bdbSAaron Liu tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
1576a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
1586a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
1596a7a0bdbSAaron Liu
1606a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
1616a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
1626a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
1636a7a0bdbSAaron Liu
1646a7a0bdbSAaron Liu mdelay(20);
1656a7a0bdbSAaron Liu psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
1666a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false);
1676a7a0bdbSAaron Liu
1686a7a0bdbSAaron Liu /* Change IH ring for UMC */
1696a7a0bdbSAaron Liu tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
1706a7a0bdbSAaron Liu tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
1716a7a0bdbSAaron Liu
1726a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
1736a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
1746a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
1756a7a0bdbSAaron Liu
1766a7a0bdbSAaron Liu mdelay(20);
1776a7a0bdbSAaron Liu psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
1786a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false);
1796a7a0bdbSAaron Liu }
1806a7a0bdbSAaron Liu
psp_v12_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)1816a7a0bdbSAaron Liu static int psp_v12_0_ring_create(struct psp_context *psp,
1826a7a0bdbSAaron Liu enum psp_ring_type ring_type)
1836a7a0bdbSAaron Liu {
1846a7a0bdbSAaron Liu int ret = 0;
1856a7a0bdbSAaron Liu unsigned int psp_ring_reg = 0;
1866a7a0bdbSAaron Liu struct psp_ring *ring = &psp->km_ring;
1876a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev;
1886a7a0bdbSAaron Liu
18954037bdfSAlex Deucher psp_v12_0_reroute_ih(psp);
19054037bdfSAlex Deucher
191a2676149SHawking Zhang if (amdgpu_sriov_vf(psp->adev)) {
1926a7a0bdbSAaron Liu /* Write low address of the ring to C2PMSG_102 */
1936a7a0bdbSAaron Liu psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
1946a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
1956a7a0bdbSAaron Liu /* Write high address of the ring to C2PMSG_103 */
1966a7a0bdbSAaron Liu psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
1976a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
1986a7a0bdbSAaron Liu
1996a7a0bdbSAaron Liu /* Write the ring initialization command to C2PMSG_101 */
2006a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
2016a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
2026a7a0bdbSAaron Liu
2036a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */
2046a7a0bdbSAaron Liu mdelay(20);
2056a7a0bdbSAaron Liu
2066a7a0bdbSAaron Liu /* Wait for response flag (bit 31) in C2PMSG_101 */
2076a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
2086a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false);
2096a7a0bdbSAaron Liu
2106a7a0bdbSAaron Liu } else {
2116a7a0bdbSAaron Liu /* Write low address of the ring to C2PMSG_69 */
2126a7a0bdbSAaron Liu psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
2136a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
2146a7a0bdbSAaron Liu /* Write high address of the ring to C2PMSG_70 */
2156a7a0bdbSAaron Liu psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
2166a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
2176a7a0bdbSAaron Liu /* Write size of ring to C2PMSG_71 */
2186a7a0bdbSAaron Liu psp_ring_reg = ring->ring_size;
2196a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
2206a7a0bdbSAaron Liu /* Write the ring initialization command to C2PMSG_64 */
2216a7a0bdbSAaron Liu psp_ring_reg = ring_type;
2226a7a0bdbSAaron Liu psp_ring_reg = psp_ring_reg << 16;
2236a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
2246a7a0bdbSAaron Liu
2256a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */
2266a7a0bdbSAaron Liu mdelay(20);
2276a7a0bdbSAaron Liu
2286a7a0bdbSAaron Liu /* Wait for response flag (bit 31) in C2PMSG_64 */
2296a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
2306a7a0bdbSAaron Liu 0x80000000, 0x8000FFFF, false);
2316a7a0bdbSAaron Liu }
2326a7a0bdbSAaron Liu
2336a7a0bdbSAaron Liu return ret;
2346a7a0bdbSAaron Liu }
2356a7a0bdbSAaron Liu
psp_v12_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)2366a7a0bdbSAaron Liu static int psp_v12_0_ring_stop(struct psp_context *psp,
2376a7a0bdbSAaron Liu enum psp_ring_type ring_type)
2386a7a0bdbSAaron Liu {
2396a7a0bdbSAaron Liu int ret = 0;
2406a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev;
2416a7a0bdbSAaron Liu
2426a7a0bdbSAaron Liu /* Write the ring destroy command*/
243a2676149SHawking Zhang if (amdgpu_sriov_vf(adev))
2446a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
2456a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
2466a7a0bdbSAaron Liu else
2476a7a0bdbSAaron Liu WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
2486a7a0bdbSAaron Liu GFX_CTRL_CMD_ID_DESTROY_RINGS);
2496a7a0bdbSAaron Liu
2506a7a0bdbSAaron Liu /* there might be handshake issue with hardware which needs delay */
2516a7a0bdbSAaron Liu mdelay(20);
2526a7a0bdbSAaron Liu
2536a7a0bdbSAaron Liu /* Wait for response flag (bit 31) */
254a2676149SHawking Zhang if (amdgpu_sriov_vf(adev))
2556a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
2566a7a0bdbSAaron Liu 0x80000000, 0x80000000, false);
2576a7a0bdbSAaron Liu else
2586a7a0bdbSAaron Liu ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
2596a7a0bdbSAaron Liu 0x80000000, 0x80000000, false);
2606a7a0bdbSAaron Liu
2616a7a0bdbSAaron Liu return ret;
2626a7a0bdbSAaron Liu }
2636a7a0bdbSAaron Liu
psp_v12_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)2646a7a0bdbSAaron Liu static int psp_v12_0_ring_destroy(struct psp_context *psp,
2656a7a0bdbSAaron Liu enum psp_ring_type ring_type)
2666a7a0bdbSAaron Liu {
2676a7a0bdbSAaron Liu int ret = 0;
2686a7a0bdbSAaron Liu struct psp_ring *ring = &psp->km_ring;
2696a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev;
2706a7a0bdbSAaron Liu
2716a7a0bdbSAaron Liu ret = psp_v12_0_ring_stop(psp, ring_type);
2726a7a0bdbSAaron Liu if (ret)
2736a7a0bdbSAaron Liu DRM_ERROR("Fail to stop psp ring\n");
2746a7a0bdbSAaron Liu
2756a7a0bdbSAaron Liu amdgpu_bo_free_kernel(&adev->firmware.rbuf,
2766a7a0bdbSAaron Liu &ring->ring_mem_mc_addr,
2776a7a0bdbSAaron Liu (void **)&ring->ring_mem);
2786a7a0bdbSAaron Liu
2796a7a0bdbSAaron Liu return ret;
2806a7a0bdbSAaron Liu }
2816a7a0bdbSAaron Liu
psp_v12_0_mode1_reset(struct psp_context * psp)2826a7a0bdbSAaron Liu static int psp_v12_0_mode1_reset(struct psp_context *psp)
2836a7a0bdbSAaron Liu {
2846a7a0bdbSAaron Liu int ret;
2856a7a0bdbSAaron Liu uint32_t offset;
2866a7a0bdbSAaron Liu struct amdgpu_device *adev = psp->adev;
2876a7a0bdbSAaron Liu
2886a7a0bdbSAaron Liu offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
2896a7a0bdbSAaron Liu
2906a7a0bdbSAaron Liu ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
2916a7a0bdbSAaron Liu
2926a7a0bdbSAaron Liu if (ret) {
2936a7a0bdbSAaron Liu DRM_INFO("psp is not working correctly before mode1 reset!\n");
2946a7a0bdbSAaron Liu return -EINVAL;
2956a7a0bdbSAaron Liu }
2966a7a0bdbSAaron Liu
2976a7a0bdbSAaron Liu /*send the mode 1 reset command*/
2986a7a0bdbSAaron Liu WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
2996a7a0bdbSAaron Liu
3006a7a0bdbSAaron Liu msleep(500);
3016a7a0bdbSAaron Liu
3026a7a0bdbSAaron Liu offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
3036a7a0bdbSAaron Liu
3046a7a0bdbSAaron Liu ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
3056a7a0bdbSAaron Liu
3066a7a0bdbSAaron Liu if (ret) {
3076a7a0bdbSAaron Liu DRM_INFO("psp mode 1 reset failed!\n");
3086a7a0bdbSAaron Liu return -EINVAL;
3096a7a0bdbSAaron Liu }
3106a7a0bdbSAaron Liu
3116a7a0bdbSAaron Liu DRM_INFO("psp mode1 reset succeed \n");
3126a7a0bdbSAaron Liu
3136a7a0bdbSAaron Liu return 0;
3146a7a0bdbSAaron Liu }
3156a7a0bdbSAaron Liu
psp_v12_0_ring_get_wptr(struct psp_context * psp)31613a390a6SHawking Zhang static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
31713a390a6SHawking Zhang {
31813a390a6SHawking Zhang uint32_t data;
31913a390a6SHawking Zhang struct amdgpu_device *adev = psp->adev;
32013a390a6SHawking Zhang
321a2676149SHawking Zhang if (amdgpu_sriov_vf(adev))
32213a390a6SHawking Zhang data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
32313a390a6SHawking Zhang else
32413a390a6SHawking Zhang data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
32513a390a6SHawking Zhang
32613a390a6SHawking Zhang return data;
32713a390a6SHawking Zhang }
32813a390a6SHawking Zhang
psp_v12_0_ring_set_wptr(struct psp_context * psp,uint32_t value)32913a390a6SHawking Zhang static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
33013a390a6SHawking Zhang {
33113a390a6SHawking Zhang struct amdgpu_device *adev = psp->adev;
33213a390a6SHawking Zhang
333a2676149SHawking Zhang if (amdgpu_sriov_vf(adev)) {
33413a390a6SHawking Zhang WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
33513a390a6SHawking Zhang WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
33613a390a6SHawking Zhang } else
33713a390a6SHawking Zhang WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
33813a390a6SHawking Zhang }
33913a390a6SHawking Zhang
3406a7a0bdbSAaron Liu static const struct psp_funcs psp_v12_0_funcs = {
3416a7a0bdbSAaron Liu .init_microcode = psp_v12_0_init_microcode,
3426a7a0bdbSAaron Liu .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
3436a7a0bdbSAaron Liu .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
3446a7a0bdbSAaron Liu .ring_create = psp_v12_0_ring_create,
3456a7a0bdbSAaron Liu .ring_stop = psp_v12_0_ring_stop,
3466a7a0bdbSAaron Liu .ring_destroy = psp_v12_0_ring_destroy,
3476a7a0bdbSAaron Liu .mode1_reset = psp_v12_0_mode1_reset,
34813a390a6SHawking Zhang .ring_get_wptr = psp_v12_0_ring_get_wptr,
34913a390a6SHawking Zhang .ring_set_wptr = psp_v12_0_ring_set_wptr,
3506a7a0bdbSAaron Liu };
3516a7a0bdbSAaron Liu
psp_v12_0_set_psp_funcs(struct psp_context * psp)3526a7a0bdbSAaron Liu void psp_v12_0_set_psp_funcs(struct psp_context *psp)
3536a7a0bdbSAaron Liu {
3546a7a0bdbSAaron Liu psp->funcs = &psp_v12_0_funcs;
3556a7a0bdbSAaron Liu }
356