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Searched refs:PPC_BIT (Results 1 – 25 of 49) sorted by relevance

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/openbmc/qemu/include/hw/i2c/
H A Dpnv_i2c_regs.h18 #define I2C_CMD_WITH_START PPC_BIT(0)
19 #define I2C_CMD_WITH_ADDR PPC_BIT(1)
20 #define I2C_CMD_READ_CONT PPC_BIT(2)
21 #define I2C_CMD_WITH_STOP PPC_BIT(3)
26 #define I2C_CMD_READ_NOT_WRITE PPC_BIT(15)
34 #define I2C_MODE_ENHANCED PPC_BIT(28)
35 #define I2C_MODE_DIAGNOSTIC PPC_BIT(29)
36 #define I2C_MODE_PACING_ALLOW PPC_BIT(30)
37 #define I2C_MODE_WRAP PPC_BIT(31)
82 #define I2C_STAT_INVALID_CMD PPC_BIT(0)
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/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb4_regs.h150 #define PHB_CA_ENABLE PPC_BIT(0)
164 #define PHB_PHB4C_32BIT_MSI_EN PPC_BIT(8)
167 #define PHB_RTT_BAR_ENABLE PPC_BIT(0)
170 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0)
174 #define PHB_PEST_BAR_ENABLE PPC_BIT(0)
184 #define PHB_DMARD_SYNC_START PPC_BIT(0)
185 #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1)
187 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0)
190 #define PHB_TCE_KILL_ALL PPC_BIT(0)
191 #define PHB_TCE_KILL_PE PPC_BIT(1)
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H A Dpnv_phb3_regs.h31 #define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0)
32 #define PBCQ_NEST_BAR_EN_MMIO1 PPC_BIT(1)
33 #define PBCQ_NEST_BAR_EN_PHB PPC_BIT(2)
34 #define PBCQ_NEST_BAR_EN_IRSN_RX PPC_BIT(3)
35 #define PBCQ_NEST_BAR_EN_IRSN_TX PPC_BIT(4)
55 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27)
56 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28)
57 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29)
59 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27)
63 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0)
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/openbmc/qemu/hw/intc/
H A Dpnv_xive_regs.h25 #define CQ_IC_BAR_VALID PPC_BIT(0)
26 #define CQ_IC_BAR_64K PPC_BIT(1)
29 #define CQ_TM_BAR_VALID PPC_BIT(0)
30 #define CQ_TM_BAR_64K PPC_BIT(1)
32 #define CQ_PC_BAR_VALID PPC_BIT(0)
36 #define CQ_VC_BAR_VALID PPC_BIT(0)
40 #define CQ_TAR_TBL_AUTOINC PPC_BIT(0)
42 #define CQ_TAR_TSEL_BLK PPC_BIT(12)
48 #define CQ_TDR_VDT_VALID PPC_BIT(0)
58 #define CQ_PBI_PC_64K PPC_BIT(5)
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H A Dpnv_xive2_regs.h33 #define CQ_XIVE_CAP_VP_SAVE_RESTORE PPC_BIT(38)
35 #define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
36 #define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
37 #define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
38 #define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
61 #define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16)
75 #define CQ_IC_BAR_VALID PPC_BIT(0)
76 #define CQ_IC_BAR_64K PPC_BIT(1)
84 #define CQ_TM_BAR_VALID PPC_BIT(0)
85 #define CQ_TM_BAR_64K PPC_BIT(1)
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H A Dspapr_xive.c928 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
929 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
930 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
932 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
1043 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
1044 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
1316 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1487 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1677 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
/openbmc/qemu/include/hw/ssi/
H A Dpnv_spi_regs.h19 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
35 #define SPI_CTR_CFG_N1_CTRL_B1 PPC_BIT(49)
36 #define SPI_CTR_CFG_N1_CTRL_B2 PPC_BIT(50)
37 #define SPI_CTR_CFG_N1_CTRL_B3 PPC_BIT(51)
38 #define SPI_CTR_CFG_N2_CTRL_B0 PPC_BIT(52)
39 #define SPI_CTR_CFG_N2_CTRL_B1 PPC_BIT(53)
40 #define SPI_CTR_CFG_N2_CTRL_B2 PPC_BIT(54)
41 #define SPI_CTR_CFG_N2_CTRL_B3 PPC_BIT(55)
69 #define SPI_STS_RDR_FULL PPC_BIT(0)
70 #define SPI_STS_RDR_OVERRUN PPC_BIT(1)
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/openbmc/linux/arch/powerpc/platforms/powernv/
H A Dvas.h121 #define VAS_XLATE_MSR_DR PPC_BIT(0)
122 #define VAS_XLATE_MSR_TA PPC_BIT(1)
123 #define VAS_XLATE_MSR_PR PPC_BIT(2)
124 #define VAS_XLATE_MSR_US PPC_BIT(3)
125 #define VAS_XLATE_MSR_HV PPC_BIT(4)
126 #define VAS_XLATE_MSR_SF PPC_BIT(5)
168 #define VAS_XTRA_WRITE PPC_BIT(2)
199 #define VAS_WINCTL_OPEN PPC_BIT(0)
201 #define VAS_WINCTL_PIN PPC_BIT(2)
212 #define VAS_WIN_BUSY PPC_BIT(1)
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/openbmc/qemu/target/ppc/
H A Dcpu.h46 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
568 #define CTRL_RUN PPC_BIT(63)
572 #define BESCR_GE PPC_BIT(0)
574 #define BESCR_EE PPC_BIT(30)
576 #define BESCR_PME PPC_BIT(31)
578 #define BESCR_EEO PPC_BIT(62)
580 #define BESCR_PMEO PPC_BIT(63)
584 #define LPCR_VPM0 PPC_BIT(0)
585 #define LPCR_VPM1 PPC_BIT(1)
586 #define LPCR_ISL PPC_BIT(2)
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H A Dexcp_helper.c1280 if (!(env->error_code & PPC_BIT(42))) { in is_prefix_insn_excp()
1369 msr |= PPC_BIT(34); in powerpc_excp_books()
3119 error_code = PPC_BIT(33); in helper_book3s_trace()
3172 env->spr[SPR_DSISR] = PPC_BIT(57); in ppc_cpu_do_transaction_failed()
3173 env->error_code = PPC_BIT(42); in ppc_cpu_do_transaction_failed()
3181 env->error_code = PPC_BIT(36) | PPC_BIT(43) | PPC_BIT(45); in ppc_cpu_do_transaction_failed()
3182 env->error_code |= PPC_BIT(42); in ppc_cpu_do_transaction_failed()
3189 env->error_code = PPC_BIT(36) | PPC_BIT(44) | PPC_BIT(45); in ppc_cpu_do_transaction_failed()
3214 env->spr[SPR_DSISR] = PPC_BIT(41); in ppc_cpu_debug_excp_handler()
3221 PPC_BIT(33) | PPC_BIT(43)); in ppc_cpu_debug_excp_handler()
/openbmc/qemu/hw/ppc/
H A Dpnv_psi.c594 #define PSIHB9_IRQ_METHOD PPC_BIT(0)
595 #define PSIHB9_IRQ_RESET PPC_BIT(1)
606 #define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0)
607 #define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1)
608 #define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2)
609 #define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3)
610 #define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4)
611 #define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5)
612 #define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6)
613 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7)
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H A Dpnv_chiptod.c121 val |= PPC_BIT(20); /* Is running */ in pnv_chiptod_xscom_read()
127 val |= PPC_BIT(23); /* Is active master */ in pnv_chiptod_xscom_read()
145 val |= PPC_BIT(4); in pnv_chiptod_xscom_read()
237 if (val & PPC_BIT(35)) { /* SCOM addressing */ in chiptod_power9_tx_ttype_target()
262 if (val & PPC_BIT(35)) { /* SCOM addressing */ in chiptod_power10_tx_ttype_target()
299 val |= PPC_BIT(1); /* TOD is master */ in pnv_chiptod_xscom_write()
301 val &= ~PPC_BIT(1); in pnv_chiptod_xscom_write()
327 if (!(val & PPC_BIT(0))) { in pnv_chiptod_xscom_write()
341 if (val & PPC_BIT(63)) { in pnv_chiptod_xscom_write()
359 } else if (!(val & PPC_BIT(0))) { in pnv_chiptod_xscom_write()
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H A Dpnv_sbe.c61 #define HOST_SBE_MSG_WAITING PPC_BIT(0)
67 #define SBE_HOST_RESPONSE_WAITING PPC_BIT(0)
68 #define SBE_HOST_MSG_READ PPC_BIT(1)
69 #define SBE_HOST_STOP15_EXIT PPC_BIT(2)
70 #define SBE_HOST_RESET PPC_BIT(3)
71 #define SBE_HOST_PASSTHROUGH PPC_BIT(4)
72 #define SBE_HOST_TIMER_EXPIRY PPC_BIT(14)
80 #define SBE_CONTROL_REG_S0 PPC_BIT(14)
81 #define SBE_CONTROL_REG_S1 PPC_BIT(15)
H A Dpnv_core.c63 env->spr[SPR_PVR] &= ~PPC_BIT(51); in pnv_core_cpu_reset()
208 val |= PPC_BIT(56 + i); in pnv_core_power10_xscom_read()
212 val |= PPC_BIT(62); in pnv_core_power10_xscom_read()
222 val |= PPC_BIT(0 + 8 * i) | PPC_BIT(1 + 8 * i); in pnv_core_power10_xscom_read()
249 val &= ~PPC_BIT(7 + 8 * i); in pnv_core_power10_xscom_write()
253 val &= ~PPC_BIT(6 + 8 * i); in pnv_core_power10_xscom_write()
257 val &= ~PPC_BIT(4 + 8 * i); in pnv_core_power10_xscom_write()
267 val &= ~PPC_BIT(3 + 8 * i); in pnv_core_power10_xscom_write()
610 val |= PPC_BIT(1); /* SPWU DONE */ in pnv_qme_power10_xscom_read()
611 val |= PPC_BIT(4); /* SSH SPWU DONE */ in pnv_qme_power10_xscom_read()
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H A Dpnv_adu.c60 val = PPC_BIT(0); /* ack / done */ in pnv_adu_xscom_read()
75 return !!(adu->lpc_cmd_reg & PPC_BIT(0)); in lpc_cmd_read()
/openbmc/linux/arch/powerpc/include/asm/
H A Dpnv-ocxl.h18 #define PNV_OCXL_ATSD_LNCH_R PPC_BIT(0)
34 #define PNV_OCXL_ATSD_LNCH_PRS PPC_BIT(13)
36 #define PNV_OCXL_ATSD_LNCH_B PPC_BIT(14)
48 #define PNV_OCXL_ATSD_LNCH_L PPC_BIT(18)
52 #define PNV_OCXL_ATSD_LNCH_F PPC_BIT(39)
53 #define PNV_OCXL_ATSD_LNCH_OCAPI_SLBI PPC_BIT(40)
54 #define PNV_OCXL_ATSD_LNCH_OCAPI_SINGLETON PPC_BIT(41)
H A Dbitops.h47 #define PPC_BIT(bit) (1UL << PPC_BITLSHIFT(bit)) macro
48 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
H A Dvas.h250 #define VAS_GZIP_QOS_FEAT_BIT PPC_BIT(VAS_GZIP_QOS_FEAT) /* Bit 1 */
251 #define VAS_GZIP_DEF_FEAT_BIT PPC_BIT(VAS_GZIP_DEF_FEAT) /* Bit 2 */
255 #define VAS_NX_GZIP_FEAT_BIT PPC_BIT(VAS_NX_GZIP_FEAT) /* Bit 1 */
H A Dplpks.h28 #define PLPKS_ALG_RSA2048 PPC_BIT(0)
29 #define PLPKS_ALG_RSA4096 PPC_BIT(1)
/openbmc/linux/arch/powerpc/platforms/pseries/
H A Dvas.h15 #define VAS_MOD_WIN_CLOSE PPC_BIT(0)
16 #define VAS_MOD_WIN_JOBS_KILL PPC_BIT(1)
17 #define VAS_MOD_WIN_DR PPC_BIT(3)
18 #define VAS_MOD_WIN_PR PPC_BIT(4)
19 #define VAS_MOD_WIN_SF PPC_BIT(5)
20 #define VAS_MOD_WIN_TA PPC_BIT(6)
/openbmc/qemu/include/hw/ppc/
H A Dspapr.h432 #define H_CPU_CHAR_SPEC_BAR_ORI31 PPC_BIT(0)
433 #define H_CPU_CHAR_BCCTRL_SERIALISED PPC_BIT(1)
434 #define H_CPU_CHAR_L1D_FLUSH_ORI30 PPC_BIT(2)
435 #define H_CPU_CHAR_L1D_FLUSH_TRIG2 PPC_BIT(3)
436 #define H_CPU_CHAR_L1D_THREAD_PRIV PPC_BIT(4)
437 #define H_CPU_CHAR_HON_BRANCH_HINTS PPC_BIT(5)
438 #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
439 #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
440 #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
442 #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
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H A Dxive_regs.h39 #define XIVE_TRIGGER_END PPC_BIT(0)
40 #define XIVE_TRIGGER_PQ PPC_BIT(1)
160 #define EAS_VALID PPC_BIT(0)
163 #define EAS_MASKED PPC_BIT(32) /* Masked */
H A Dxive2_regs.h41 #define EAS2_VALID PPC_BIT(0)
44 #define EAS2_MASKED PPC_BIT(32) /* Masked */
/openbmc/qemu/tests/qtest/
H A Dpnv-host-i2c-test.c15 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) macro
18 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
/openbmc/linux/arch/powerpc/kernel/
H A Dmce_power.c135 #define SRR1_MC_LOADSTORE(srr1) ((srr1) & PPC_BIT(42))
766 srr1 &= ~PPC_BIT(42); in __machine_check_early_realmode_p9()
786 srr1 &= ~PPC_BIT(42); in __machine_check_early_realmode_p10()

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