12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
296768914SSukadev Bhattiprolu /*
396768914SSukadev Bhattiprolu * Copyright 2016-17 IBM Corp.
496768914SSukadev Bhattiprolu */
596768914SSukadev Bhattiprolu
696768914SSukadev Bhattiprolu #ifndef _VAS_H
796768914SSukadev Bhattiprolu #define _VAS_H
896768914SSukadev Bhattiprolu #include <linux/atomic.h>
996768914SSukadev Bhattiprolu #include <linux/idr.h>
1096768914SSukadev Bhattiprolu #include <asm/vas.h>
11b25b33acSSukadev Bhattiprolu #include <linux/io.h>
12ece4e512SSukadev Bhattiprolu #include <linux/dcache.h>
13ece4e512SSukadev Bhattiprolu #include <linux/mutex.h>
145c35a02cSChristophe Leroy #include <linux/stringify.h>
1596768914SSukadev Bhattiprolu
1696768914SSukadev Bhattiprolu /*
1796768914SSukadev Bhattiprolu * Overview of Virtual Accelerator Switchboard (VAS).
1896768914SSukadev Bhattiprolu *
1996768914SSukadev Bhattiprolu * VAS is a hardware "switchboard" that allows senders and receivers to
2096768914SSukadev Bhattiprolu * exchange messages with _minimal_ kernel involvment. The receivers are
2196768914SSukadev Bhattiprolu * typically NX coprocessor engines that perform compression or encryption
2296768914SSukadev Bhattiprolu * in hardware, but receivers can also be other software threads.
2396768914SSukadev Bhattiprolu *
2496768914SSukadev Bhattiprolu * Senders are user/kernel threads that submit compression/encryption or
2596768914SSukadev Bhattiprolu * other requests to the receivers. Senders must format their messages as
2696768914SSukadev Bhattiprolu * Coprocessor Request Blocks (CRB)s and submit them using the "copy" and
2796768914SSukadev Bhattiprolu * "paste" instructions which were introduced in Power9.
2896768914SSukadev Bhattiprolu *
2996768914SSukadev Bhattiprolu * A Power node can have (upto?) 8 Power chips. There is one instance of
3096768914SSukadev Bhattiprolu * VAS in each Power9 chip. Each instance of VAS has 64K windows or ports,
3196768914SSukadev Bhattiprolu * Senders and receivers must each connect to a separate window before they
3296768914SSukadev Bhattiprolu * can exchange messages through the switchboard.
3396768914SSukadev Bhattiprolu *
3496768914SSukadev Bhattiprolu * Each window is described by two types of window contexts:
3596768914SSukadev Bhattiprolu *
3696768914SSukadev Bhattiprolu * Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes
3796768914SSukadev Bhattiprolu *
3896768914SSukadev Bhattiprolu * OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes.
3996768914SSukadev Bhattiprolu *
4096768914SSukadev Bhattiprolu * A window context can be viewed as a set of 64-bit registers. The settings
4196768914SSukadev Bhattiprolu * in these registers configure/control/determine the behavior of the VAS
4296768914SSukadev Bhattiprolu * hardware when messages are sent/received through the window. The registers
4396768914SSukadev Bhattiprolu * in the HVWC are configured by the kernel while the registers in the UWC can
4496768914SSukadev Bhattiprolu * be configured by the kernel or by the user space application that is using
4596768914SSukadev Bhattiprolu * the window.
4696768914SSukadev Bhattiprolu *
4796768914SSukadev Bhattiprolu * The HVWCs for all windows on a specific instance of VAS are in a contiguous
4896768914SSukadev Bhattiprolu * range of hardware addresses or Base address region (BAR) referred to as the
4996768914SSukadev Bhattiprolu * HVWC BAR for the instance. Similarly the UWCs for all windows on an instance
5096768914SSukadev Bhattiprolu * are referred to as the UWC BAR for the instance.
5196768914SSukadev Bhattiprolu *
5296768914SSukadev Bhattiprolu * The two BARs for each instance are defined Power9 MMIO Ranges spreadsheet
5396768914SSukadev Bhattiprolu * and available to the kernel in the VAS node's "reg" property in the device
5496768914SSukadev Bhattiprolu * tree:
5596768914SSukadev Bhattiprolu *
5696768914SSukadev Bhattiprolu * /proc/device-tree/vasm@.../reg
5796768914SSukadev Bhattiprolu *
5896768914SSukadev Bhattiprolu * (see vas_probe() for details on the reg property).
5996768914SSukadev Bhattiprolu *
6096768914SSukadev Bhattiprolu * The kernel maps the HVWC and UWC BAR regions into the kernel address
6196768914SSukadev Bhattiprolu * space (hvwc_map and uwc_map). The kernel can then access the window
6296768914SSukadev Bhattiprolu * contexts of a specific window using:
6396768914SSukadev Bhattiprolu *
6496768914SSukadev Bhattiprolu * hvwc = hvwc_map + winid * VAS_HVWC_SIZE.
6596768914SSukadev Bhattiprolu * uwc = uwc_map + winid * VAS_UWC_SIZE.
6696768914SSukadev Bhattiprolu *
6796768914SSukadev Bhattiprolu * where winid is the window index (0..64K).
6896768914SSukadev Bhattiprolu *
6996768914SSukadev Bhattiprolu * As mentioned, a window context is used to "configure" a window. Besides
7096768914SSukadev Bhattiprolu * this configuration address, each _send_ window also has a unique hardware
7196768914SSukadev Bhattiprolu * "paste" address that is used to submit requests/CRBs (see vas_paste_crb()).
7296768914SSukadev Bhattiprolu *
7396768914SSukadev Bhattiprolu * The hardware paste address for a window is computed using the "paste
7496768914SSukadev Bhattiprolu * base address" and "paste win id shift" reg properties in the VAS device
7596768914SSukadev Bhattiprolu * tree node using:
7696768914SSukadev Bhattiprolu *
7796768914SSukadev Bhattiprolu * paste_addr = paste_base + ((winid << paste_win_id_shift))
7896768914SSukadev Bhattiprolu *
7996768914SSukadev Bhattiprolu * (again, see vas_probe() for ->paste_base_addr and ->paste_win_id_shift).
8096768914SSukadev Bhattiprolu *
8196768914SSukadev Bhattiprolu * The kernel maps this hardware address into the sender's address space
8296768914SSukadev Bhattiprolu * after which they can use the 'paste' instruction (new in Power9) to
8396768914SSukadev Bhattiprolu * send a message (submit a request aka CRB) to the coprocessor.
8496768914SSukadev Bhattiprolu *
8596768914SSukadev Bhattiprolu * NOTE: In the initial version, senders can only in-kernel drivers/threads.
8696768914SSukadev Bhattiprolu * Support for user space threads will be added in follow-on patches.
8796768914SSukadev Bhattiprolu *
8896768914SSukadev Bhattiprolu * TODO: Do we need to map the UWC into user address space so they can return
8996768914SSukadev Bhattiprolu * credits? Its NA for NX but may be needed for other receive windows.
9096768914SSukadev Bhattiprolu *
9196768914SSukadev Bhattiprolu */
9296768914SSukadev Bhattiprolu
9396768914SSukadev Bhattiprolu #define VAS_WINDOWS_PER_CHIP (64 << 10)
9496768914SSukadev Bhattiprolu
9596768914SSukadev Bhattiprolu /*
9696768914SSukadev Bhattiprolu * Hypervisor and OS/USer Window Context sizes
9796768914SSukadev Bhattiprolu */
9896768914SSukadev Bhattiprolu #define VAS_HVWC_SIZE 512
9996768914SSukadev Bhattiprolu #define VAS_UWC_SIZE PAGE_SIZE
10096768914SSukadev Bhattiprolu
10196768914SSukadev Bhattiprolu /*
10296768914SSukadev Bhattiprolu * Initial per-process credits.
10396768914SSukadev Bhattiprolu * Max send window credits: 4K-1 (12-bits in VAS_TX_WCRED)
10496768914SSukadev Bhattiprolu *
10596768914SSukadev Bhattiprolu * TODO: Needs tuning for per-process credits
10696768914SSukadev Bhattiprolu */
10751b53712SSukadev Bhattiprolu #define VAS_TX_WCREDS_MAX ((4 << 10) - 1)
10896768914SSukadev Bhattiprolu #define VAS_WCREDS_DEFAULT (1 << 10)
10996768914SSukadev Bhattiprolu
11096768914SSukadev Bhattiprolu /*
11196768914SSukadev Bhattiprolu * VAS Window Context Register Offsets and bitmasks.
11296768914SSukadev Bhattiprolu * See Section 3.1.4 of VAS Work book
11396768914SSukadev Bhattiprolu */
11496768914SSukadev Bhattiprolu #define VAS_LPID_OFFSET 0x010
11596768914SSukadev Bhattiprolu #define VAS_LPID PPC_BITMASK(0, 11)
11696768914SSukadev Bhattiprolu
11796768914SSukadev Bhattiprolu #define VAS_PID_OFFSET 0x018
11896768914SSukadev Bhattiprolu #define VAS_PID_ID PPC_BITMASK(0, 19)
11996768914SSukadev Bhattiprolu
12096768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_OFFSET 0x020
12196768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_DR PPC_BIT(0)
12296768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_TA PPC_BIT(1)
12396768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_PR PPC_BIT(2)
12496768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_US PPC_BIT(3)
12596768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_HV PPC_BIT(4)
12696768914SSukadev Bhattiprolu #define VAS_XLATE_MSR_SF PPC_BIT(5)
12796768914SSukadev Bhattiprolu
12896768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_OFFSET 0x028
12996768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_PAGE_SIZE PPC_BITMASK(0, 2)
13096768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_ISL PPC_BIT(3)
13196768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_TC PPC_BIT(4)
13296768914SSukadev Bhattiprolu #define VAS_XLATE_LPCR_SC PPC_BIT(5)
13396768914SSukadev Bhattiprolu
13496768914SSukadev Bhattiprolu #define VAS_XLATE_CTL_OFFSET 0x030
13596768914SSukadev Bhattiprolu #define VAS_XLATE_MODE PPC_BITMASK(0, 1)
13696768914SSukadev Bhattiprolu
13796768914SSukadev Bhattiprolu #define VAS_AMR_OFFSET 0x040
13896768914SSukadev Bhattiprolu #define VAS_AMR PPC_BITMASK(0, 63)
13996768914SSukadev Bhattiprolu
14096768914SSukadev Bhattiprolu #define VAS_SEIDR_OFFSET 0x048
14196768914SSukadev Bhattiprolu #define VAS_SEIDR PPC_BITMASK(0, 63)
14296768914SSukadev Bhattiprolu
14396768914SSukadev Bhattiprolu #define VAS_FAULT_TX_WIN_OFFSET 0x050
14496768914SSukadev Bhattiprolu #define VAS_FAULT_TX_WIN PPC_BITMASK(48, 63)
14596768914SSukadev Bhattiprolu
14696768914SSukadev Bhattiprolu #define VAS_OSU_INTR_SRC_RA_OFFSET 0x060
14796768914SSukadev Bhattiprolu #define VAS_OSU_INTR_SRC_RA PPC_BITMASK(8, 63)
14896768914SSukadev Bhattiprolu
14996768914SSukadev Bhattiprolu #define VAS_HV_INTR_SRC_RA_OFFSET 0x070
15096768914SSukadev Bhattiprolu #define VAS_HV_INTR_SRC_RA PPC_BITMASK(8, 63)
15196768914SSukadev Bhattiprolu
15296768914SSukadev Bhattiprolu #define VAS_PSWID_OFFSET 0x078
15396768914SSukadev Bhattiprolu #define VAS_PSWID_EA_HANDLE PPC_BITMASK(0, 31)
15496768914SSukadev Bhattiprolu
15596768914SSukadev Bhattiprolu #define VAS_SPARE1_OFFSET 0x080
15696768914SSukadev Bhattiprolu #define VAS_SPARE2_OFFSET 0x088
15796768914SSukadev Bhattiprolu #define VAS_SPARE3_OFFSET 0x090
15896768914SSukadev Bhattiprolu #define VAS_SPARE4_OFFSET 0x130
15996768914SSukadev Bhattiprolu #define VAS_SPARE5_OFFSET 0x160
16096768914SSukadev Bhattiprolu #define VAS_SPARE6_OFFSET 0x188
16196768914SSukadev Bhattiprolu
16296768914SSukadev Bhattiprolu #define VAS_LFIFO_BAR_OFFSET 0x0A0
16396768914SSukadev Bhattiprolu #define VAS_LFIFO_BAR PPC_BITMASK(8, 53)
16496768914SSukadev Bhattiprolu #define VAS_PAGE_MIGRATION_SELECT PPC_BITMASK(54, 56)
16596768914SSukadev Bhattiprolu
16696768914SSukadev Bhattiprolu #define VAS_LDATA_STAMP_CTL_OFFSET 0x0A8
16796768914SSukadev Bhattiprolu #define VAS_LDATA_STAMP PPC_BITMASK(0, 1)
16896768914SSukadev Bhattiprolu #define VAS_XTRA_WRITE PPC_BIT(2)
16996768914SSukadev Bhattiprolu
17096768914SSukadev Bhattiprolu #define VAS_LDMA_CACHE_CTL_OFFSET 0x0B0
17196768914SSukadev Bhattiprolu #define VAS_LDMA_TYPE PPC_BITMASK(0, 1)
17296768914SSukadev Bhattiprolu #define VAS_LDMA_FIFO_DISABLE PPC_BIT(2)
17396768914SSukadev Bhattiprolu
17496768914SSukadev Bhattiprolu #define VAS_LRFIFO_PUSH_OFFSET 0x0B8
17596768914SSukadev Bhattiprolu #define VAS_LRFIFO_PUSH PPC_BITMASK(0, 15)
17696768914SSukadev Bhattiprolu
17796768914SSukadev Bhattiprolu #define VAS_CURR_MSG_COUNT_OFFSET 0x0C0
17896768914SSukadev Bhattiprolu #define VAS_CURR_MSG_COUNT PPC_BITMASK(0, 7)
17996768914SSukadev Bhattiprolu
18096768914SSukadev Bhattiprolu #define VAS_LNOTIFY_AFTER_COUNT_OFFSET 0x0C8
18196768914SSukadev Bhattiprolu #define VAS_LNOTIFY_AFTER_COUNT PPC_BITMASK(0, 7)
18296768914SSukadev Bhattiprolu
18396768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_OFFSET 0x0E0
18496768914SSukadev Bhattiprolu #define VAS_LRX_WCRED PPC_BITMASK(0, 15)
18596768914SSukadev Bhattiprolu
18696768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_ADDER_OFFSET 0x190
18796768914SSukadev Bhattiprolu #define VAS_LRX_WCRED_ADDER PPC_BITMASK(0, 15)
18896768914SSukadev Bhattiprolu
18996768914SSukadev Bhattiprolu #define VAS_TX_WCRED_OFFSET 0x0F0
19096768914SSukadev Bhattiprolu #define VAS_TX_WCRED PPC_BITMASK(4, 15)
19196768914SSukadev Bhattiprolu
19296768914SSukadev Bhattiprolu #define VAS_TX_WCRED_ADDER_OFFSET 0x1A0
19396768914SSukadev Bhattiprolu #define VAS_TX_WCRED_ADDER PPC_BITMASK(4, 15)
19496768914SSukadev Bhattiprolu
19596768914SSukadev Bhattiprolu #define VAS_LFIFO_SIZE_OFFSET 0x100
19696768914SSukadev Bhattiprolu #define VAS_LFIFO_SIZE PPC_BITMASK(0, 3)
19796768914SSukadev Bhattiprolu
19896768914SSukadev Bhattiprolu #define VAS_WINCTL_OFFSET 0x108
19996768914SSukadev Bhattiprolu #define VAS_WINCTL_OPEN PPC_BIT(0)
20096768914SSukadev Bhattiprolu #define VAS_WINCTL_REJ_NO_CREDIT PPC_BIT(1)
20196768914SSukadev Bhattiprolu #define VAS_WINCTL_PIN PPC_BIT(2)
20296768914SSukadev Bhattiprolu #define VAS_WINCTL_TX_WCRED_MODE PPC_BIT(3)
20396768914SSukadev Bhattiprolu #define VAS_WINCTL_RX_WCRED_MODE PPC_BIT(4)
20496768914SSukadev Bhattiprolu #define VAS_WINCTL_TX_WORD_MODE PPC_BIT(5)
20596768914SSukadev Bhattiprolu #define VAS_WINCTL_RX_WORD_MODE PPC_BIT(6)
20696768914SSukadev Bhattiprolu #define VAS_WINCTL_RSVD_TXBUF PPC_BIT(7)
20796768914SSukadev Bhattiprolu #define VAS_WINCTL_THRESH_CTL PPC_BITMASK(8, 9)
20896768914SSukadev Bhattiprolu #define VAS_WINCTL_FAULT_WIN PPC_BIT(10)
20996768914SSukadev Bhattiprolu #define VAS_WINCTL_NX_WIN PPC_BIT(11)
21096768914SSukadev Bhattiprolu
21196768914SSukadev Bhattiprolu #define VAS_WIN_STATUS_OFFSET 0x110
21296768914SSukadev Bhattiprolu #define VAS_WIN_BUSY PPC_BIT(1)
21396768914SSukadev Bhattiprolu
21496768914SSukadev Bhattiprolu #define VAS_WIN_CTX_CACHING_CTL_OFFSET 0x118
21596768914SSukadev Bhattiprolu #define VAS_CASTOUT_REQ PPC_BIT(0)
21696768914SSukadev Bhattiprolu #define VAS_PUSH_TO_MEM PPC_BIT(1)
21796768914SSukadev Bhattiprolu #define VAS_WIN_CACHE_STATUS PPC_BIT(4)
21896768914SSukadev Bhattiprolu
21996768914SSukadev Bhattiprolu #define VAS_TX_RSVD_BUF_COUNT_OFFSET 0x120
22096768914SSukadev Bhattiprolu #define VAS_RXVD_BUF_COUNT PPC_BITMASK(58, 63)
22196768914SSukadev Bhattiprolu
22296768914SSukadev Bhattiprolu #define VAS_LRFIFO_WIN_PTR_OFFSET 0x128
22396768914SSukadev Bhattiprolu #define VAS_LRX_WIN_ID PPC_BITMASK(0, 15)
22496768914SSukadev Bhattiprolu
22596768914SSukadev Bhattiprolu /*
22696768914SSukadev Bhattiprolu * Local Notification Control Register controls what happens in _response_
22796768914SSukadev Bhattiprolu * to a paste command and hence applies only to receive windows.
22896768914SSukadev Bhattiprolu */
22996768914SSukadev Bhattiprolu #define VAS_LNOTIFY_CTL_OFFSET 0x138
23096768914SSukadev Bhattiprolu #define VAS_NOTIFY_DISABLE PPC_BIT(0)
23196768914SSukadev Bhattiprolu #define VAS_INTR_DISABLE PPC_BIT(1)
23296768914SSukadev Bhattiprolu #define VAS_NOTIFY_EARLY PPC_BIT(2)
23396768914SSukadev Bhattiprolu #define VAS_NOTIFY_OSU_INTR PPC_BIT(3)
23496768914SSukadev Bhattiprolu
23596768914SSukadev Bhattiprolu #define VAS_LNOTIFY_PID_OFFSET 0x140
23696768914SSukadev Bhattiprolu #define VAS_LNOTIFY_PID PPC_BITMASK(0, 19)
23796768914SSukadev Bhattiprolu
23896768914SSukadev Bhattiprolu #define VAS_LNOTIFY_LPID_OFFSET 0x148
23996768914SSukadev Bhattiprolu #define VAS_LNOTIFY_LPID PPC_BITMASK(0, 11)
24096768914SSukadev Bhattiprolu
24196768914SSukadev Bhattiprolu #define VAS_LNOTIFY_TID_OFFSET 0x150
24296768914SSukadev Bhattiprolu #define VAS_LNOTIFY_TID PPC_BITMASK(0, 15)
24396768914SSukadev Bhattiprolu
24496768914SSukadev Bhattiprolu #define VAS_LNOTIFY_SCOPE_OFFSET 0x158
24596768914SSukadev Bhattiprolu #define VAS_LNOTIFY_MIN_SCOPE PPC_BITMASK(0, 1)
24696768914SSukadev Bhattiprolu #define VAS_LNOTIFY_MAX_SCOPE PPC_BITMASK(2, 3)
24796768914SSukadev Bhattiprolu
24896768914SSukadev Bhattiprolu #define VAS_NX_UTIL_OFFSET 0x1B0
24996768914SSukadev Bhattiprolu #define VAS_NX_UTIL PPC_BITMASK(0, 63)
25096768914SSukadev Bhattiprolu
25196768914SSukadev Bhattiprolu /* SE: Side effects */
25296768914SSukadev Bhattiprolu #define VAS_NX_UTIL_SE_OFFSET 0x1B8
25396768914SSukadev Bhattiprolu #define VAS_NX_UTIL_SE PPC_BITMASK(0, 63)
25496768914SSukadev Bhattiprolu
25596768914SSukadev Bhattiprolu #define VAS_NX_UTIL_ADDER_OFFSET 0x180
25696768914SSukadev Bhattiprolu #define VAS_NX_UTIL_ADDER PPC_BITMASK(32, 63)
25796768914SSukadev Bhattiprolu
25896768914SSukadev Bhattiprolu /*
2590a2c2c24SSukadev Bhattiprolu * VREG(x):
2600a2c2c24SSukadev Bhattiprolu * Expand a register's short name (eg: LPID) into two parameters:
2610a2c2c24SSukadev Bhattiprolu * - the register's short name in string form ("LPID"), and
2620a2c2c24SSukadev Bhattiprolu * - the name of the macro (eg: VAS_LPID_OFFSET), defining the
2630a2c2c24SSukadev Bhattiprolu * register's offset in the window context
2640a2c2c24SSukadev Bhattiprolu */
2650a2c2c24SSukadev Bhattiprolu #define VREG_SFX(n, s) __stringify(n), VAS_##n##s
2660a2c2c24SSukadev Bhattiprolu #define VREG(r) VREG_SFX(r, _OFFSET)
2670a2c2c24SSukadev Bhattiprolu
2680a2c2c24SSukadev Bhattiprolu /*
26996768914SSukadev Bhattiprolu * Local Notify Scope Control Register. (Receive windows only).
27096768914SSukadev Bhattiprolu */
27196768914SSukadev Bhattiprolu enum vas_notify_scope {
27296768914SSukadev Bhattiprolu VAS_SCOPE_LOCAL,
27396768914SSukadev Bhattiprolu VAS_SCOPE_GROUP,
27496768914SSukadev Bhattiprolu VAS_SCOPE_VECTORED_GROUP,
27596768914SSukadev Bhattiprolu VAS_SCOPE_UNUSED,
27696768914SSukadev Bhattiprolu };
27796768914SSukadev Bhattiprolu
27896768914SSukadev Bhattiprolu /*
27996768914SSukadev Bhattiprolu * Local DMA Cache Control Register (Receive windows only).
28096768914SSukadev Bhattiprolu */
28196768914SSukadev Bhattiprolu enum vas_dma_type {
28296768914SSukadev Bhattiprolu VAS_DMA_TYPE_INJECT,
28396768914SSukadev Bhattiprolu VAS_DMA_TYPE_WRITE,
28496768914SSukadev Bhattiprolu };
28596768914SSukadev Bhattiprolu
28696768914SSukadev Bhattiprolu /*
28796768914SSukadev Bhattiprolu * Local Notify Scope Control Register. (Receive windows only).
28896768914SSukadev Bhattiprolu * Not applicable to NX receive windows.
28996768914SSukadev Bhattiprolu */
29096768914SSukadev Bhattiprolu enum vas_notify_after_count {
29196768914SSukadev Bhattiprolu VAS_NOTIFY_AFTER_256 = 0,
29296768914SSukadev Bhattiprolu VAS_NOTIFY_NONE,
29396768914SSukadev Bhattiprolu VAS_NOTIFY_AFTER_2
29496768914SSukadev Bhattiprolu };
29596768914SSukadev Bhattiprolu
29696768914SSukadev Bhattiprolu /*
2970d17de03SHaren Myneni * NX can generate an interrupt for multiple faults and expects kernel
2980d17de03SHaren Myneni * to process all of them. So read all valid CRB entries until find the
2990d17de03SHaren Myneni * invalid one. So use pswid which is pasted by NX and ccw[0] (reserved
3000d17de03SHaren Myneni * bit in BE) to check valid CRB. CCW[0] will not be touched by user
3010d17de03SHaren Myneni * space. Application gets CRB formt error if it updates this bit.
3020d17de03SHaren Myneni *
3030d17de03SHaren Myneni * Invalidate FIFO during allocation and process all entries from last
3040d17de03SHaren Myneni * successful read until finds invalid pswid and ccw[0] values.
3050d17de03SHaren Myneni * After reading each CRB entry from fault FIFO, the kernel invalidate
3060d17de03SHaren Myneni * it by updating pswid with FIFO_INVALID_ENTRY and CCW[0] with
3070d17de03SHaren Myneni * CCW0_INVALID.
3080d17de03SHaren Myneni */
3090d17de03SHaren Myneni #define FIFO_INVALID_ENTRY 0xffffffff
3100d17de03SHaren Myneni #define CCW0_INVALID 1
3110d17de03SHaren Myneni
3120d17de03SHaren Myneni /*
31396768914SSukadev Bhattiprolu * One per instance of VAS. Each instance will have a separate set of
31496768914SSukadev Bhattiprolu * receive windows, one per coprocessor type.
31562c4eda4SSukadev Bhattiprolu *
31662c4eda4SSukadev Bhattiprolu * See also function header of set_vinst_win() for details on ->windows[]
31762c4eda4SSukadev Bhattiprolu * and ->rxwin[] tables.
31896768914SSukadev Bhattiprolu */
31996768914SSukadev Bhattiprolu struct vas_instance {
32096768914SSukadev Bhattiprolu int vas_id;
32196768914SSukadev Bhattiprolu struct ida ida;
32296768914SSukadev Bhattiprolu struct list_head node;
32396768914SSukadev Bhattiprolu struct platform_device *pdev;
32496768914SSukadev Bhattiprolu
32596768914SSukadev Bhattiprolu u64 hvwc_bar_start;
32696768914SSukadev Bhattiprolu u64 uwc_bar_start;
32796768914SSukadev Bhattiprolu u64 paste_base_addr;
32896768914SSukadev Bhattiprolu u64 paste_win_id_shift;
32996768914SSukadev Bhattiprolu
330c20e1e29SHaren Myneni u64 irq_port;
331c20e1e29SHaren Myneni int virq;
3329774628aSHaren Myneni int fault_crbs;
3330d17de03SHaren Myneni int fault_fifo_size;
3349774628aSHaren Myneni int fifo_in_progress; /* To wake up thread or return IRQ_HANDLED */
3359774628aSHaren Myneni spinlock_t fault_lock; /* Protects fifo_in_progress update */
3360d17de03SHaren Myneni void *fault_fifo;
3377bc6f71bSHaren Myneni struct pnv_vas_window *fault_win; /* Fault window */
3380d17de03SHaren Myneni
33996768914SSukadev Bhattiprolu struct mutex mutex;
3407bc6f71bSHaren Myneni struct pnv_vas_window *rxwin[VAS_COP_TYPE_MAX];
3417bc6f71bSHaren Myneni struct pnv_vas_window *windows[VAS_WINDOWS_PER_CHIP];
342ece4e512SSukadev Bhattiprolu
3439dd31b11SCédric Le Goater char *name;
344ece4e512SSukadev Bhattiprolu char *dbgname;
345ece4e512SSukadev Bhattiprolu struct dentry *dbgdir;
34696768914SSukadev Bhattiprolu };
34796768914SSukadev Bhattiprolu
34896768914SSukadev Bhattiprolu /*
3497bc6f71bSHaren Myneni * In-kernel state a VAS window on PowerNV. One per window.
35096768914SSukadev Bhattiprolu */
3517bc6f71bSHaren Myneni struct pnv_vas_window {
3527bc6f71bSHaren Myneni struct vas_window vas_win;
35396768914SSukadev Bhattiprolu /* Fields common to send and receive windows */
35496768914SSukadev Bhattiprolu struct vas_instance *vinst;
35596768914SSukadev Bhattiprolu bool tx_win; /* True if send window */
35696768914SSukadev Bhattiprolu bool nx_win; /* True if NX window */
35796768914SSukadev Bhattiprolu bool user_win; /* True if user space window */
35896768914SSukadev Bhattiprolu void *hvwc_map; /* HV window context */
35996768914SSukadev Bhattiprolu void *uwc_map; /* OS/User window context */
360ece4e512SSukadev Bhattiprolu
36196768914SSukadev Bhattiprolu /* Fields applicable only to send windows */
36296768914SSukadev Bhattiprolu void *paste_kaddr;
36396768914SSukadev Bhattiprolu char *paste_addr_name;
3647bc6f71bSHaren Myneni struct pnv_vas_window *rxwin;
36596768914SSukadev Bhattiprolu
3667bc6f71bSHaren Myneni /* Fields applicable only to receive windows */
36796768914SSukadev Bhattiprolu atomic_t num_txwins;
36896768914SSukadev Bhattiprolu };
36996768914SSukadev Bhattiprolu
37096768914SSukadev Bhattiprolu /*
37196768914SSukadev Bhattiprolu * Container for the hardware state of a window. One per-window.
37296768914SSukadev Bhattiprolu *
37396768914SSukadev Bhattiprolu * A VAS Window context is a 512-byte area in the hardware that contains
37496768914SSukadev Bhattiprolu * a set of 64-bit registers. Individual bit-fields in these registers
37596768914SSukadev Bhattiprolu * determine the configuration/operation of the hardware. struct vas_winctx
37696768914SSukadev Bhattiprolu * is a container for the register fields in the window context.
37796768914SSukadev Bhattiprolu */
37896768914SSukadev Bhattiprolu struct vas_winctx {
379ce29ea35SHaren Myneni u64 rx_fifo;
38096768914SSukadev Bhattiprolu int rx_fifo_size;
38196768914SSukadev Bhattiprolu int wcreds_max;
38296768914SSukadev Bhattiprolu int rsvd_txbuf_count;
38396768914SSukadev Bhattiprolu
38496768914SSukadev Bhattiprolu bool user_win;
38596768914SSukadev Bhattiprolu bool nx_win;
38696768914SSukadev Bhattiprolu bool fault_win;
38796768914SSukadev Bhattiprolu bool rsvd_txbuf_enable;
38896768914SSukadev Bhattiprolu bool pin_win;
38996768914SSukadev Bhattiprolu bool rej_no_credit;
39096768914SSukadev Bhattiprolu bool tx_wcred_mode;
39196768914SSukadev Bhattiprolu bool rx_wcred_mode;
39296768914SSukadev Bhattiprolu bool tx_word_mode;
39396768914SSukadev Bhattiprolu bool rx_word_mode;
39496768914SSukadev Bhattiprolu bool data_stamp;
39596768914SSukadev Bhattiprolu bool xtra_write;
39696768914SSukadev Bhattiprolu bool notify_disable;
39796768914SSukadev Bhattiprolu bool intr_disable;
39896768914SSukadev Bhattiprolu bool fifo_disable;
39996768914SSukadev Bhattiprolu bool notify_early;
40096768914SSukadev Bhattiprolu bool notify_os_intr_reg;
40196768914SSukadev Bhattiprolu
40296768914SSukadev Bhattiprolu int lpid;
40396768914SSukadev Bhattiprolu int pidr; /* value from SPRN_PID, not linux pid */
40496768914SSukadev Bhattiprolu int lnotify_lpid;
40596768914SSukadev Bhattiprolu int lnotify_pid;
40696768914SSukadev Bhattiprolu int lnotify_tid;
40796768914SSukadev Bhattiprolu u32 pswid;
40896768914SSukadev Bhattiprolu int rx_win_id;
40996768914SSukadev Bhattiprolu int fault_win_id;
41096768914SSukadev Bhattiprolu int tc_mode;
41196768914SSukadev Bhattiprolu
41296768914SSukadev Bhattiprolu u64 irq_port;
41396768914SSukadev Bhattiprolu
41496768914SSukadev Bhattiprolu enum vas_dma_type dma_type;
41596768914SSukadev Bhattiprolu enum vas_notify_scope min_scope;
41696768914SSukadev Bhattiprolu enum vas_notify_scope max_scope;
41796768914SSukadev Bhattiprolu enum vas_notify_after_count notify_after_count;
41896768914SSukadev Bhattiprolu };
41996768914SSukadev Bhattiprolu
420ece4e512SSukadev Bhattiprolu extern struct mutex vas_mutex;
421ece4e512SSukadev Bhattiprolu
4224dea2d1aSSukadev Bhattiprolu extern struct vas_instance *find_vas_instance(int vasid);
423ece4e512SSukadev Bhattiprolu extern void vas_init_dbgdir(void);
424ece4e512SSukadev Bhattiprolu extern void vas_instance_init_dbgdir(struct vas_instance *vinst);
4257bc6f71bSHaren Myneni extern void vas_window_init_dbgdir(struct pnv_vas_window *win);
4267bc6f71bSHaren Myneni extern void vas_window_free_dbgdir(struct pnv_vas_window *win);
4270d17de03SHaren Myneni extern int vas_setup_fault_window(struct vas_instance *vinst);
4289774628aSHaren Myneni extern irqreturn_t vas_fault_thread_fn(int irq, void *data);
4299774628aSHaren Myneni extern irqreturn_t vas_fault_handler(int irq, void *dev_id);
4307bc6f71bSHaren Myneni extern void vas_return_credit(struct pnv_vas_window *window, bool tx);
4317bc6f71bSHaren Myneni extern struct pnv_vas_window *vas_pswid_to_window(struct vas_instance *vinst,
4329774628aSHaren Myneni uint32_t pswid);
4337bc6f71bSHaren Myneni extern void vas_win_paste_addr(struct pnv_vas_window *window, u64 *addr,
4341a0d0d5eSHaren Myneni int *len);
4354dea2d1aSSukadev Bhattiprolu
vas_window_pid(struct vas_window * window)436db1c08a7SHaren Myneni static inline int vas_window_pid(struct vas_window *window)
437db1c08a7SHaren Myneni {
4383856aa54SHaren Myneni return pid_vnr(window->task_ref.pid);
439db1c08a7SHaren Myneni }
440db1c08a7SHaren Myneni
vas_log_write(struct pnv_vas_window * win,char * name,void * regptr,u64 val)4417bc6f71bSHaren Myneni static inline void vas_log_write(struct pnv_vas_window *win, char *name,
442b25b33acSSukadev Bhattiprolu void *regptr, u64 val)
443b25b33acSSukadev Bhattiprolu {
444b25b33acSSukadev Bhattiprolu if (val)
4450a2c2c24SSukadev Bhattiprolu pr_debug("%swin #%d: %s reg %p, val 0x%016llx\n",
4467bc6f71bSHaren Myneni win->tx_win ? "Tx" : "Rx", win->vas_win.winid,
4477bc6f71bSHaren Myneni name, regptr, val);
448b25b33acSSukadev Bhattiprolu }
449b25b33acSSukadev Bhattiprolu
write_uwc_reg(struct pnv_vas_window * win,char * name,s32 reg,u64 val)4507bc6f71bSHaren Myneni static inline void write_uwc_reg(struct pnv_vas_window *win, char *name,
451b25b33acSSukadev Bhattiprolu s32 reg, u64 val)
452b25b33acSSukadev Bhattiprolu {
453b25b33acSSukadev Bhattiprolu void *regptr;
454b25b33acSSukadev Bhattiprolu
455b25b33acSSukadev Bhattiprolu regptr = win->uwc_map + reg;
456b25b33acSSukadev Bhattiprolu vas_log_write(win, name, regptr, val);
457b25b33acSSukadev Bhattiprolu
458b25b33acSSukadev Bhattiprolu out_be64(regptr, val);
459b25b33acSSukadev Bhattiprolu }
460b25b33acSSukadev Bhattiprolu
write_hvwc_reg(struct pnv_vas_window * win,char * name,s32 reg,u64 val)4617bc6f71bSHaren Myneni static inline void write_hvwc_reg(struct pnv_vas_window *win, char *name,
462b25b33acSSukadev Bhattiprolu s32 reg, u64 val)
463b25b33acSSukadev Bhattiprolu {
464b25b33acSSukadev Bhattiprolu void *regptr;
465b25b33acSSukadev Bhattiprolu
466b25b33acSSukadev Bhattiprolu regptr = win->hvwc_map + reg;
467b25b33acSSukadev Bhattiprolu vas_log_write(win, name, regptr, val);
468b25b33acSSukadev Bhattiprolu
469b25b33acSSukadev Bhattiprolu out_be64(regptr, val);
470b25b33acSSukadev Bhattiprolu }
471b25b33acSSukadev Bhattiprolu
read_hvwc_reg(struct pnv_vas_window * win,char * name __maybe_unused,s32 reg)4727bc6f71bSHaren Myneni static inline u64 read_hvwc_reg(struct pnv_vas_window *win,
473b25b33acSSukadev Bhattiprolu char *name __maybe_unused, s32 reg)
474b25b33acSSukadev Bhattiprolu {
475b25b33acSSukadev Bhattiprolu return in_be64(win->hvwc_map+reg);
476b25b33acSSukadev Bhattiprolu }
477b25b33acSSukadev Bhattiprolu
4788b8a73dcSHaren Myneni /*
4798b8a73dcSHaren Myneni * Encode/decode the Partition Send Window ID (PSWID) for a window in
4808b8a73dcSHaren Myneni * a way that we can uniquely identify any window in the system. i.e.
4818b8a73dcSHaren Myneni * we should be able to locate the 'struct vas_window' given the PSWID.
4828b8a73dcSHaren Myneni *
4838b8a73dcSHaren Myneni * Bits Usage
4848b8a73dcSHaren Myneni * 0:7 VAS id (8 bits)
4858b8a73dcSHaren Myneni * 8:15 Unused, 0 (3 bits)
4868b8a73dcSHaren Myneni * 16:31 Window id (16 bits)
4878b8a73dcSHaren Myneni */
encode_pswid(int vasid,int winid)4888b8a73dcSHaren Myneni static inline u32 encode_pswid(int vasid, int winid)
4898b8a73dcSHaren Myneni {
4908b8a73dcSHaren Myneni return ((u32)winid | (vasid << (31 - 7)));
4918b8a73dcSHaren Myneni }
4928b8a73dcSHaren Myneni
decode_pswid(u32 pswid,int * vasid,int * winid)49361f3cca8SSukadev Bhattiprolu static inline void decode_pswid(u32 pswid, int *vasid, int *winid)
49461f3cca8SSukadev Bhattiprolu {
49561f3cca8SSukadev Bhattiprolu if (vasid)
49661f3cca8SSukadev Bhattiprolu *vasid = pswid >> (31 - 7) & 0xFF;
49761f3cca8SSukadev Bhattiprolu
49861f3cca8SSukadev Bhattiprolu if (winid)
49961f3cca8SSukadev Bhattiprolu *winid = pswid & 0xFFFF;
50061f3cca8SSukadev Bhattiprolu }
50196768914SSukadev Bhattiprolu #endif /* _VAS_H */
502