12200bbecSNishad Kamdar /* SPDX-License-Identifier: GPL-2.0+ */ 26914c757SFrederic Barrat // Copyright 2017 IBM Corp. 36914c757SFrederic Barrat #ifndef _ASM_PNV_OCXL_H 46914c757SFrederic Barrat #define _ASM_PNV_OCXL_H 56914c757SFrederic Barrat 6*19b311caSChristophe Lombard #include <linux/bitfield.h> 76914c757SFrederic Barrat #include <linux/pci.h> 86914c757SFrederic Barrat 96914c757SFrederic Barrat #define PNV_OCXL_TL_MAX_TEMPLATE 63 106914c757SFrederic Barrat #define PNV_OCXL_TL_BITS_PER_RATE 4 116914c757SFrederic Barrat #define PNV_OCXL_TL_RATE_BUF_SIZE ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8) 126914c757SFrederic Barrat 13*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_TIMEOUT 1 14*19b311caSChristophe Lombard 15*19b311caSChristophe Lombard /* TLB Management Instructions */ 16*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH 0x00 17*19b311caSChristophe Lombard /* Radix Invalidate */ 18*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_R PPC_BIT(0) 19*19b311caSChristophe Lombard /* Radix Invalidation Control 20*19b311caSChristophe Lombard * 0b00 Just invalidate TLB. 21*19b311caSChristophe Lombard * 0b01 Invalidate just Page Walk Cache. 22*19b311caSChristophe Lombard * 0b10 Invalidate TLB, Page Walk Cache, and any 23*19b311caSChristophe Lombard * caching of Partition and Process Table Entries. 24*19b311caSChristophe Lombard */ 25*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_RIC PPC_BITMASK(1, 2) 26*19b311caSChristophe Lombard /* Number and Page Size of translations to be invalidated */ 27*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_LP PPC_BITMASK(3, 10) 28*19b311caSChristophe Lombard /* Invalidation Criteria 29*19b311caSChristophe Lombard * 0b00 Invalidate just the target VA. 30*19b311caSChristophe Lombard * 0b01 Invalidate matching PID. 31*19b311caSChristophe Lombard */ 32*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_IS PPC_BITMASK(11, 12) 33*19b311caSChristophe Lombard /* 0b1: Process Scope, 0b0: Partition Scope */ 34*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_PRS PPC_BIT(13) 35*19b311caSChristophe Lombard /* Invalidation Flag */ 36*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_B PPC_BIT(14) 37*19b311caSChristophe Lombard /* Actual Page Size to be invalidated 38*19b311caSChristophe Lombard * 000 4KB 39*19b311caSChristophe Lombard * 101 64KB 40*19b311caSChristophe Lombard * 001 2MB 41*19b311caSChristophe Lombard * 010 1GB 42*19b311caSChristophe Lombard */ 43*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_AP PPC_BITMASK(15, 17) 44*19b311caSChristophe Lombard /* Defines the large page select 45*19b311caSChristophe Lombard * L=0b0 for 4KB pages 46*19b311caSChristophe Lombard * L=0b1 for large pages) 47*19b311caSChristophe Lombard */ 48*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_L PPC_BIT(18) 49*19b311caSChristophe Lombard /* Process ID */ 50*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_PID PPC_BITMASK(19, 38) 51*19b311caSChristophe Lombard /* NoFlush – Assumed to be 0b0 */ 52*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_F PPC_BIT(39) 53*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_OCAPI_SLBI PPC_BIT(40) 54*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_LNCH_OCAPI_SINGLETON PPC_BIT(41) 55*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_AVA 0x08 56*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_AVA_AVA PPC_BITMASK(0, 51) 57*19b311caSChristophe Lombard #define PNV_OCXL_ATSD_STAT 0x10 58*19b311caSChristophe Lombard 59c75d42e4SAlastair D'Silva int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, u16 *supported); 60c75d42e4SAlastair D'Silva int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count); 612cb3d64bSFrederic Barrat 62c75d42e4SAlastair D'Silva int pnv_ocxl_get_tl_cap(struct pci_dev *dev, long *cap, 636914c757SFrederic Barrat char *rate_buf, int rate_buf_size); 64c75d42e4SAlastair D'Silva int pnv_ocxl_set_tl_conf(struct pci_dev *dev, long cap, 656914c757SFrederic Barrat uint64_t rate_buf_phys, int rate_buf_size); 666914c757SFrederic Barrat 67c75d42e4SAlastair D'Silva int pnv_ocxl_get_xsl_irq(struct pci_dev *dev, int *hwirq); 68c75d42e4SAlastair D'Silva void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar, 696914c757SFrederic Barrat void __iomem *tfc, void __iomem *pe_handle); 70c75d42e4SAlastair D'Silva int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr, 716914c757SFrederic Barrat void __iomem **dar, void __iomem **tfc, 726914c757SFrederic Barrat void __iomem **pe_handle); 736914c757SFrederic Barrat 74c75d42e4SAlastair D'Silva int pnv_ocxl_spa_setup(struct pci_dev *dev, void *spa_mem, int PE_mask, void **platform_data); 75c75d42e4SAlastair D'Silva void pnv_ocxl_spa_release(void *platform_data); 76c75d42e4SAlastair D'Silva int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle); 776914c757SFrederic Barrat 78fc1347b5SChristophe Lombard int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid, 79fc1347b5SChristophe Lombard uint64_t lpcr, void __iomem **arva); 80fc1347b5SChristophe Lombard void pnv_ocxl_unmap_lpar(void __iomem *arva); 81*19b311caSChristophe Lombard void pnv_ocxl_tlb_invalidate(void __iomem *arva, 82*19b311caSChristophe Lombard unsigned long pid, 83*19b311caSChristophe Lombard unsigned long addr, 84*19b311caSChristophe Lombard unsigned long page_size); 856914c757SFrederic Barrat #endif /* _ASM_PNV_OCXL_H */ 86