63         env->spr[SPR_PVR] &= ~PPC_BIT(51);  in pnv_core_cpu_reset()
208                 val |= PPC_BIT(56 + i);  in pnv_core_power10_xscom_read()
212             val |= PPC_BIT(62);  in pnv_core_power10_xscom_read()
222                 val |= PPC_BIT(0 + 8 * i) | PPC_BIT(1 + 8 * i);  in pnv_core_power10_xscom_read()
249             if (val & PPC_BIT(7 + 8 * i)) { /* stop */  in pnv_core_power10_xscom_write()
250                 val &= ~PPC_BIT(7 + 8 * i);  in pnv_core_power10_xscom_write()
254             if (val & PPC_BIT(6 + 8 * i)) { /* start */  in pnv_core_power10_xscom_write()
255                 val &= ~PPC_BIT(6 + 8 * i);  in pnv_core_power10_xscom_write()
259             if (val & PPC_BIT(4 + 8 * i)) { /* sreset */  in pnv_core_power10_xscom_write()
260                 val &= ~PPC_BIT(4 + 8 * i);  in pnv_core_power10_xscom_write()
264             if (val & PPC_BIT(3 + 8 * i)) { /* clear maint */  in pnv_core_power10_xscom_write()
272                 val &= ~PPC_BIT(3 + 8 * i);  in pnv_core_power10_xscom_write()
617             val |= PPC_BIT(1); /* SPWU DONE */  in pnv_qme_power10_xscom_read()
618             val |= PPC_BIT(4); /* SSH SPWU DONE */  in pnv_qme_power10_xscom_read()
639         set = !!(val & PPC_BIT(0));  in pnv_qme_power10_xscom_write()