Lines Matching refs:PPC_BIT
31 #define PBCQ_NEST_BAR_EN_MMIO0 PPC_BIT(0)
32 #define PBCQ_NEST_BAR_EN_MMIO1 PPC_BIT(1)
33 #define PBCQ_NEST_BAR_EN_PHB PPC_BIT(2)
34 #define PBCQ_NEST_BAR_EN_IRSN_RX PPC_BIT(3)
35 #define PBCQ_NEST_BAR_EN_IRSN_TX PPC_BIT(4)
55 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27)
56 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28)
57 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29)
59 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27)
60 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28)
61 #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29)
63 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0)
68 #define PHB_CA_ENABLE PPC_BIT(0)
76 #define PHB_IVT_BAR_ENABLE PPC_BIT(0)
80 #define PHB_RBA_BAR_ENABLE PPC_BIT(0)
83 #define PHB_PHB3C_64B_TCE_EN PPC_BIT(2)
84 #define PHB_PHB3C_32BIT_MSI_EN PPC_BIT(8)
85 #define PHB_PHB3C_64BIT_MSI_EN PPC_BIT(14)
86 #define PHB_PHB3C_M32_EN PPC_BIT(16)
88 #define PHB_RTT_BAR_ENABLE PPC_BIT(0)
91 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0)
97 #define PHB_PEST_BAR_ENABLE PPC_BIT(0)
102 #define PHB_DMARD_SYNC_START PPC_BIT(0)
103 #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1)
105 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0)
108 #define PHB_TCE_KILL_ALL PPC_BIT(0)
111 #define PHB_IODA_AD_AUTOINC PPC_BIT(0)
116 #define PHB_FFI_LOCK_CLEAR PPC_BIT(3)
119 #define PHB_FFI_LOCK_STATE PPC_BIT(0)
126 #define PHB_IVC_INVALIDATE_ALL PPC_BIT(0)
129 #define PHB_IVC_UPDATE_ENABLE_P PPC_BIT(0)
130 #define PHB_IVC_UPDATE_ENABLE_Q PPC_BIT(1)
131 #define PHB_IVC_UPDATE_ENABLE_SERVER PPC_BIT(2)
132 #define PHB_IVC_UPDATE_ENABLE_PRI PPC_BIT(3)
133 #define PHB_IVC_UPDATE_ENABLE_GEN PPC_BIT(4)
134 #define PHB_IVC_UPDATE_ENABLE_CON PPC_BIT(5)
143 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0)
144 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1)
145 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2)
146 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3)
147 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4)
148 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5)
149 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6)
203 #define PHB_PCIE_LM_LINK_ACTIVE PPC_BIT(8)
205 #define PHB_PCIE_DLP_TCTX_DISABLE PPC_BIT(1)
206 #define PHB_PCIE_DLP_TCRX_DISABLED PPC_BIT(16)
207 #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19)
208 #define PHB_PCIE_DLP_TC_DL_LINKUP PPC_BIT(21)
209 #define PHB_PCIE_DLP_TC_DL_PGRESET PPC_BIT(22)
210 #define PHB_PCIE_DLP_TC_DL_LINKACT PPC_BIT(23)
235 #define PHB_CTRL_IVE_128_BYTES PPC_BIT(24)
249 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0)
250 #define PHB_Q_DMA_R_AUTORESET PPC_BIT(1)
251 #define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4)
252 #define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5)
253 #define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6)
323 #define PHB_HPOVR_FORCE_RESAMPLE PPC_BIT(9)
324 #define PHB_HPOVR_PRESENCE_A PPC_BIT(10)
325 #define PHB_HPOVR_PRESENCE_B PPC_BIT(11)
326 #define PHB_HPOVR_LINK_ACTIVE PPC_BIT(12)
327 #define PHB_HPOVR_LINK_BIFURCATED PPC_BIT(13)
328 #define PHB_HPOVR_LINK_LANE_SWAPPED PPC_BIT(14)
374 #define IODA2_PESTA_MMIO_FROZEN PPC_BIT(0)
377 #define IODA2_PESTB_DMA_STOPPED PPC_BIT(0)
383 #define IODA2_M64BT_ENABLE PPC_BIT(0)
384 #define IODA2_M64BT_SINGLE_PE PPC_BIT(1)
402 #define IODA2_PEST0_MMIO_CAUSE PPC_BIT(2)
403 #define IODA2_PEST0_CFG_READ PPC_BIT(3)
404 #define IODA2_PEST0_CFG_WRITE PPC_BIT(4)
413 #define IODA2_PEST0_CA_RETURN PPC_BIT(8)
414 #define IODA2_PEST0_UTL_RTOS_TIMEOUT PPC_BIT(8) /* Same bit as CA return */
415 #define IODA2_PEST0_UR_RETURN PPC_BIT(9)
416 #define IODA2_PEST0_UTL_NONFATAL PPC_BIT(10)
417 #define IODA2_PEST0_UTL_FATAL PPC_BIT(11)
418 #define IODA2_PEST0_PARITY_UE PPC_BIT(13)
419 #define IODA2_PEST0_UTL_CORRECTABLE PPC_BIT(14)
420 #define IODA2_PEST0_UTL_INTERRUPT PPC_BIT(15)
421 #define IODA2_PEST0_MMIO_XLATE PPC_BIT(16)
422 #define IODA2_PEST0_IODA2_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */
423 #define IODA2_PEST0_TCE_PAGE_FAULT PPC_BIT(18)
424 #define IODA2_PEST0_TCE_ACCESS_FAULT PPC_BIT(19)
425 #define IODA2_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20)
426 #define IODA2_PEST0_AIB_SIZE_INVALID PPC_BIT(21)