1 /* 2 * QEMU PowerPC SPI model 3 * 4 * Copyright (c) 2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #ifndef PNV_SPI_CONTROLLER_REGS_H 10 #define PNV_SPI_CONTROLLER_REGS_H 11 12 /* 13 * Macros from target/ppc/cpu.h 14 * These macros are copied from ppc target specific file target/ppc/cpu.h 15 * as target/ppc/cpu.h cannot be included here. 16 */ 17 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) 18 #define PPC_BIT8(bit) (0x80 >> (bit)) 19 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) 20 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs)) 21 #define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1) 22 #define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m)) 23 #define SETFIELD(m, v, val) \ 24 (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m))) 25 26 /* Error Register */ 27 #define ERROR_REG 0x00 28 29 /* counter_config_reg */ 30 #define SPI_CTR_CFG_REG 0x01 31 #define SPI_CTR_CFG_N1 PPC_BITMASK(0, 7) 32 #define SPI_CTR_CFG_N2 PPC_BITMASK(8, 15) 33 #define SPI_CTR_CFG_CMP1 PPC_BITMASK(24, 31) 34 #define SPI_CTR_CFG_CMP2 PPC_BITMASK(32, 39) 35 #define SPI_CTR_CFG_N1_CTRL_B1 PPC_BIT(49) 36 #define SPI_CTR_CFG_N1_CTRL_B2 PPC_BIT(50) 37 #define SPI_CTR_CFG_N1_CTRL_B3 PPC_BIT(51) 38 #define SPI_CTR_CFG_N2_CTRL_B0 PPC_BIT(52) 39 #define SPI_CTR_CFG_N2_CTRL_B1 PPC_BIT(53) 40 #define SPI_CTR_CFG_N2_CTRL_B2 PPC_BIT(54) 41 #define SPI_CTR_CFG_N2_CTRL_B3 PPC_BIT(55) 42 43 /* config_reg */ 44 #define CONFIG_REG1 0x02 45 46 /* clock_config_reset_control_ecc_enable_reg */ 47 #define SPI_CLK_CFG_REG 0x03 48 #define SPI_CLK_CFG_HARD_RST 0x0084000000000000; 49 #define SPI_CLK_CFG_RST_CTRL PPC_BITMASK(24, 27) 50 #define SPI_CLK_CFG_ECC_EN PPC_BIT(28) 51 #define SPI_CLK_CFG_ECC_CTRL PPC_BITMASK(29, 30) 52 53 /* memory_mapping_reg */ 54 #define SPI_MM_REG 0x04 55 #define SPI_MM_RDR_MATCH_VAL PPC_BITMASK(32, 47) 56 #define SPI_MM_RDR_MATCH_MASK PPC_BITMASK(48, 63) 57 58 /* transmit_data_reg */ 59 #define SPI_XMIT_DATA_REG 0x05 60 61 /* receive_data_reg */ 62 #define SPI_RCV_DATA_REG 0x06 63 64 /* sequencer_operation_reg */ 65 #define SPI_SEQ_OP_REG 0x07 66 67 /* status_reg */ 68 #define SPI_STS_REG 0x08 69 #define SPI_STS_RDR_FULL PPC_BIT(0) 70 #define SPI_STS_RDR_OVERRUN PPC_BIT(1) 71 #define SPI_STS_RDR_UNDERRUN PPC_BIT(2) 72 #define SPI_STS_TDR_FULL PPC_BIT(4) 73 #define SPI_STS_TDR_OVERRUN PPC_BIT(5) 74 #define SPI_STS_TDR_UNDERRUN PPC_BIT(6) 75 #define SPI_STS_SEQ_FSM PPC_BITMASK(8, 15) 76 #define SPI_STS_SHIFTER_FSM PPC_BITMASK(16, 27) 77 #define SPI_STS_SEQ_INDEX PPC_BITMASK(28, 31) 78 #define SPI_STS_GEN_STATUS_B3 PPC_BIT(35) 79 #define SPI_STS_RDR PPC_BITMASK(1, 3) 80 #define SPI_STS_TDR PPC_BITMASK(5, 7) 81 82 /* 83 * Shifter states 84 * 85 * These are the same values defined for the Shifter FSM field of the 86 * status register. It's a 12 bit field so we will represent it as three 87 * nibbles in the constants. 88 * 89 * These are shifter_fsm values 90 * 91 * Status reg bits 16-27 -> field bits 0-11 92 * bits 0,1,2,5 unused/reserved 93 * bit 4 crc shift in (unused) 94 * bit 8 crc shift out (unused) 95 */ 96 97 #define FSM_DONE 0x100 /* bit 3 */ 98 #define FSM_SHIFT_N2 0x020 /* bit 6 */ 99 #define FSM_WAIT 0x010 /* bit 7 */ 100 #define FSM_SHIFT_N1 0x004 /* bit 9 */ 101 #define FSM_START 0x002 /* bit 10 */ 102 #define FSM_IDLE 0x001 /* bit 11 */ 103 104 /* 105 * Sequencer states 106 * 107 * These are sequencer_fsm values 108 * 109 * Status reg bits 8-15 -> field bits 0-7 110 * bits 0-3 unused/reserved 111 * 112 */ 113 #define SEQ_STATE_INDEX_INCREMENT 0x08 /* bit 4 */ 114 #define SEQ_STATE_EXECUTE 0x04 /* bit 5 */ 115 #define SEQ_STATE_DECODE 0x02 /* bit 6 */ 116 #define SEQ_STATE_IDLE 0x01 /* bit 7 */ 117 118 /* 119 * These are the supported sequencer operations. 120 * Only the upper nibble is significant because for many operations 121 * the lower nibble is a variable specific to the operation. 122 */ 123 #define SEQ_OP_STOP 0x00 124 #define SEQ_OP_SELECT_SLAVE 0x10 125 #define SEQ_OP_SHIFT_N1 0x30 126 #define SEQ_OP_SHIFT_N2 0x40 127 #define SEQ_OP_BRANCH_IFNEQ_RDR 0x60 128 #define SEQ_OP_TRANSFER_TDR 0xC0 129 #define SEQ_OP_BRANCH_IFNEQ_INC_1 0xE0 130 #define SEQ_OP_BRANCH_IFNEQ_INC_2 0xF0 131 #define NUM_SEQ_OPS 8 132 133 #endif 134