Lines Matching refs:PPC_BIT
33 #define CQ_XIVE_CAP_VP_SAVE_RESTORE PPC_BIT(38)
35 #define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
36 #define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
37 #define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
38 #define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
61 #define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16)
64 #define CQ_XIVE_CFG_GEN1_TIMA_OS PPC_BIT(24)
65 #define CQ_XIVE_CFG_GEN1_TIMA_HYP PPC_BIT(25)
66 #define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */
67 #define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */
68 #define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28)
69 #define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25]=1 */
70 #define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39) /* 0 if bit[25]=1 */
75 #define CQ_IC_BAR_VALID PPC_BIT(0)
76 #define CQ_IC_BAR_64K PPC_BIT(1)
84 #define CQ_TM_BAR_VALID PPC_BIT(0)
85 #define CQ_TM_BAR_64K PPC_BIT(1)
91 #define CQ_BAR_VALID PPC_BIT(0)
92 #define CQ_BAR_64K PPC_BIT(1)
114 #define CQ_TAR_AUTOINC PPC_BIT(0)
126 #define CQ_TDR_VALID PPC_BIT(0)
140 #define CQ_RST_SYNC_RESET PPC_BIT(0) /* Write Only */
141 #define CQ_RST_QUIESCE_PB PPC_BIT(1) /* RW */
142 #define CQ_RST_MASTER_IDLE PPC_BIT(2) /* Read Only */
143 #define CQ_RST_SAVE_IDLE PPC_BIT(3) /* Read Only */
144 #define CQ_RST_PB_BAR_RESET PPC_BIT(4) /* Write Only */
149 #define CQ_CFG_PB_GEN_PB_INIT PPC_BIT(45)
162 #define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19)
184 #define VC_VSD_TABLE_AUTOINC PPC_BIT(0)
195 #define VC_AT_MACRO_KILL_VALID PPC_BIT(0)
214 #define VC_QUEUES_CFG_MEMB_EN PPC_BIT(38)
224 #define VC_ESBC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
225 #define VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
246 #define VC_EASC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
247 #define VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
268 #define VC_ENDC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
269 #define VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
270 #define VC_ENDC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3)
271 #define VC_ENDC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7)
289 #define VC_ENDC_SYNC_QUEUE_IPI PPC_BIT(0)
290 #define VC_ENDC_SYNC_QUEUE_HWD PPC_BIT(1)
291 #define VC_ENDC_SYNC_QUEUE_NXC PPC_BIT(2)
292 #define VC_ENDC_SYNC_QUEUE_INT PPC_BIT(3)
293 #define VC_ENDC_SYNC_QUEUE_OS PPC_BIT(4)
294 #define VC_ENDC_SYNC_QUEUE_POOL PPC_BIT(5)
295 #define VC_ENDC_SYNC_QUEUE_HARD PPC_BIT(6)
310 #define VC_ENDC_WATCH_CONFLICT PPC_BIT(0)
311 #define VC_ENDC_WATCH_FULL PPC_BIT(8)
369 #define PC_VSD_TABLE_AUTOINC PPC_BIT(0)
380 #define PC_AT_KILL_VALID PPC_BIT(0)
400 #define PC_NXC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
401 #define PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
402 #define PC_NXC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3)
403 #define PC_NXC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7)
436 #define PC_NXC_WATCH_CONFLICT PPC_BIT(0)
437 #define PC_NXC_WATCH_FULL PPC_BIT(8)
550 #define VSD_FIRMWARE PPC_BIT(2) /* Read warning */
551 #define VSD_FIRMWARE2 PPC_BIT(3) /* unused */
555 #define VSD_INDIRECT PPC_BIT(56)