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Searched refs:CLK (Results 1 – 25 of 80) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dclock.h34 #define CLK_LIST(CLK)\ argument
35 CLK(0, core_pll_clk)\
36 CLK(1, pass_pll_clk)\
37 CLK(2, tetris_pll_clk)\
38 CLK(3, ddr3a_pll_clk)\
39 CLK(4, ddr3b_pll_clk)\
40 CLK(5, sys_clk0_clk)\
41 CLK(6, sys_clk0_1_clk)\
42 CLK(7, sys_clk0_2_clk)\
43 CLK(8, sys_clk0_3_clk)\
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c72 #define CLK(x) CLOCK_ID_ ## x macro
74 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
75 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
77 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
78 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
80 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
81 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
83 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
84 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
86 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c74 #define CLK(x) CLOCK_ID_ ## x macro
76 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
79 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
82 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c62 #define CLK(x) CLOCK_ID_ ## x macro
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
65 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
67 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
68 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
71 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
73 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c62 #define CLK(x) CLOCK_ID_ ## x macro
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
65 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
67 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
68 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
71 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
73 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c59 #define CLK(x) CLOCK_ID_ ## x macro
61 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
62 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
63 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
64 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
65 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
66 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
67 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
68 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
/openbmc/qemu/tests/qtest/
H A Drtl8139-test.c22 #define CLK 33333333 macro
72 const unsigned from = 0.95 * CLK; in test_timer()
73 const unsigned to = 1.6 * CLK; in test_timer()
88 if (curr > 0.1 * CLK) { in test_timer()
130 out_TimerInt(curr + 0.5 * CLK); in test_timer()
142 out_TimerInt(curr + 0.5 * CLK); in test_timer()
151 next = curr + 5.0 * CLK; in test_timer()
166 next = curr + 5.0 * CLK; in test_timer()
/openbmc/u-boot/drivers/clk/
H A DKconfig3 config CLK config
15 depends on CLK && SPL && SPL_DM
25 depends on CLK && TPL_DM
35 depends on CLK && ARCH_BMIPS
43 depends on CLK
51 depends on CLK && (STM32F7 || STM32F4)
59 depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL
67 depends on CLK
73 depends on CLK && VEXPRESS_CONFIG
80 depends on CLK && ARCH_ZYNQ
[all …]
H A DMakefile7 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
8 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
9 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
/openbmc/u-boot/arch/arm/mach-stm32/
H A DKconfig5 select CLK
21 select CLK
59 select CLK
/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME94 make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK
95 make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK
98 make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK
99 make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK
101 make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK
102 make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK
/openbmc/u-boot/include/
H A Dclk.h81 #if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(CLK)
174 CONFIG_IS_ENABLED(CLK)
/openbmc/u-boot/drivers/clk/imx/
H A DKconfig4 select CLK
/openbmc/u-boot/drivers/clk/uniphier/
H A DKconfig4 select CLK
/openbmc/u-boot/drivers/net/
H A Dmacb.c812 config = MACB_BF(CLK, MACB_CLK_DIV8); in macb_mdc_clk_div()
814 config = MACB_BF(CLK, MACB_CLK_DIV16); in macb_mdc_clk_div()
816 config = MACB_BF(CLK, MACB_CLK_DIV32); in macb_mdc_clk_div()
818 config = MACB_BF(CLK, MACB_CLK_DIV64); in macb_mdc_clk_div()
834 config = GEM_BF(CLK, GEM_CLK_DIV8); in gem_mdc_clk_div()
836 config = GEM_BF(CLK, GEM_CLK_DIV16); in gem_mdc_clk_div()
838 config = GEM_BF(CLK, GEM_CLK_DIV32); in gem_mdc_clk_div()
840 config = GEM_BF(CLK, GEM_CLK_DIV48); in gem_mdc_clk_div()
842 config = GEM_BF(CLK, GEM_CLK_DIV64); in gem_mdc_clk_div()
844 config = GEM_BF(CLK, GEM_CLK_DIV96); in gem_mdc_clk_div()
/openbmc/u-boot/drivers/clk/mvebu/
H A DKconfig3 depends on CLK && ARCH_MVEBU
/openbmc/u-boot/drivers/clk/owl/
H A DKconfig3 depends on CLK && ARCH_OWL
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxl-s905x-khadas-vim.dts151 "SDCard D1", "SDCard D0", "SDCard CLK", "SDCard CMD",
160 "WIFI SDIO D3", "WIFI SDIO CLK", "WIFI SDIO CMD",
163 "Bluetooth PCM SYNC", "Bluetooth PCM CLK",
/openbmc/u-boot/drivers/clk/exynos/
H A DKconfig3 select CLK
/openbmc/u-boot/drivers/clk/sifive/
H A DKconfig8 depends on CLK
/openbmc/u-boot/drivers/phy/
H A Dmeson-gxl-usb3.c90 #if CONFIG_IS_ENABLED(CLK)
170 #if CONFIG_IS_ENABLED(CLK) in meson_gxl_usb3_phy_probe()
H A Dmeson-gxl-usb2.c102 #if CONFIG_IS_ENABLED(CLK)
199 #if CONFIG_IS_ENABLED(CLK) in meson_gxl_usb2_phy_probe()
/openbmc/u-boot/drivers/mmc/
H A Duniphier-sd.c36 #if CONFIG_IS_ENABLED(CLK) in uniphier_sd_clk_get_rate()
/openbmc/u-boot/doc/device-tree-bindings/i2c/
H A Di2c-gpio.txt28 <&gpd1 1 GPIO_ACTIVE_HIGH>; /* CLK */
/openbmc/u-boot/doc/
H A DREADME.m54418twr135 CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
136 INP CLK 50 MHz VCO CLK 500 MHz

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