1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
209f455dcSMasahiro Yamada /*
3722e000cSTom Warren * (C) Copyright 2013-2015
409f455dcSMasahiro Yamada * NVIDIA Corporation <www.nvidia.com>
509f455dcSMasahiro Yamada */
609f455dcSMasahiro Yamada
709f455dcSMasahiro Yamada /* Tegra124 Clock control functions */
809f455dcSMasahiro Yamada
909f455dcSMasahiro Yamada #include <common.h>
1009f455dcSMasahiro Yamada #include <asm/io.h>
1109f455dcSMasahiro Yamada #include <asm/arch/clock.h>
1209f455dcSMasahiro Yamada #include <asm/arch/sysctr.h>
1309f455dcSMasahiro Yamada #include <asm/arch/tegra.h>
1409f455dcSMasahiro Yamada #include <asm/arch-tegra/clk_rst.h>
1509f455dcSMasahiro Yamada #include <asm/arch-tegra/timer.h>
1609f455dcSMasahiro Yamada #include <div64.h>
1709f455dcSMasahiro Yamada #include <fdtdec.h>
1809f455dcSMasahiro Yamada
1909f455dcSMasahiro Yamada /*
2009f455dcSMasahiro Yamada * Clock types that we can use as a source. The Tegra124 has muxes for the
2109f455dcSMasahiro Yamada * peripheral clocks, and in most cases there are four options for the clock
2209f455dcSMasahiro Yamada * source. This gives us a clock 'type' and exploits what commonality exists
2309f455dcSMasahiro Yamada * in the device.
2409f455dcSMasahiro Yamada *
2509f455dcSMasahiro Yamada * Letters are obvious, except for T which means CLK_M, and S which means the
2609f455dcSMasahiro Yamada * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
2709f455dcSMasahiro Yamada * datasheet) and PLL_M are different things. The former is the basic
2809f455dcSMasahiro Yamada * clock supplied to the SOC from an external oscillator. The latter is the
2909f455dcSMasahiro Yamada * memory clock PLL.
3009f455dcSMasahiro Yamada *
3109f455dcSMasahiro Yamada * See definitions in clock_id in the header file.
3209f455dcSMasahiro Yamada */
3309f455dcSMasahiro Yamada enum clock_type_id {
3409f455dcSMasahiro Yamada CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
3509f455dcSMasahiro Yamada CLOCK_TYPE_MCPA, /* and so on */
3609f455dcSMasahiro Yamada CLOCK_TYPE_MCPT,
3709f455dcSMasahiro Yamada CLOCK_TYPE_PCM,
3809f455dcSMasahiro Yamada CLOCK_TYPE_PCMT,
3909f455dcSMasahiro Yamada CLOCK_TYPE_PDCT,
4009f455dcSMasahiro Yamada CLOCK_TYPE_ACPT,
4109f455dcSMasahiro Yamada CLOCK_TYPE_ASPTE,
4209f455dcSMasahiro Yamada CLOCK_TYPE_PMDACD2T,
4309f455dcSMasahiro Yamada CLOCK_TYPE_PCST,
4496e82a25SSimon Glass CLOCK_TYPE_DP,
4509f455dcSMasahiro Yamada
4609f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3M,
4709f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3S_T,
4809f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3M_T,
4909f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
5009f455dcSMasahiro Yamada CLOCK_TYPE_MC2CC3P_A,
5109f455dcSMasahiro Yamada CLOCK_TYPE_M,
5209f455dcSMasahiro Yamada CLOCK_TYPE_MCPTM2C2C3,
5309f455dcSMasahiro Yamada CLOCK_TYPE_PC2CC3T_S,
5409f455dcSMasahiro Yamada CLOCK_TYPE_AC2CC3P_TS2,
5509f455dcSMasahiro Yamada
5609f455dcSMasahiro Yamada CLOCK_TYPE_COUNT,
5709f455dcSMasahiro Yamada CLOCK_TYPE_NONE = -1, /* invalid clock type */
5809f455dcSMasahiro Yamada };
5909f455dcSMasahiro Yamada
6009f455dcSMasahiro Yamada enum {
6109f455dcSMasahiro Yamada CLOCK_MAX_MUX = 8 /* number of source options for each clock */
6209f455dcSMasahiro Yamada };
6309f455dcSMasahiro Yamada
6409f455dcSMasahiro Yamada /*
6509f455dcSMasahiro Yamada * Clock source mux for each clock type. This just converts our enum into
6609f455dcSMasahiro Yamada * a list of mux sources for use by the code.
6709f455dcSMasahiro Yamada *
6809f455dcSMasahiro Yamada * Note:
6909f455dcSMasahiro Yamada * The extra column in each clock source array is used to store the mask
7009f455dcSMasahiro Yamada * bits in its register for the source.
7109f455dcSMasahiro Yamada */
7209f455dcSMasahiro Yamada #define CLK(x) CLOCK_ID_ ## x
7309f455dcSMasahiro Yamada static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
7409f455dcSMasahiro Yamada { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
7509f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
7609f455dcSMasahiro Yamada MASK_BITS_31_30},
7709f455dcSMasahiro Yamada { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
7809f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
7909f455dcSMasahiro Yamada MASK_BITS_31_30},
8009f455dcSMasahiro Yamada { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
8109f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
8209f455dcSMasahiro Yamada MASK_BITS_31_30},
8309f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
8409f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
8509f455dcSMasahiro Yamada MASK_BITS_31_30},
8609f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
8709f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
8809f455dcSMasahiro Yamada MASK_BITS_31_30},
8909f455dcSMasahiro Yamada { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
9009f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
9109f455dcSMasahiro Yamada MASK_BITS_31_30},
9209f455dcSMasahiro Yamada { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
9309f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
9409f455dcSMasahiro Yamada MASK_BITS_31_30},
9509f455dcSMasahiro Yamada { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
9609f455dcSMasahiro Yamada CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
9709f455dcSMasahiro Yamada MASK_BITS_31_29},
9809f455dcSMasahiro Yamada { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
9909f455dcSMasahiro Yamada CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
10009f455dcSMasahiro Yamada MASK_BITS_31_29},
10109f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
10209f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
10309f455dcSMasahiro Yamada MASK_BITS_31_28},
10496e82a25SSimon Glass /* CLOCK_TYPE_DP */
10596e82a25SSimon Glass { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
10696e82a25SSimon Glass CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
10796e82a25SSimon Glass MASK_BITS_31_28},
10809f455dcSMasahiro Yamada
10909f455dcSMasahiro Yamada /* Additional clock types on Tegra114+ */
11009f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3M */
11109f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
11209f455dcSMasahiro Yamada CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
11309f455dcSMasahiro Yamada MASK_BITS_31_29},
11409f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3S_T */
11509f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
11609f455dcSMasahiro Yamada CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
11709f455dcSMasahiro Yamada MASK_BITS_31_29},
11809f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3M_T */
11909f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
12009f455dcSMasahiro Yamada CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
12109f455dcSMasahiro Yamada MASK_BITS_31_29},
12209f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
12309f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
12409f455dcSMasahiro Yamada CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
12509f455dcSMasahiro Yamada MASK_BITS_31_29},
12609f455dcSMasahiro Yamada /* CLOCK_TYPE_MC2CC3P_A */
12709f455dcSMasahiro Yamada { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
12809f455dcSMasahiro Yamada CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
12909f455dcSMasahiro Yamada MASK_BITS_31_29},
13009f455dcSMasahiro Yamada /* CLOCK_TYPE_M */
13109f455dcSMasahiro Yamada { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
13209f455dcSMasahiro Yamada CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
13309f455dcSMasahiro Yamada MASK_BITS_31_30},
13409f455dcSMasahiro Yamada /* CLOCK_TYPE_MCPTM2C2C3 */
13509f455dcSMasahiro Yamada { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
13609f455dcSMasahiro Yamada CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
13709f455dcSMasahiro Yamada MASK_BITS_31_29},
13809f455dcSMasahiro Yamada /* CLOCK_TYPE_PC2CC3T_S */
13909f455dcSMasahiro Yamada { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
14009f455dcSMasahiro Yamada CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
14109f455dcSMasahiro Yamada MASK_BITS_31_29},
14209f455dcSMasahiro Yamada /* CLOCK_TYPE_AC2CC3P_TS2 */
14309f455dcSMasahiro Yamada { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
14409f455dcSMasahiro Yamada CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
14509f455dcSMasahiro Yamada MASK_BITS_31_29},
14609f455dcSMasahiro Yamada };
14709f455dcSMasahiro Yamada
14809f455dcSMasahiro Yamada /*
14909f455dcSMasahiro Yamada * Clock type for each peripheral clock source. We put the name in each
15009f455dcSMasahiro Yamada * record just so it is easy to match things up
15109f455dcSMasahiro Yamada */
15209f455dcSMasahiro Yamada #define TYPE(name, type) type
15309f455dcSMasahiro Yamada static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
15409f455dcSMasahiro Yamada /* 0x00 */
15509f455dcSMasahiro Yamada TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
15609f455dcSMasahiro Yamada TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
15709f455dcSMasahiro Yamada TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
15809f455dcSMasahiro Yamada TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PC2CC3M),
15909f455dcSMasahiro Yamada TYPE(PERIPHC_PWM, CLOCK_TYPE_PC2CC3S_T),
16009f455dcSMasahiro Yamada TYPE(PERIPHC_05h, CLOCK_TYPE_NONE),
16109f455dcSMasahiro Yamada TYPE(PERIPHC_SBC2, CLOCK_TYPE_PC2CC3M_T),
16209f455dcSMasahiro Yamada TYPE(PERIPHC_SBC3, CLOCK_TYPE_PC2CC3M_T),
16309f455dcSMasahiro Yamada
16409f455dcSMasahiro Yamada /* 0x08 */
16509f455dcSMasahiro Yamada TYPE(PERIPHC_08h, CLOCK_TYPE_NONE),
16609f455dcSMasahiro Yamada TYPE(PERIPHC_I2C1, CLOCK_TYPE_PC2CC3M_T16),
16709f455dcSMasahiro Yamada TYPE(PERIPHC_I2C5, CLOCK_TYPE_PC2CC3M_T16),
16809f455dcSMasahiro Yamada TYPE(PERIPHC_0bh, CLOCK_TYPE_NONE),
16909f455dcSMasahiro Yamada TYPE(PERIPHC_0ch, CLOCK_TYPE_NONE),
17009f455dcSMasahiro Yamada TYPE(PERIPHC_SBC1, CLOCK_TYPE_PC2CC3M_T),
17109f455dcSMasahiro Yamada TYPE(PERIPHC_DISP1, CLOCK_TYPE_PMDACD2T),
17209f455dcSMasahiro Yamada TYPE(PERIPHC_DISP2, CLOCK_TYPE_PMDACD2T),
17309f455dcSMasahiro Yamada
17409f455dcSMasahiro Yamada /* 0x10 */
17509f455dcSMasahiro Yamada TYPE(PERIPHC_10h, CLOCK_TYPE_NONE),
17609f455dcSMasahiro Yamada TYPE(PERIPHC_11h, CLOCK_TYPE_NONE),
17709f455dcSMasahiro Yamada TYPE(PERIPHC_VI, CLOCK_TYPE_MC2CC3P_A),
17809f455dcSMasahiro Yamada TYPE(PERIPHC_13h, CLOCK_TYPE_NONE),
17909f455dcSMasahiro Yamada TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PC2CC3M_T),
18009f455dcSMasahiro Yamada TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PC2CC3M_T),
18109f455dcSMasahiro Yamada TYPE(PERIPHC_16h, CLOCK_TYPE_NONE),
18209f455dcSMasahiro Yamada TYPE(PERIPHC_17h, CLOCK_TYPE_NONE),
18309f455dcSMasahiro Yamada
18409f455dcSMasahiro Yamada /* 0x18 */
18509f455dcSMasahiro Yamada TYPE(PERIPHC_18h, CLOCK_TYPE_NONE),
18609f455dcSMasahiro Yamada TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PC2CC3M_T),
18709f455dcSMasahiro Yamada TYPE(PERIPHC_VFIR, CLOCK_TYPE_PC2CC3M_T),
18809f455dcSMasahiro Yamada TYPE(PERIPHC_1Bh, CLOCK_TYPE_NONE),
18909f455dcSMasahiro Yamada TYPE(PERIPHC_1Ch, CLOCK_TYPE_NONE),
19009f455dcSMasahiro Yamada TYPE(PERIPHC_HSI, CLOCK_TYPE_PC2CC3M_T),
19109f455dcSMasahiro Yamada TYPE(PERIPHC_UART1, CLOCK_TYPE_PC2CC3M_T),
19209f455dcSMasahiro Yamada TYPE(PERIPHC_UART2, CLOCK_TYPE_PC2CC3M_T),
19309f455dcSMasahiro Yamada
19409f455dcSMasahiro Yamada /* 0x20 */
19509f455dcSMasahiro Yamada TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MC2CC3P_A),
19609f455dcSMasahiro Yamada TYPE(PERIPHC_21h, CLOCK_TYPE_NONE),
19709f455dcSMasahiro Yamada TYPE(PERIPHC_22h, CLOCK_TYPE_NONE),
19809f455dcSMasahiro Yamada TYPE(PERIPHC_HDMI, CLOCK_TYPE_PMDACD2T),
19909f455dcSMasahiro Yamada TYPE(PERIPHC_24h, CLOCK_TYPE_NONE),
20009f455dcSMasahiro Yamada TYPE(PERIPHC_25h, CLOCK_TYPE_NONE),
20109f455dcSMasahiro Yamada TYPE(PERIPHC_I2C2, CLOCK_TYPE_PC2CC3M_T16),
20209f455dcSMasahiro Yamada TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPTM2C2C3),
20309f455dcSMasahiro Yamada
20409f455dcSMasahiro Yamada /* 0x28 */
20509f455dcSMasahiro Yamada TYPE(PERIPHC_UART3, CLOCK_TYPE_PC2CC3M_T),
20609f455dcSMasahiro Yamada TYPE(PERIPHC_29h, CLOCK_TYPE_NONE),
20709f455dcSMasahiro Yamada TYPE(PERIPHC_VI_SENSOR, CLOCK_TYPE_MC2CC3P_A),
20809f455dcSMasahiro Yamada TYPE(PERIPHC_2bh, CLOCK_TYPE_NONE),
20909f455dcSMasahiro Yamada TYPE(PERIPHC_2ch, CLOCK_TYPE_NONE),
21009f455dcSMasahiro Yamada TYPE(PERIPHC_SBC4, CLOCK_TYPE_PC2CC3M_T),
21109f455dcSMasahiro Yamada TYPE(PERIPHC_I2C3, CLOCK_TYPE_PC2CC3M_T16),
21209f455dcSMasahiro Yamada TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PC2CC3M_T),
21309f455dcSMasahiro Yamada
21409f455dcSMasahiro Yamada /* 0x30 */
21509f455dcSMasahiro Yamada TYPE(PERIPHC_UART4, CLOCK_TYPE_PC2CC3M_T),
21609f455dcSMasahiro Yamada TYPE(PERIPHC_UART5, CLOCK_TYPE_PC2CC3M_T),
21709f455dcSMasahiro Yamada TYPE(PERIPHC_VDE, CLOCK_TYPE_PC2CC3M_T),
21809f455dcSMasahiro Yamada TYPE(PERIPHC_OWR, CLOCK_TYPE_PC2CC3M_T),
21909f455dcSMasahiro Yamada TYPE(PERIPHC_NOR, CLOCK_TYPE_PC2CC3M_T),
22009f455dcSMasahiro Yamada TYPE(PERIPHC_CSITE, CLOCK_TYPE_PC2CC3M_T),
22109f455dcSMasahiro Yamada TYPE(PERIPHC_I2S0, CLOCK_TYPE_AXPT),
22209f455dcSMasahiro Yamada TYPE(PERIPHC_DTV, CLOCK_TYPE_NONE),
22309f455dcSMasahiro Yamada
22409f455dcSMasahiro Yamada /* 0x38 */
22509f455dcSMasahiro Yamada TYPE(PERIPHC_38h, CLOCK_TYPE_NONE),
22609f455dcSMasahiro Yamada TYPE(PERIPHC_39h, CLOCK_TYPE_NONE),
22709f455dcSMasahiro Yamada TYPE(PERIPHC_3ah, CLOCK_TYPE_NONE),
22809f455dcSMasahiro Yamada TYPE(PERIPHC_3bh, CLOCK_TYPE_NONE),
22909f455dcSMasahiro Yamada TYPE(PERIPHC_MSENC, CLOCK_TYPE_MC2CC3P_A),
23009f455dcSMasahiro Yamada TYPE(PERIPHC_TSEC, CLOCK_TYPE_PC2CC3M_T),
23109f455dcSMasahiro Yamada TYPE(PERIPHC_3eh, CLOCK_TYPE_NONE),
23209f455dcSMasahiro Yamada TYPE(PERIPHC_OSC, CLOCK_TYPE_NONE),
23309f455dcSMasahiro Yamada
23409f455dcSMasahiro Yamada /* 0x40 */
23509f455dcSMasahiro Yamada TYPE(PERIPHC_40h, CLOCK_TYPE_NONE), /* start with 0x3b0 */
23609f455dcSMasahiro Yamada TYPE(PERIPHC_MSELECT, CLOCK_TYPE_PC2CC3M_T),
23709f455dcSMasahiro Yamada TYPE(PERIPHC_TSENSOR, CLOCK_TYPE_PC2CC3T_S),
23809f455dcSMasahiro Yamada TYPE(PERIPHC_I2S3, CLOCK_TYPE_AXPT),
23909f455dcSMasahiro Yamada TYPE(PERIPHC_I2S4, CLOCK_TYPE_AXPT),
24009f455dcSMasahiro Yamada TYPE(PERIPHC_I2C4, CLOCK_TYPE_PC2CC3M_T16),
24109f455dcSMasahiro Yamada TYPE(PERIPHC_SBC5, CLOCK_TYPE_PC2CC3M_T),
24209f455dcSMasahiro Yamada TYPE(PERIPHC_SBC6, CLOCK_TYPE_PC2CC3M_T),
24309f455dcSMasahiro Yamada
24409f455dcSMasahiro Yamada /* 0x48 */
24509f455dcSMasahiro Yamada TYPE(PERIPHC_AUDIO, CLOCK_TYPE_AC2CC3P_TS2),
24609f455dcSMasahiro Yamada TYPE(PERIPHC_49h, CLOCK_TYPE_NONE),
24709f455dcSMasahiro Yamada TYPE(PERIPHC_DAM0, CLOCK_TYPE_AC2CC3P_TS2),
24809f455dcSMasahiro Yamada TYPE(PERIPHC_DAM1, CLOCK_TYPE_AC2CC3P_TS2),
24909f455dcSMasahiro Yamada TYPE(PERIPHC_DAM2, CLOCK_TYPE_AC2CC3P_TS2),
25009f455dcSMasahiro Yamada TYPE(PERIPHC_HDA2CODEC2X, CLOCK_TYPE_PC2CC3M_T),
25109f455dcSMasahiro Yamada TYPE(PERIPHC_ACTMON, CLOCK_TYPE_PC2CC3S_T),
25209f455dcSMasahiro Yamada TYPE(PERIPHC_EXTPERIPH1, CLOCK_TYPE_ASPTE),
25309f455dcSMasahiro Yamada
25409f455dcSMasahiro Yamada /* 0x50 */
25509f455dcSMasahiro Yamada TYPE(PERIPHC_EXTPERIPH2, CLOCK_TYPE_ASPTE),
25609f455dcSMasahiro Yamada TYPE(PERIPHC_EXTPERIPH3, CLOCK_TYPE_ASPTE),
25709f455dcSMasahiro Yamada TYPE(PERIPHC_52h, CLOCK_TYPE_NONE),
25809f455dcSMasahiro Yamada TYPE(PERIPHC_I2CSLOW, CLOCK_TYPE_PC2CC3S_T),
25909f455dcSMasahiro Yamada TYPE(PERIPHC_SYS, CLOCK_TYPE_NONE),
26009f455dcSMasahiro Yamada TYPE(PERIPHC_55h, CLOCK_TYPE_NONE),
26109f455dcSMasahiro Yamada TYPE(PERIPHC_56h, CLOCK_TYPE_NONE),
26209f455dcSMasahiro Yamada TYPE(PERIPHC_57h, CLOCK_TYPE_NONE),
26309f455dcSMasahiro Yamada
26409f455dcSMasahiro Yamada /* 0x58 */
26509f455dcSMasahiro Yamada TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
26696e82a25SSimon Glass TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE),
26709f455dcSMasahiro Yamada TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
26809f455dcSMasahiro Yamada TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
26909f455dcSMasahiro Yamada TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
27009f455dcSMasahiro Yamada TYPE(PERIPHC_SATA, CLOCK_TYPE_PCMT),
27109f455dcSMasahiro Yamada TYPE(PERIPHC_HDA, CLOCK_TYPE_PC2CC3M_T),
27209f455dcSMasahiro Yamada TYPE(PERIPHC_5fh, CLOCK_TYPE_NONE),
27309f455dcSMasahiro Yamada
27409f455dcSMasahiro Yamada /* 0x60 */
27509f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_CORE_HOST, CLOCK_TYPE_NONE),
27609f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_FALCON, CLOCK_TYPE_NONE),
27709f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_FS, CLOCK_TYPE_NONE),
27809f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_CORE_DEV, CLOCK_TYPE_NONE),
27909f455dcSMasahiro Yamada TYPE(PERIPHC_XUSB_SS, CLOCK_TYPE_NONE),
28009f455dcSMasahiro Yamada TYPE(PERIPHC_CILAB, CLOCK_TYPE_NONE),
28109f455dcSMasahiro Yamada TYPE(PERIPHC_CILCD, CLOCK_TYPE_NONE),
28209f455dcSMasahiro Yamada TYPE(PERIPHC_CILE, CLOCK_TYPE_NONE),
28309f455dcSMasahiro Yamada
28409f455dcSMasahiro Yamada /* 0x68 */
28509f455dcSMasahiro Yamada TYPE(PERIPHC_DSIA_LP, CLOCK_TYPE_NONE),
28609f455dcSMasahiro Yamada TYPE(PERIPHC_DSIB_LP, CLOCK_TYPE_NONE),
28709f455dcSMasahiro Yamada TYPE(PERIPHC_ENTROPY, CLOCK_TYPE_NONE),
28809f455dcSMasahiro Yamada TYPE(PERIPHC_DVFS_REF, CLOCK_TYPE_NONE),
28909f455dcSMasahiro Yamada TYPE(PERIPHC_DVFS_SOC, CLOCK_TYPE_NONE),
29009f455dcSMasahiro Yamada TYPE(PERIPHC_TRACECLKIN, CLOCK_TYPE_NONE),
29109f455dcSMasahiro Yamada TYPE(PERIPHC_ADX0, CLOCK_TYPE_NONE),
29209f455dcSMasahiro Yamada TYPE(PERIPHC_AMX0, CLOCK_TYPE_NONE),
29309f455dcSMasahiro Yamada
29409f455dcSMasahiro Yamada /* 0x70 */
29509f455dcSMasahiro Yamada TYPE(PERIPHC_EMC_LATENCY, CLOCK_TYPE_NONE),
29609f455dcSMasahiro Yamada TYPE(PERIPHC_SOC_THERM, CLOCK_TYPE_NONE),
29709f455dcSMasahiro Yamada TYPE(PERIPHC_72h, CLOCK_TYPE_NONE),
29809f455dcSMasahiro Yamada TYPE(PERIPHC_73h, CLOCK_TYPE_NONE),
29909f455dcSMasahiro Yamada TYPE(PERIPHC_74h, CLOCK_TYPE_NONE),
30009f455dcSMasahiro Yamada TYPE(PERIPHC_75h, CLOCK_TYPE_NONE),
30109f455dcSMasahiro Yamada TYPE(PERIPHC_VI_SENSOR2, CLOCK_TYPE_NONE),
30209f455dcSMasahiro Yamada TYPE(PERIPHC_I2C6, CLOCK_TYPE_PC2CC3M_T16),
30309f455dcSMasahiro Yamada
30409f455dcSMasahiro Yamada /* 0x78 */
30509f455dcSMasahiro Yamada TYPE(PERIPHC_78h, CLOCK_TYPE_NONE),
30609f455dcSMasahiro Yamada TYPE(PERIPHC_EMC_DLL, CLOCK_TYPE_MCPTM2C2C3),
30709f455dcSMasahiro Yamada TYPE(PERIPHC_HDMI_AUDIO, CLOCK_TYPE_NONE),
30809f455dcSMasahiro Yamada TYPE(PERIPHC_CLK72MHZ, CLOCK_TYPE_NONE),
30909f455dcSMasahiro Yamada TYPE(PERIPHC_ADX1, CLOCK_TYPE_AC2CC3P_TS2),
31009f455dcSMasahiro Yamada TYPE(PERIPHC_AMX1, CLOCK_TYPE_AC2CC3P_TS2),
31109f455dcSMasahiro Yamada TYPE(PERIPHC_VIC, CLOCK_TYPE_NONE),
31209f455dcSMasahiro Yamada TYPE(PERIPHC_7Fh, CLOCK_TYPE_NONE),
31309f455dcSMasahiro Yamada };
31409f455dcSMasahiro Yamada
31509f455dcSMasahiro Yamada /*
31609f455dcSMasahiro Yamada * This array translates a periph_id to a periphc_internal_id
31709f455dcSMasahiro Yamada *
31809f455dcSMasahiro Yamada * Not present/matched up:
31909f455dcSMasahiro Yamada * uint vi_sensor; _VI_SENSOR_0, 0x1A8
32009f455dcSMasahiro Yamada * SPDIF - which is both 0x08 and 0x0c
32109f455dcSMasahiro Yamada *
32209f455dcSMasahiro Yamada */
32309f455dcSMasahiro Yamada #define NONE(name) (-1)
32409f455dcSMasahiro Yamada #define OFFSET(name, value) PERIPHC_ ## name
32509f455dcSMasahiro Yamada static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
32609f455dcSMasahiro Yamada /* Low word: 31:0 */
32709f455dcSMasahiro Yamada NONE(CPU),
32809f455dcSMasahiro Yamada NONE(COP),
32909f455dcSMasahiro Yamada NONE(TRIGSYS),
33009f455dcSMasahiro Yamada NONE(ISPB),
33109f455dcSMasahiro Yamada NONE(RESERVED4),
33209f455dcSMasahiro Yamada NONE(TMR),
33309f455dcSMasahiro Yamada PERIPHC_UART1,
33409f455dcSMasahiro Yamada PERIPHC_UART2, /* and vfir 0x68 */
33509f455dcSMasahiro Yamada
33609f455dcSMasahiro Yamada /* 8 */
33709f455dcSMasahiro Yamada NONE(GPIO),
33809f455dcSMasahiro Yamada PERIPHC_SDMMC2,
33909f455dcSMasahiro Yamada PERIPHC_SPDIF_IN,
34009f455dcSMasahiro Yamada PERIPHC_I2S1,
34109f455dcSMasahiro Yamada PERIPHC_I2C1,
34209f455dcSMasahiro Yamada NONE(RESERVED13),
34309f455dcSMasahiro Yamada PERIPHC_SDMMC1,
34409f455dcSMasahiro Yamada PERIPHC_SDMMC4,
34509f455dcSMasahiro Yamada
34609f455dcSMasahiro Yamada /* 16 */
34709f455dcSMasahiro Yamada NONE(TCW),
34809f455dcSMasahiro Yamada PERIPHC_PWM,
34909f455dcSMasahiro Yamada PERIPHC_I2S2,
35009f455dcSMasahiro Yamada NONE(RESERVED19),
35109f455dcSMasahiro Yamada PERIPHC_VI,
35209f455dcSMasahiro Yamada NONE(RESERVED21),
35309f455dcSMasahiro Yamada NONE(USBD),
35409f455dcSMasahiro Yamada NONE(ISP),
35509f455dcSMasahiro Yamada
35609f455dcSMasahiro Yamada /* 24 */
35709f455dcSMasahiro Yamada NONE(RESERVED24),
35809f455dcSMasahiro Yamada NONE(RESERVED25),
35909f455dcSMasahiro Yamada PERIPHC_DISP2,
36009f455dcSMasahiro Yamada PERIPHC_DISP1,
36109f455dcSMasahiro Yamada PERIPHC_HOST1X,
36209f455dcSMasahiro Yamada NONE(VCP),
36309f455dcSMasahiro Yamada PERIPHC_I2S0,
36409f455dcSMasahiro Yamada NONE(CACHE2),
36509f455dcSMasahiro Yamada
36609f455dcSMasahiro Yamada /* Middle word: 63:32 */
36709f455dcSMasahiro Yamada NONE(MEM),
36809f455dcSMasahiro Yamada NONE(AHBDMA),
36909f455dcSMasahiro Yamada NONE(APBDMA),
37009f455dcSMasahiro Yamada NONE(RESERVED35),
37109f455dcSMasahiro Yamada NONE(RESERVED36),
37209f455dcSMasahiro Yamada NONE(STAT_MON),
37309f455dcSMasahiro Yamada NONE(RESERVED38),
37409f455dcSMasahiro Yamada NONE(FUSE),
37509f455dcSMasahiro Yamada
37609f455dcSMasahiro Yamada /* 40 */
37709f455dcSMasahiro Yamada NONE(KFUSE),
37809f455dcSMasahiro Yamada PERIPHC_SBC1, /* SBCx = SPIx */
37909f455dcSMasahiro Yamada PERIPHC_NOR,
38009f455dcSMasahiro Yamada NONE(RESERVED43),
38109f455dcSMasahiro Yamada PERIPHC_SBC2,
38209f455dcSMasahiro Yamada NONE(XIO),
38309f455dcSMasahiro Yamada PERIPHC_SBC3,
38409f455dcSMasahiro Yamada PERIPHC_I2C5,
38509f455dcSMasahiro Yamada
38609f455dcSMasahiro Yamada /* 48 */
38709f455dcSMasahiro Yamada NONE(DSI),
38809f455dcSMasahiro Yamada NONE(RESERVED49),
38909f455dcSMasahiro Yamada PERIPHC_HSI,
39009f455dcSMasahiro Yamada PERIPHC_HDMI,
39109f455dcSMasahiro Yamada NONE(CSI),
39209f455dcSMasahiro Yamada NONE(RESERVED53),
39309f455dcSMasahiro Yamada PERIPHC_I2C2,
39409f455dcSMasahiro Yamada PERIPHC_UART3,
39509f455dcSMasahiro Yamada
39609f455dcSMasahiro Yamada /* 56 */
39709f455dcSMasahiro Yamada NONE(MIPI_CAL),
39809f455dcSMasahiro Yamada PERIPHC_EMC,
39909f455dcSMasahiro Yamada NONE(USB2),
40009f455dcSMasahiro Yamada NONE(USB3),
40109f455dcSMasahiro Yamada NONE(RESERVED60),
40209f455dcSMasahiro Yamada PERIPHC_VDE,
40309f455dcSMasahiro Yamada NONE(BSEA),
40409f455dcSMasahiro Yamada NONE(BSEV),
40509f455dcSMasahiro Yamada
40609f455dcSMasahiro Yamada /* Upper word 95:64 */
40709f455dcSMasahiro Yamada NONE(RESERVED64),
40809f455dcSMasahiro Yamada PERIPHC_UART4,
40909f455dcSMasahiro Yamada PERIPHC_UART5,
41009f455dcSMasahiro Yamada PERIPHC_I2C3,
41109f455dcSMasahiro Yamada PERIPHC_SBC4,
41209f455dcSMasahiro Yamada PERIPHC_SDMMC3,
41309f455dcSMasahiro Yamada NONE(PCIE),
41409f455dcSMasahiro Yamada PERIPHC_OWR,
41509f455dcSMasahiro Yamada
41609f455dcSMasahiro Yamada /* 72 */
41709f455dcSMasahiro Yamada NONE(AFI),
41809f455dcSMasahiro Yamada PERIPHC_CSITE,
41909f455dcSMasahiro Yamada NONE(PCIEXCLK),
42009f455dcSMasahiro Yamada NONE(AVPUCQ),
42109f455dcSMasahiro Yamada NONE(LA),
42209f455dcSMasahiro Yamada NONE(TRACECLKIN),
42309f455dcSMasahiro Yamada NONE(SOC_THERM),
42409f455dcSMasahiro Yamada NONE(DTV),
42509f455dcSMasahiro Yamada
42609f455dcSMasahiro Yamada /* 80 */
42709f455dcSMasahiro Yamada NONE(RESERVED80),
42809f455dcSMasahiro Yamada PERIPHC_I2CSLOW,
42909f455dcSMasahiro Yamada NONE(DSIB),
43009f455dcSMasahiro Yamada PERIPHC_TSEC,
43109f455dcSMasahiro Yamada NONE(RESERVED84),
43209f455dcSMasahiro Yamada NONE(RESERVED85),
43309f455dcSMasahiro Yamada NONE(RESERVED86),
43409f455dcSMasahiro Yamada NONE(EMUCIF),
43509f455dcSMasahiro Yamada
43609f455dcSMasahiro Yamada /* 88 */
43709f455dcSMasahiro Yamada NONE(RESERVED88),
43809f455dcSMasahiro Yamada NONE(XUSB_HOST),
43909f455dcSMasahiro Yamada NONE(RESERVED90),
44009f455dcSMasahiro Yamada PERIPHC_MSENC,
44109f455dcSMasahiro Yamada NONE(RESERVED92),
44209f455dcSMasahiro Yamada NONE(RESERVED93),
44309f455dcSMasahiro Yamada NONE(RESERVED94),
44409f455dcSMasahiro Yamada NONE(XUSB_DEV),
44509f455dcSMasahiro Yamada
44609f455dcSMasahiro Yamada /* V word: 31:0 */
44709f455dcSMasahiro Yamada NONE(CPUG),
44809f455dcSMasahiro Yamada NONE(CPULP),
44909f455dcSMasahiro Yamada NONE(V_RESERVED2),
45009f455dcSMasahiro Yamada PERIPHC_MSELECT,
45109f455dcSMasahiro Yamada NONE(V_RESERVED4),
45209f455dcSMasahiro Yamada PERIPHC_I2S3,
45309f455dcSMasahiro Yamada PERIPHC_I2S4,
45409f455dcSMasahiro Yamada PERIPHC_I2C4,
45509f455dcSMasahiro Yamada
45609f455dcSMasahiro Yamada /* 104 */
45709f455dcSMasahiro Yamada PERIPHC_SBC5,
45809f455dcSMasahiro Yamada PERIPHC_SBC6,
45909f455dcSMasahiro Yamada PERIPHC_AUDIO,
46009f455dcSMasahiro Yamada NONE(APBIF),
46109f455dcSMasahiro Yamada PERIPHC_DAM0,
46209f455dcSMasahiro Yamada PERIPHC_DAM1,
46309f455dcSMasahiro Yamada PERIPHC_DAM2,
46409f455dcSMasahiro Yamada PERIPHC_HDA2CODEC2X,
46509f455dcSMasahiro Yamada
46609f455dcSMasahiro Yamada /* 112 */
46709f455dcSMasahiro Yamada NONE(ATOMICS),
46809f455dcSMasahiro Yamada NONE(V_RESERVED17),
46909f455dcSMasahiro Yamada NONE(V_RESERVED18),
47009f455dcSMasahiro Yamada NONE(V_RESERVED19),
47109f455dcSMasahiro Yamada NONE(V_RESERVED20),
47209f455dcSMasahiro Yamada NONE(V_RESERVED21),
47309f455dcSMasahiro Yamada NONE(V_RESERVED22),
47409f455dcSMasahiro Yamada PERIPHC_ACTMON,
47509f455dcSMasahiro Yamada
47609f455dcSMasahiro Yamada /* 120 */
477057772b7SSimon Glass PERIPHC_EXTPERIPH1,
47809f455dcSMasahiro Yamada NONE(EXTPERIPH2),
47909f455dcSMasahiro Yamada NONE(EXTPERIPH3),
48009f455dcSMasahiro Yamada NONE(OOB),
48109f455dcSMasahiro Yamada PERIPHC_SATA,
48209f455dcSMasahiro Yamada PERIPHC_HDA,
48309f455dcSMasahiro Yamada NONE(TZRAM),
48409f455dcSMasahiro Yamada NONE(SE),
48509f455dcSMasahiro Yamada
48609f455dcSMasahiro Yamada /* W word: 31:0 */
48709f455dcSMasahiro Yamada NONE(HDA2HDMICODEC),
48809f455dcSMasahiro Yamada NONE(SATACOLD),
48909f455dcSMasahiro Yamada NONE(W_RESERVED2),
49009f455dcSMasahiro Yamada NONE(W_RESERVED3),
49109f455dcSMasahiro Yamada NONE(W_RESERVED4),
49209f455dcSMasahiro Yamada NONE(W_RESERVED5),
49309f455dcSMasahiro Yamada NONE(W_RESERVED6),
49409f455dcSMasahiro Yamada NONE(W_RESERVED7),
49509f455dcSMasahiro Yamada
49609f455dcSMasahiro Yamada /* 136 */
49709f455dcSMasahiro Yamada NONE(CEC),
49809f455dcSMasahiro Yamada NONE(W_RESERVED9),
49909f455dcSMasahiro Yamada NONE(W_RESERVED10),
50009f455dcSMasahiro Yamada NONE(W_RESERVED11),
50109f455dcSMasahiro Yamada NONE(W_RESERVED12),
50209f455dcSMasahiro Yamada NONE(W_RESERVED13),
50309f455dcSMasahiro Yamada NONE(XUSB_PADCTL),
50409f455dcSMasahiro Yamada NONE(W_RESERVED15),
50509f455dcSMasahiro Yamada
50609f455dcSMasahiro Yamada /* 144 */
50709f455dcSMasahiro Yamada NONE(W_RESERVED16),
50809f455dcSMasahiro Yamada NONE(W_RESERVED17),
50909f455dcSMasahiro Yamada NONE(W_RESERVED18),
51009f455dcSMasahiro Yamada NONE(W_RESERVED19),
51109f455dcSMasahiro Yamada NONE(W_RESERVED20),
51209f455dcSMasahiro Yamada NONE(ENTROPY),
51309f455dcSMasahiro Yamada NONE(DDS),
51409f455dcSMasahiro Yamada NONE(W_RESERVED23),
51509f455dcSMasahiro Yamada
51609f455dcSMasahiro Yamada /* 152 */
51709f455dcSMasahiro Yamada NONE(DP2),
51809f455dcSMasahiro Yamada NONE(AMX0),
51909f455dcSMasahiro Yamada NONE(ADX0),
52009f455dcSMasahiro Yamada NONE(DVFS),
52109f455dcSMasahiro Yamada NONE(XUSB_SS),
52209f455dcSMasahiro Yamada NONE(W_RESERVED29),
52309f455dcSMasahiro Yamada NONE(W_RESERVED30),
52409f455dcSMasahiro Yamada NONE(W_RESERVED31),
52509f455dcSMasahiro Yamada
52609f455dcSMasahiro Yamada /* X word: 31:0 */
52709f455dcSMasahiro Yamada NONE(SPARE),
52809f455dcSMasahiro Yamada NONE(X_RESERVED1),
52909f455dcSMasahiro Yamada NONE(X_RESERVED2),
53009f455dcSMasahiro Yamada NONE(X_RESERVED3),
53109f455dcSMasahiro Yamada NONE(CAM_MCLK),
53209f455dcSMasahiro Yamada NONE(CAM_MCLK2),
53309f455dcSMasahiro Yamada PERIPHC_I2C6,
53409f455dcSMasahiro Yamada NONE(X_RESERVED7),
53509f455dcSMasahiro Yamada
53609f455dcSMasahiro Yamada /* 168 */
53709f455dcSMasahiro Yamada NONE(X_RESERVED8),
53809f455dcSMasahiro Yamada NONE(X_RESERVED9),
53909f455dcSMasahiro Yamada NONE(X_RESERVED10),
54009f455dcSMasahiro Yamada NONE(VIM2_CLK),
54109f455dcSMasahiro Yamada NONE(X_RESERVED12),
54209f455dcSMasahiro Yamada NONE(X_RESERVED13),
54309f455dcSMasahiro Yamada NONE(EMC_DLL),
54409f455dcSMasahiro Yamada NONE(X_RESERVED15),
54509f455dcSMasahiro Yamada
54609f455dcSMasahiro Yamada /* 176 */
54709f455dcSMasahiro Yamada NONE(HDMI_AUDIO),
54809f455dcSMasahiro Yamada NONE(CLK72MHZ),
54909f455dcSMasahiro Yamada NONE(VIC),
55009f455dcSMasahiro Yamada NONE(X_RESERVED19),
55109f455dcSMasahiro Yamada NONE(ADX1),
55209f455dcSMasahiro Yamada NONE(DPAUX),
55396e82a25SSimon Glass PERIPHC_SOR,
55409f455dcSMasahiro Yamada NONE(X_RESERVED23),
55509f455dcSMasahiro Yamada
55609f455dcSMasahiro Yamada /* 184 */
55709f455dcSMasahiro Yamada NONE(GPU),
55809f455dcSMasahiro Yamada NONE(AMX1),
55909f455dcSMasahiro Yamada NONE(X_RESERVED26),
56009f455dcSMasahiro Yamada NONE(X_RESERVED27),
56109f455dcSMasahiro Yamada NONE(X_RESERVED28),
56209f455dcSMasahiro Yamada NONE(X_RESERVED29),
56309f455dcSMasahiro Yamada NONE(X_RESERVED30),
56409f455dcSMasahiro Yamada NONE(X_RESERVED31),
56509f455dcSMasahiro Yamada };
56609f455dcSMasahiro Yamada
56709f455dcSMasahiro Yamada /*
568722e000cSTom Warren * PLL divider shift/mask tables for all PLL IDs.
569722e000cSTom Warren */
570722e000cSTom Warren struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
571722e000cSTom Warren /*
5725a30cee5SSimon Glass * T124: same as T114, some deviations from T2x/T30. Adds PLLDP.
573722e000cSTom Warren * NOTE: If kcp_mask/kvco_mask == 0, they're not used in that PLL (PLLX, etc.)
574722e000cSTom Warren * If lock_ena or lock_det are >31, they're not used in that PLL.
575722e000cSTom Warren */
576722e000cSTom Warren
577722e000cSTom Warren { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
578722e000cSTom Warren .lock_ena = 24, .lock_det = 27, .kcp_shift = 28, .kcp_mask = 3, .kvco_shift = 27, .kvco_mask = 1 }, /* PLLC */
579722e000cSTom Warren { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
580722e000cSTom Warren .lock_ena = 0, .lock_det = 27, .kcp_shift = 1, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLM */
581722e000cSTom Warren { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
582722e000cSTom Warren .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLP */
583722e000cSTom Warren { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
584722e000cSTom Warren .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLA */
585722e000cSTom Warren { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
586722e000cSTom Warren .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLU */
587722e000cSTom Warren { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
588722e000cSTom Warren .lock_ena = 22, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLD */
589722e000cSTom Warren { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
590722e000cSTom Warren .lock_ena = 18, .lock_det = 27, .kcp_shift = 0, .kcp_mask = 0, .kvco_shift = 0, .kvco_mask = 0 }, /* PLLX */
591722e000cSTom Warren { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
592722e000cSTom Warren .lock_ena = 9, .lock_det = 11, .kcp_shift = 6, .kcp_mask = 3, .kvco_shift = 0, .kvco_mask = 1 }, /* PLLE */
593722e000cSTom Warren { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
594722e000cSTom Warren .lock_ena = 18, .lock_det = 27, .kcp_shift = 8, .kcp_mask = 0xF, .kvco_shift = 4, .kvco_mask = 0xF }, /* PLLS (RESERVED) */
5955a30cee5SSimon Glass { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
5965a30cee5SSimon Glass .lock_ena = 30, .lock_det = 27, .kcp_shift = 25, .kcp_mask = 3, .kvco_shift = 24, .kvco_mask = 1 }, /* PLLDP */
597722e000cSTom Warren };
598722e000cSTom Warren
599722e000cSTom Warren /*
60009f455dcSMasahiro Yamada * Get the oscillator frequency, from the corresponding hardware configuration
60109f455dcSMasahiro Yamada * field. Note that Tegra30+ support 3 new higher freqs, but we map back
60209f455dcSMasahiro Yamada * to the old T20 freqs. Support for the higher oscillators is TBD.
60309f455dcSMasahiro Yamada */
clock_get_osc_freq(void)60409f455dcSMasahiro Yamada enum clock_osc_freq clock_get_osc_freq(void)
60509f455dcSMasahiro Yamada {
60609f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst =
60709f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
60809f455dcSMasahiro Yamada u32 reg;
60909f455dcSMasahiro Yamada
61009f455dcSMasahiro Yamada reg = readl(&clkrst->crc_osc_ctrl);
61109f455dcSMasahiro Yamada reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
61209f455dcSMasahiro Yamada
61309f455dcSMasahiro Yamada if (reg & 1) /* one of the newer freqs */
61409f455dcSMasahiro Yamada printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
61509f455dcSMasahiro Yamada
61609f455dcSMasahiro Yamada return reg >> 2; /* Map to most common (T20) freqs */
61709f455dcSMasahiro Yamada }
61809f455dcSMasahiro Yamada
61909f455dcSMasahiro Yamada /* Returns a pointer to the clock source register for a peripheral */
get_periph_source_reg(enum periph_id periph_id)62009f455dcSMasahiro Yamada u32 *get_periph_source_reg(enum periph_id periph_id)
62109f455dcSMasahiro Yamada {
62209f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst =
62309f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
62409f455dcSMasahiro Yamada enum periphc_internal_id internal_id;
62509f455dcSMasahiro Yamada
62609f455dcSMasahiro Yamada /* Coresight is a special case */
62709f455dcSMasahiro Yamada if (periph_id == PERIPH_ID_CSI)
62809f455dcSMasahiro Yamada return &clkrst->crc_clk_src[PERIPH_ID_CSI+1];
62909f455dcSMasahiro Yamada
63009f455dcSMasahiro Yamada assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
63109f455dcSMasahiro Yamada internal_id = periph_id_to_internal_id[periph_id];
63209f455dcSMasahiro Yamada assert(internal_id != -1);
63396e82a25SSimon Glass if (internal_id >= PERIPHC_X_FIRST) {
63496e82a25SSimon Glass internal_id -= PERIPHC_X_FIRST;
63596e82a25SSimon Glass return &clkrst->crc_clk_src_x[internal_id];
63696e82a25SSimon Glass } else if (internal_id >= PERIPHC_VW_FIRST) {
63709f455dcSMasahiro Yamada internal_id -= PERIPHC_VW_FIRST;
63809f455dcSMasahiro Yamada return &clkrst->crc_clk_src_vw[internal_id];
63909f455dcSMasahiro Yamada } else {
64009f455dcSMasahiro Yamada return &clkrst->crc_clk_src[internal_id];
64109f455dcSMasahiro Yamada }
64209f455dcSMasahiro Yamada }
64309f455dcSMasahiro Yamada
get_periph_clock_info(enum periph_id periph_id,int * mux_bits,int * divider_bits,int * type)644d0ad8a5cSStephen Warren int get_periph_clock_info(enum periph_id periph_id, int *mux_bits,
645d0ad8a5cSStephen Warren int *divider_bits, int *type)
646d0ad8a5cSStephen Warren {
647d0ad8a5cSStephen Warren enum periphc_internal_id internal_id;
648d0ad8a5cSStephen Warren
649d0ad8a5cSStephen Warren if (!clock_periph_id_isvalid(periph_id))
650d0ad8a5cSStephen Warren return -1;
651d0ad8a5cSStephen Warren
652d0ad8a5cSStephen Warren internal_id = periph_id_to_internal_id[periph_id];
653d0ad8a5cSStephen Warren if (!periphc_internal_id_isvalid(internal_id))
654d0ad8a5cSStephen Warren return -1;
655d0ad8a5cSStephen Warren
656d0ad8a5cSStephen Warren *type = clock_periph_type[internal_id];
657d0ad8a5cSStephen Warren if (!clock_type_id_isvalid(*type))
658d0ad8a5cSStephen Warren return -1;
659d0ad8a5cSStephen Warren
660d0ad8a5cSStephen Warren *mux_bits = clock_source[*type][CLOCK_MAX_MUX];
661d0ad8a5cSStephen Warren
662d0ad8a5cSStephen Warren if (*type == CLOCK_TYPE_PC2CC3M_T16)
663d0ad8a5cSStephen Warren *divider_bits = 16;
664d0ad8a5cSStephen Warren else
665d0ad8a5cSStephen Warren *divider_bits = 8;
666d0ad8a5cSStephen Warren
667d0ad8a5cSStephen Warren return 0;
668d0ad8a5cSStephen Warren }
669d0ad8a5cSStephen Warren
get_periph_clock_id(enum periph_id periph_id,int source)670d0ad8a5cSStephen Warren enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)
671d0ad8a5cSStephen Warren {
672d0ad8a5cSStephen Warren enum periphc_internal_id internal_id;
673d0ad8a5cSStephen Warren int type;
674d0ad8a5cSStephen Warren
675d0ad8a5cSStephen Warren if (!clock_periph_id_isvalid(periph_id))
676d0ad8a5cSStephen Warren return CLOCK_ID_NONE;
677d0ad8a5cSStephen Warren
678d0ad8a5cSStephen Warren internal_id = periph_id_to_internal_id[periph_id];
679d0ad8a5cSStephen Warren if (!periphc_internal_id_isvalid(internal_id))
680d0ad8a5cSStephen Warren return CLOCK_ID_NONE;
681d0ad8a5cSStephen Warren
682d0ad8a5cSStephen Warren type = clock_periph_type[internal_id];
683d0ad8a5cSStephen Warren if (!clock_type_id_isvalid(type))
684d0ad8a5cSStephen Warren return CLOCK_ID_NONE;
685d0ad8a5cSStephen Warren
686d0ad8a5cSStephen Warren return clock_source[type][source];
687d0ad8a5cSStephen Warren }
688d0ad8a5cSStephen Warren
68909f455dcSMasahiro Yamada /**
69009f455dcSMasahiro Yamada * Given a peripheral ID and the required source clock, this returns which
69109f455dcSMasahiro Yamada * value should be programmed into the source mux for that peripheral.
69209f455dcSMasahiro Yamada *
69309f455dcSMasahiro Yamada * There is special code here to handle the one source type with 5 sources.
69409f455dcSMasahiro Yamada *
69509f455dcSMasahiro Yamada * @param periph_id peripheral to start
69609f455dcSMasahiro Yamada * @param source PLL id of required parent clock
69709f455dcSMasahiro Yamada * @param mux_bits Set to number of bits in mux register: 2 or 4
69809f455dcSMasahiro Yamada * @param divider_bits Set to number of divider bits (8 or 16)
69909f455dcSMasahiro Yamada * @return mux value (0-4, or -1 if not found)
70009f455dcSMasahiro Yamada */
get_periph_clock_source(enum periph_id periph_id,enum clock_id parent,int * mux_bits,int * divider_bits)70109f455dcSMasahiro Yamada int get_periph_clock_source(enum periph_id periph_id,
70209f455dcSMasahiro Yamada enum clock_id parent, int *mux_bits, int *divider_bits)
70309f455dcSMasahiro Yamada {
70409f455dcSMasahiro Yamada enum clock_type_id type;
705d0ad8a5cSStephen Warren int mux, err;
70609f455dcSMasahiro Yamada
707d0ad8a5cSStephen Warren err = get_periph_clock_info(periph_id, mux_bits, divider_bits, &type);
708d0ad8a5cSStephen Warren assert(!err);
70909f455dcSMasahiro Yamada
71009f455dcSMasahiro Yamada for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
71109f455dcSMasahiro Yamada if (clock_source[type][mux] == parent)
71209f455dcSMasahiro Yamada return mux;
71309f455dcSMasahiro Yamada
71409f455dcSMasahiro Yamada /* if we get here, either us or the caller has made a mistake */
71509f455dcSMasahiro Yamada printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
71609f455dcSMasahiro Yamada parent);
71709f455dcSMasahiro Yamada return -1;
71809f455dcSMasahiro Yamada }
71909f455dcSMasahiro Yamada
clock_set_enable(enum periph_id periph_id,int enable)72009f455dcSMasahiro Yamada void clock_set_enable(enum periph_id periph_id, int enable)
72109f455dcSMasahiro Yamada {
72209f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst =
72309f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
72409f455dcSMasahiro Yamada u32 *clk;
72509f455dcSMasahiro Yamada u32 reg;
72609f455dcSMasahiro Yamada
72709f455dcSMasahiro Yamada /* Enable/disable the clock to this peripheral */
72809f455dcSMasahiro Yamada assert(clock_periph_id_isvalid(periph_id));
72909f455dcSMasahiro Yamada if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
73009f455dcSMasahiro Yamada clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
73196e82a25SSimon Glass else if ((int)periph_id < PERIPH_ID_X_FIRST)
73209f455dcSMasahiro Yamada clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
73396e82a25SSimon Glass else
73496e82a25SSimon Glass clk = &clkrst->crc_clk_out_enb_x;
73509f455dcSMasahiro Yamada reg = readl(clk);
73609f455dcSMasahiro Yamada if (enable)
73709f455dcSMasahiro Yamada reg |= PERIPH_MASK(periph_id);
73809f455dcSMasahiro Yamada else
73909f455dcSMasahiro Yamada reg &= ~PERIPH_MASK(periph_id);
74009f455dcSMasahiro Yamada writel(reg, clk);
74109f455dcSMasahiro Yamada }
74209f455dcSMasahiro Yamada
reset_set_enable(enum periph_id periph_id,int enable)74309f455dcSMasahiro Yamada void reset_set_enable(enum periph_id periph_id, int enable)
74409f455dcSMasahiro Yamada {
74509f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst =
74609f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
74709f455dcSMasahiro Yamada u32 *reset;
74809f455dcSMasahiro Yamada u32 reg;
74909f455dcSMasahiro Yamada
75009f455dcSMasahiro Yamada /* Enable/disable reset to the peripheral */
75109f455dcSMasahiro Yamada assert(clock_periph_id_isvalid(periph_id));
75209f455dcSMasahiro Yamada if (periph_id < PERIPH_ID_VW_FIRST)
75309f455dcSMasahiro Yamada reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
75496e82a25SSimon Glass else if ((int)periph_id < PERIPH_ID_X_FIRST)
75509f455dcSMasahiro Yamada reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
75696e82a25SSimon Glass else
75796e82a25SSimon Glass reset = &clkrst->crc_rst_devices_x;
75809f455dcSMasahiro Yamada reg = readl(reset);
75909f455dcSMasahiro Yamada if (enable)
76009f455dcSMasahiro Yamada reg |= PERIPH_MASK(periph_id);
76109f455dcSMasahiro Yamada else
76209f455dcSMasahiro Yamada reg &= ~PERIPH_MASK(periph_id);
76309f455dcSMasahiro Yamada writel(reg, reset);
76409f455dcSMasahiro Yamada }
76509f455dcSMasahiro Yamada
7660f925822SMasahiro Yamada #if CONFIG_IS_ENABLED(OF_CONTROL)
76709f455dcSMasahiro Yamada /*
76809f455dcSMasahiro Yamada * Convert a device tree clock ID to our peripheral ID. They are mostly
76909f455dcSMasahiro Yamada * the same but we are very cautious so we check that a valid clock ID is
77009f455dcSMasahiro Yamada * provided.
77109f455dcSMasahiro Yamada *
77209f455dcSMasahiro Yamada * @param clk_id Clock ID according to tegra124 device tree binding
77309f455dcSMasahiro Yamada * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
77409f455dcSMasahiro Yamada */
clk_id_to_periph_id(int clk_id)77509f455dcSMasahiro Yamada enum periph_id clk_id_to_periph_id(int clk_id)
77609f455dcSMasahiro Yamada {
77709f455dcSMasahiro Yamada if (clk_id > PERIPH_ID_COUNT)
77809f455dcSMasahiro Yamada return PERIPH_ID_NONE;
77909f455dcSMasahiro Yamada
78009f455dcSMasahiro Yamada switch (clk_id) {
78109f455dcSMasahiro Yamada case PERIPH_ID_RESERVED4:
78209f455dcSMasahiro Yamada case PERIPH_ID_RESERVED25:
78309f455dcSMasahiro Yamada case PERIPH_ID_RESERVED35:
78409f455dcSMasahiro Yamada case PERIPH_ID_RESERVED36:
78509f455dcSMasahiro Yamada case PERIPH_ID_RESERVED38:
78609f455dcSMasahiro Yamada case PERIPH_ID_RESERVED43:
78709f455dcSMasahiro Yamada case PERIPH_ID_RESERVED49:
78809f455dcSMasahiro Yamada case PERIPH_ID_RESERVED53:
78909f455dcSMasahiro Yamada case PERIPH_ID_RESERVED64:
79009f455dcSMasahiro Yamada case PERIPH_ID_RESERVED84:
79109f455dcSMasahiro Yamada case PERIPH_ID_RESERVED85:
79209f455dcSMasahiro Yamada case PERIPH_ID_RESERVED86:
79309f455dcSMasahiro Yamada case PERIPH_ID_RESERVED88:
79409f455dcSMasahiro Yamada case PERIPH_ID_RESERVED90:
79509f455dcSMasahiro Yamada case PERIPH_ID_RESERVED92:
79609f455dcSMasahiro Yamada case PERIPH_ID_RESERVED93:
79709f455dcSMasahiro Yamada case PERIPH_ID_RESERVED94:
79809f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED2:
79909f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED4:
80009f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED17:
80109f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED18:
80209f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED19:
80309f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED20:
80409f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED21:
80509f455dcSMasahiro Yamada case PERIPH_ID_V_RESERVED22:
80609f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED2:
80709f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED3:
80809f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED4:
80909f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED5:
81009f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED6:
81109f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED7:
81209f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED9:
81309f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED10:
81409f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED11:
81509f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED12:
81609f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED13:
81709f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED15:
81809f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED16:
81909f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED17:
82009f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED18:
82109f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED19:
82209f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED20:
82309f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED23:
82409f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED29:
82509f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED30:
82609f455dcSMasahiro Yamada case PERIPH_ID_W_RESERVED31:
82709f455dcSMasahiro Yamada return PERIPH_ID_NONE;
82809f455dcSMasahiro Yamada default:
82909f455dcSMasahiro Yamada return clk_id;
83009f455dcSMasahiro Yamada }
83109f455dcSMasahiro Yamada }
8320f925822SMasahiro Yamada #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
83309f455dcSMasahiro Yamada
clock_early_init(void)83409f455dcSMasahiro Yamada void clock_early_init(void)
83509f455dcSMasahiro Yamada {
83609f455dcSMasahiro Yamada struct clk_rst_ctlr *clkrst =
83709f455dcSMasahiro Yamada (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
838722e000cSTom Warren struct clk_pll_info *pllinfo;
839722e000cSTom Warren u32 data;
84009f455dcSMasahiro Yamada
84109f455dcSMasahiro Yamada tegra30_set_up_pllp();
84209f455dcSMasahiro Yamada
843aba11d44SThierry Reding /* clear IDDQ before accessing any other PLLC registers */
844aba11d44SThierry Reding pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
845aba11d44SThierry Reding clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
846aba11d44SThierry Reding udelay(2);
847aba11d44SThierry Reding
84809f455dcSMasahiro Yamada /*
84909f455dcSMasahiro Yamada * PLLC output frequency set to 600Mhz
85009f455dcSMasahiro Yamada * PLLD output frequency set to 925Mhz
85109f455dcSMasahiro Yamada */
85209f455dcSMasahiro Yamada switch (clock_get_osc_freq()) {
85309f455dcSMasahiro Yamada case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
85409f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
85509f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
85609f455dcSMasahiro Yamada break;
85709f455dcSMasahiro Yamada
85809f455dcSMasahiro Yamada case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
85909f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
86009f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_DISPLAY, 925, 26, 0, 12);
86109f455dcSMasahiro Yamada break;
86209f455dcSMasahiro Yamada
86309f455dcSMasahiro Yamada case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
86409f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
86509f455dcSMasahiro Yamada clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
86609f455dcSMasahiro Yamada break;
86709f455dcSMasahiro Yamada case CLOCK_OSC_FREQ_19_2:
86809f455dcSMasahiro Yamada default:
86909f455dcSMasahiro Yamada /*
87009f455dcSMasahiro Yamada * These are not supported. It is too early to print a
87109f455dcSMasahiro Yamada * message and the UART likely won't work anyway due to the
87209f455dcSMasahiro Yamada * oscillator being wrong.
87309f455dcSMasahiro Yamada */
87409f455dcSMasahiro Yamada break;
87509f455dcSMasahiro Yamada }
87609f455dcSMasahiro Yamada
87709f455dcSMasahiro Yamada /* PLLC_MISC2: Set dynramp_stepA/B. MISC2 maps to pll_out[1] */
87809f455dcSMasahiro Yamada writel(0x00561600, &clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1]);
87909f455dcSMasahiro Yamada
88009f455dcSMasahiro Yamada /* PLLC_MISC: Set LOCK_ENABLE */
881722e000cSTom Warren pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
882722e000cSTom Warren setbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, (1 << pllinfo->lock_ena));
88309f455dcSMasahiro Yamada udelay(2);
88409f455dcSMasahiro Yamada
885722e000cSTom Warren /* PLLD_MISC: Set CLKENABLE, CPCON 12, LFCON 1, and enable lock */
886722e000cSTom Warren pllinfo = &tegra_pll_info_table[CLOCK_ID_DISPLAY];
887722e000cSTom Warren data = (12 << pllinfo->kcp_shift) | (1 << pllinfo->kvco_shift);
888722e000cSTom Warren data |= (1 << PLLD_CLKENABLE) | (1 << pllinfo->lock_ena);
889722e000cSTom Warren writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc);
89009f455dcSMasahiro Yamada udelay(2);
89109f455dcSMasahiro Yamada }
89209f455dcSMasahiro Yamada
89346864cc8SSimon Glass /*
89446864cc8SSimon Glass * clock_early_init_done - Check if clock_early_init() has been called
89546864cc8SSimon Glass *
89646864cc8SSimon Glass * Check a register that we set up to see if clock_early_init() has already
89746864cc8SSimon Glass * been called.
89846864cc8SSimon Glass *
89946864cc8SSimon Glass * @return true if clock_early_init() was called, false if not
90046864cc8SSimon Glass */
clock_early_init_done(void)90146864cc8SSimon Glass bool clock_early_init_done(void)
90246864cc8SSimon Glass {
90346864cc8SSimon Glass struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
90446864cc8SSimon Glass u32 val;
90546864cc8SSimon Glass
90646864cc8SSimon Glass val = readl(&clkrst->crc_sclk_brst_pol);
90746864cc8SSimon Glass
90846864cc8SSimon Glass return val == 0x20002222;
90946864cc8SSimon Glass }
91046864cc8SSimon Glass
arch_timer_init(void)91109f455dcSMasahiro Yamada void arch_timer_init(void)
91209f455dcSMasahiro Yamada {
91309f455dcSMasahiro Yamada struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
91409f455dcSMasahiro Yamada u32 freq, val;
91509f455dcSMasahiro Yamada
91697c02d87SThierry Reding freq = clock_get_rate(CLOCK_ID_CLK_M);
91797c02d87SThierry Reding debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
91809f455dcSMasahiro Yamada
91909f455dcSMasahiro Yamada /* ARM CNTFRQ */
92009f455dcSMasahiro Yamada asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
92109f455dcSMasahiro Yamada
92209f455dcSMasahiro Yamada /* Only Tegra114+ has the System Counter regs */
92309f455dcSMasahiro Yamada debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
92409f455dcSMasahiro Yamada writel(freq, &sysctr->cntfid0);
92509f455dcSMasahiro Yamada
92609f455dcSMasahiro Yamada val = readl(&sysctr->cntcr);
92709f455dcSMasahiro Yamada val |= TSC_CNTCR_ENABLE | TSC_CNTCR_HDBG;
92809f455dcSMasahiro Yamada writel(val, &sysctr->cntcr);
92909f455dcSMasahiro Yamada debug("%s: TSC CNTCR = 0x%08X\n", __func__, val);
93009f455dcSMasahiro Yamada }
93109f455dcSMasahiro Yamada
93209f455dcSMasahiro Yamada #define PLLE_SS_CNTL 0x68
93309f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCINCINTR(x) (((x) & 0x3f) << 24)
93409f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCINC(x) (((x) & 0xff) << 16)
93509f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCINVERT (1 << 15)
93609f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCCENTER (1 << 14)
93709f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCBYP (1 << 12)
93809f455dcSMasahiro Yamada #define PLLE_SS_CNTL_INTERP_RESET (1 << 11)
93909f455dcSMasahiro Yamada #define PLLE_SS_CNTL_BYPASS_SS (1 << 10)
94009f455dcSMasahiro Yamada #define PLLE_SS_CNTL_SSCMAX(x) (((x) & 0x1ff) << 0)
94109f455dcSMasahiro Yamada
94209f455dcSMasahiro Yamada #define PLLE_BASE 0x0e8
94309f455dcSMasahiro Yamada #define PLLE_BASE_ENABLE (1 << 30)
94409f455dcSMasahiro Yamada #define PLLE_BASE_LOCK_OVERRIDE (1 << 29)
94509f455dcSMasahiro Yamada #define PLLE_BASE_PLDIV_CML(x) (((x) & 0xf) << 24)
94609f455dcSMasahiro Yamada #define PLLE_BASE_NDIV(x) (((x) & 0xff) << 8)
94709f455dcSMasahiro Yamada #define PLLE_BASE_MDIV(x) (((x) & 0xff) << 0)
94809f455dcSMasahiro Yamada
94909f455dcSMasahiro Yamada #define PLLE_MISC 0x0ec
95009f455dcSMasahiro Yamada #define PLLE_MISC_IDDQ_SWCTL (1 << 14)
95109f455dcSMasahiro Yamada #define PLLE_MISC_IDDQ_OVERRIDE (1 << 13)
95209f455dcSMasahiro Yamada #define PLLE_MISC_LOCK_ENABLE (1 << 9)
95309f455dcSMasahiro Yamada #define PLLE_MISC_PTS (1 << 8)
95409f455dcSMasahiro Yamada #define PLLE_MISC_VREG_BG_CTRL(x) (((x) & 0x3) << 4)
95509f455dcSMasahiro Yamada #define PLLE_MISC_VREG_CTRL(x) (((x) & 0x3) << 2)
95609f455dcSMasahiro Yamada
95709f455dcSMasahiro Yamada #define PLLE_AUX 0x48c
95809f455dcSMasahiro Yamada #define PLLE_AUX_SEQ_ENABLE (1 << 24)
95909f455dcSMasahiro Yamada #define PLLE_AUX_ENABLE_SWCTL (1 << 4)
96009f455dcSMasahiro Yamada
tegra_plle_enable(void)96109f455dcSMasahiro Yamada int tegra_plle_enable(void)
96209f455dcSMasahiro Yamada {
96309f455dcSMasahiro Yamada unsigned int m = 1, n = 200, cpcon = 13;
96409f455dcSMasahiro Yamada u32 value;
96509f455dcSMasahiro Yamada
96609f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
96709f455dcSMasahiro Yamada value &= ~PLLE_BASE_LOCK_OVERRIDE;
96809f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
96909f455dcSMasahiro Yamada
97009f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
97109f455dcSMasahiro Yamada value |= PLLE_AUX_ENABLE_SWCTL;
97209f455dcSMasahiro Yamada value &= ~PLLE_AUX_SEQ_ENABLE;
97309f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
97409f455dcSMasahiro Yamada
97509f455dcSMasahiro Yamada udelay(1);
97609f455dcSMasahiro Yamada
97709f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
97809f455dcSMasahiro Yamada value |= PLLE_MISC_IDDQ_SWCTL;
97909f455dcSMasahiro Yamada value &= ~PLLE_MISC_IDDQ_OVERRIDE;
98009f455dcSMasahiro Yamada value |= PLLE_MISC_LOCK_ENABLE;
98109f455dcSMasahiro Yamada value |= PLLE_MISC_PTS;
98209f455dcSMasahiro Yamada value |= PLLE_MISC_VREG_BG_CTRL(3);
98309f455dcSMasahiro Yamada value |= PLLE_MISC_VREG_CTRL(2);
98409f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
98509f455dcSMasahiro Yamada
98609f455dcSMasahiro Yamada udelay(5);
98709f455dcSMasahiro Yamada
98809f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
98909f455dcSMasahiro Yamada value |= PLLE_SS_CNTL_SSCBYP | PLLE_SS_CNTL_INTERP_RESET |
99009f455dcSMasahiro Yamada PLLE_SS_CNTL_BYPASS_SS;
99109f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
99209f455dcSMasahiro Yamada
99309f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
99409f455dcSMasahiro Yamada value &= ~PLLE_BASE_PLDIV_CML(0xf);
99509f455dcSMasahiro Yamada value &= ~PLLE_BASE_NDIV(0xff);
99609f455dcSMasahiro Yamada value &= ~PLLE_BASE_MDIV(0xff);
99709f455dcSMasahiro Yamada value |= PLLE_BASE_PLDIV_CML(cpcon);
99809f455dcSMasahiro Yamada value |= PLLE_BASE_NDIV(n);
99909f455dcSMasahiro Yamada value |= PLLE_BASE_MDIV(m);
100009f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
100109f455dcSMasahiro Yamada
100209f455dcSMasahiro Yamada udelay(1);
100309f455dcSMasahiro Yamada
100409f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_BASE);
100509f455dcSMasahiro Yamada value |= PLLE_BASE_ENABLE;
100609f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_BASE);
100709f455dcSMasahiro Yamada
100809f455dcSMasahiro Yamada /* wait for lock */
100909f455dcSMasahiro Yamada udelay(300);
101009f455dcSMasahiro Yamada
101109f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
101209f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCINVERT;
101309f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCCENTER;
101409f455dcSMasahiro Yamada
101509f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCINCINTR(0x3f);
101609f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCINC(0xff);
101709f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCMAX(0x1ff);
101809f455dcSMasahiro Yamada
101909f455dcSMasahiro Yamada value |= PLLE_SS_CNTL_SSCINCINTR(0x20);
102009f455dcSMasahiro Yamada value |= PLLE_SS_CNTL_SSCINC(0x01);
102109f455dcSMasahiro Yamada value |= PLLE_SS_CNTL_SSCMAX(0x25);
102209f455dcSMasahiro Yamada
102309f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
102409f455dcSMasahiro Yamada
102509f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
102609f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_SSCBYP;
102709f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_BYPASS_SS;
102809f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
102909f455dcSMasahiro Yamada
103009f455dcSMasahiro Yamada udelay(1);
103109f455dcSMasahiro Yamada
103209f455dcSMasahiro Yamada value = readl(NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
103309f455dcSMasahiro Yamada value &= ~PLLE_SS_CNTL_INTERP_RESET;
103409f455dcSMasahiro Yamada writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
103509f455dcSMasahiro Yamada
103609f455dcSMasahiro Yamada udelay(1);
103709f455dcSMasahiro Yamada
103809f455dcSMasahiro Yamada return 0;
103909f455dcSMasahiro Yamada }
104096e82a25SSimon Glass
clock_sor_enable_edp_clock(void)104196e82a25SSimon Glass void clock_sor_enable_edp_clock(void)
104296e82a25SSimon Glass {
104396e82a25SSimon Glass u32 *reg;
104496e82a25SSimon Glass
104596e82a25SSimon Glass /* uses PLLP, has a non-standard bit layout. */
104696e82a25SSimon Glass reg = get_periph_source_reg(PERIPH_ID_SOR0);
104796e82a25SSimon Glass setbits_le32(reg, SOR0_CLK_SEL0);
104896e82a25SSimon Glass }
104996e82a25SSimon Glass
clock_set_display_rate(u32 frequency)105096e82a25SSimon Glass u32 clock_set_display_rate(u32 frequency)
105196e82a25SSimon Glass {
105296e82a25SSimon Glass /**
105396e82a25SSimon Glass * plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
105496e82a25SSimon Glass * = (cf * n) >> p, where 1MHz < cf < 6MHz
105596e82a25SSimon Glass * = ((ref / m) * n) >> p
105696e82a25SSimon Glass *
105796e82a25SSimon Glass * Iterate the possible values of p (3 bits, 2^7) to find out a minimum
105896e82a25SSimon Glass * safe vco, then find best (m, n). since m has only 5 bits, we can
105996e82a25SSimon Glass * iterate all possible values. Note Tegra 124 supports 11 bits for n,
106096e82a25SSimon Glass * but our pll_fields has only 10 bits for n.
106196e82a25SSimon Glass *
106296e82a25SSimon Glass * Note values undershoot or overshoot target output frequency may not
106396e82a25SSimon Glass * work if the values are not in "safe" range by panel specification.
106496e82a25SSimon Glass */
106596e82a25SSimon Glass u32 ref = clock_get_rate(CLOCK_ID_OSC);
106696e82a25SSimon Glass u32 divm, divn, divp, cpcon;
106796e82a25SSimon Glass u32 cf, vco, rounded_rate = frequency;
106896e82a25SSimon Glass u32 diff, best_diff, best_m = 0, best_n = 0, best_p;
106996e82a25SSimon Glass const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3,
107096e82a25SSimon Glass mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz,
107196e82a25SSimon Glass min_cf = 1 * mhz, max_cf = 6 * mhz;
107296e82a25SSimon Glass int mux_bits, divider_bits, source;
107396e82a25SSimon Glass
107496e82a25SSimon Glass for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++)
107596e82a25SSimon Glass vco <<= 1;
107696e82a25SSimon Glass
107796e82a25SSimon Glass if (vco < min_vco || vco > max_vco) {
107896e82a25SSimon Glass printf("%s: Cannot find out a supported VCO for Frequency (%u)\n",
107996e82a25SSimon Glass __func__, frequency);
108096e82a25SSimon Glass return 0;
108196e82a25SSimon Glass }
108296e82a25SSimon Glass
108396e82a25SSimon Glass best_p = divp;
108496e82a25SSimon Glass best_diff = vco;
108596e82a25SSimon Glass
108696e82a25SSimon Glass for (divm = 1; divm < max_m && best_diff; divm++) {
108796e82a25SSimon Glass cf = ref / divm;
108896e82a25SSimon Glass if (cf < min_cf)
108996e82a25SSimon Glass break;
109096e82a25SSimon Glass if (cf > max_cf)
109196e82a25SSimon Glass continue;
109296e82a25SSimon Glass
109396e82a25SSimon Glass divn = vco / cf;
109496e82a25SSimon Glass if (divn >= max_n)
109596e82a25SSimon Glass continue;
109696e82a25SSimon Glass
109796e82a25SSimon Glass diff = vco - divn * cf;
109896e82a25SSimon Glass if (divn + 1 < max_n && diff > cf / 2) {
109996e82a25SSimon Glass divn++;
110096e82a25SSimon Glass diff = cf - diff;
110196e82a25SSimon Glass }
110296e82a25SSimon Glass
110396e82a25SSimon Glass if (diff >= best_diff)
110496e82a25SSimon Glass continue;
110596e82a25SSimon Glass
110696e82a25SSimon Glass best_diff = diff;
110796e82a25SSimon Glass best_m = divm;
110896e82a25SSimon Glass best_n = divn;
110996e82a25SSimon Glass }
111096e82a25SSimon Glass
111196e82a25SSimon Glass if (best_n < 50)
111296e82a25SSimon Glass cpcon = 2;
111396e82a25SSimon Glass else if (best_n < 300)
111496e82a25SSimon Glass cpcon = 3;
111596e82a25SSimon Glass else if (best_n < 600)
111696e82a25SSimon Glass cpcon = 8;
111796e82a25SSimon Glass else
111896e82a25SSimon Glass cpcon = 12;
111996e82a25SSimon Glass
112096e82a25SSimon Glass if (best_diff) {
112196e82a25SSimon Glass printf("%s: Failed to match output frequency %u, best difference is %u\n",
112296e82a25SSimon Glass __func__, frequency, best_diff);
112396e82a25SSimon Glass rounded_rate = (ref / best_m * best_n) >> best_p;
112496e82a25SSimon Glass }
112596e82a25SSimon Glass
112696e82a25SSimon Glass debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
112796e82a25SSimon Glass __func__, rounded_rate, ref, best_m, best_n, best_p, cpcon);
112896e82a25SSimon Glass
112996e82a25SSimon Glass source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY,
113096e82a25SSimon Glass &mux_bits, ÷r_bits);
113196e82a25SSimon Glass clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source);
113296e82a25SSimon Glass clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon);
113396e82a25SSimon Glass
113496e82a25SSimon Glass return rounded_rate;
113596e82a25SSimon Glass }
113696e82a25SSimon Glass
clock_set_up_plldp(void)113796e82a25SSimon Glass void clock_set_up_plldp(void)
113896e82a25SSimon Glass {
113996e82a25SSimon Glass struct clk_rst_ctlr *clkrst =
114096e82a25SSimon Glass (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
114196e82a25SSimon Glass u32 value;
114296e82a25SSimon Glass
114396e82a25SSimon Glass value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER;
114496e82a25SSimon Glass writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg);
114596e82a25SSimon Glass clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0);
114696e82a25SSimon Glass writel(value, &clkrst->crc_plldp_ss_cfg);
114796e82a25SSimon Glass }
114896e82a25SSimon Glass
clock_get_simple_pll(enum clock_id clkid)114996e82a25SSimon Glass struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
115096e82a25SSimon Glass {
115196e82a25SSimon Glass struct clk_rst_ctlr *clkrst =
115296e82a25SSimon Glass (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
115396e82a25SSimon Glass
115496e82a25SSimon Glass if (clkid == CLOCK_ID_DP)
115596e82a25SSimon Glass return &clkrst->plldp;
115696e82a25SSimon Glass
115796e82a25SSimon Glass return NULL;
115896e82a25SSimon Glass }
11596dbcc962SStephen Warren
11606dbcc962SStephen Warren struct periph_clk_init periph_clk_init_table[] = {
11616dbcc962SStephen Warren { PERIPH_ID_SBC1, CLOCK_ID_PERIPH },
11626dbcc962SStephen Warren { PERIPH_ID_SBC2, CLOCK_ID_PERIPH },
11636dbcc962SStephen Warren { PERIPH_ID_SBC3, CLOCK_ID_PERIPH },
11646dbcc962SStephen Warren { PERIPH_ID_SBC4, CLOCK_ID_PERIPH },
11656dbcc962SStephen Warren { PERIPH_ID_SBC5, CLOCK_ID_PERIPH },
11666dbcc962SStephen Warren { PERIPH_ID_SBC6, CLOCK_ID_PERIPH },
11676dbcc962SStephen Warren { PERIPH_ID_HOST1X, CLOCK_ID_PERIPH },
11686dbcc962SStephen Warren { PERIPH_ID_DISP1, CLOCK_ID_CGENERAL },
11696dbcc962SStephen Warren { PERIPH_ID_SDMMC1, CLOCK_ID_PERIPH },
11706dbcc962SStephen Warren { PERIPH_ID_SDMMC2, CLOCK_ID_PERIPH },
11716dbcc962SStephen Warren { PERIPH_ID_SDMMC3, CLOCK_ID_PERIPH },
11726dbcc962SStephen Warren { PERIPH_ID_SDMMC4, CLOCK_ID_PERIPH },
11736dbcc962SStephen Warren { PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ },
11746dbcc962SStephen Warren { PERIPH_ID_I2C1, CLOCK_ID_PERIPH },
11756dbcc962SStephen Warren { PERIPH_ID_I2C2, CLOCK_ID_PERIPH },
11766dbcc962SStephen Warren { PERIPH_ID_I2C3, CLOCK_ID_PERIPH },
11776dbcc962SStephen Warren { PERIPH_ID_I2C4, CLOCK_ID_PERIPH },
11786dbcc962SStephen Warren { PERIPH_ID_I2C5, CLOCK_ID_PERIPH },
11796dbcc962SStephen Warren { PERIPH_ID_I2C6, CLOCK_ID_PERIPH },
11806dbcc962SStephen Warren { -1, },
11816dbcc962SStephen Warren };
1182