History log of /openbmc/u-boot/drivers/clk/Kconfig (Results 1 – 25 of 46)
Revision (<<< Hide revision tags) (Show revision tags >>>) Date Author Comments
Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04
# 783e6681 27-Feb-2019 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-riscv

- SiFive FU540 Support


# c40b6df8 25-Feb-2019 Anup Patel <Anup.Patel@wdc.com>

clk: Add SiFive FU540 PRCI clock driver

Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock

clk: Add SiFive FU540 PRCI clock driver

Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra <wesley@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>

show more ...


# d01806a8 24-Jan-2019 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-sunxi


# 0d47bc70 22-Dec-2018 Jagan Teki <jagan@amarulasolutions.com>

clk: Add Allwinner A64 CLK driver

Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk ga

clk: Add Allwinner A64 CLK driver

Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

show more ...


# cf033e04 25-Oct-2018 Tom Rini <trini@konsulko.com>

Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx

Merged imx8 architecture, fix build for imx8 + warnings


# f77d4410 18-Oct-2018 Peng Fan <peng.fan@nxp.com>

clk: imx: add clk driver for i.MX8QXP

Add clk driver for i.MX8QXP. This basic version supports clk
enable/disable/get_rate/set_rate operations for I2C, ENET,
SDHC0 and UART clocks.

Signed-off-by: P

clk: imx: add clk driver for i.MX8QXP

Add clk driver for i.MX8QXP. This basic version supports clk
enable/disable/get_rate/set_rate operations for I2C, ENET,
SDHC0 and UART clocks.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

show more ...


# a71e907c 17-Sep-2018 Liviu Dudau <Liviu.Dudau@foss.arm.com>

clk: Add support for Arm's Versatile Express OSC clock generators

The Arm Versatile Express and Juno development boards contain an
OSC clock generator that can be accessed through the Versatile
Expr

clk: Add support for Arm's Versatile Express OSC clock generators

The Arm Versatile Express and Juno development boards contain an
OSC clock generator that can be accessed through the Versatile
Express config bus. The generators are quite often being controlled
by some MCU and the config bus offers a uniform way of exposing them.

Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

show more ...


# 4e710ebb 18-Sep-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-dm

- MPC83xx device tree additions (CPU and RAM)
- Fix sandbox build error
- Sync bitrev with Linux
- Various ofnode/DT improvements


# 07d538d2 06-Aug-2018 Mario Six <mario.six@gdsys.cc>

clk: Add MPC83xx clock driver

Add a clock driver for the MPC83xx architecture.

Signed-off-by: Mario Six <mario.six@gdsys.cc>


# e585bef1 27-Aug-2018 Andreas Dannenberg <dannenberg@ti.com>

clk: Introduce TI System Control Interface (TI SCI) clock driver

Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoC

clk: Introduce TI System Control Interface (TI SCI) clock driver

Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a clock driver that communicates to the system
controller over the TI SCI protocol for performing clock management of
various devices present on the SoC. Various clock functionality is
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.

This code is loosely based on the drivers/clk/keystone/sci-clk.c driver
of the Linux kernel.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

show more ...


# b71d9e8b 20-Aug-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-sunxi


# cf682257 30-Jul-2018 Jagan Teki <jagan@amarulasolutions.com>

clk: Kconfig: Ascending order to sub directiory kconfigs

sourcing of sub directiory kconfig files are not in
proper order, so keep them in ascending order.

Signed-off-by: Jagan Teki <jagan@amarulas

clk: Kconfig: Ascending order to sub directiory kconfigs

sourcing of sub directiory kconfig files are not in
proper order, so keep them in ascending order.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>

show more ...


Revision tags: v2018.07
# ae485b54 14-Jun-2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

clk: Add Actions Semi OWL clock support

This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for

clk: Add Actions Semi OWL clock support

This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...


# ca70cbab 14-May-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-marvell


# 82a248df 24-Apr-2018 Marek Behún <marek.behun@nic.cz>

driver: clk: Add support for clocks on Armada 37xx

The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
- since setting rate is not supporte

driver: clk: Add support for clocks on Armada 37xx

The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
- since setting rate is not supported, the driver computes the rates
when probing and so subsequent calls to the .get_rate method do not
read the corresponding registers again

The peripheral clocks support methods .get_rate, .enable and .disable.

- the .set_parent method theoretically could be supported on some clocks
(the parent would have to be one of the TBG clocks)

- the .set_rate method would have to try all the divider values to find
the best approximation of a given rate, and it doesn't seem like
this should be needed in U-Boot, therefore not implemented

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

show more ...


# f0bcbe6c 27-Apr-2018 Mario Six <mario.six@gdsys.cc>

clk: Add ICS8N3QV01 driver

Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.

Signed-off-by: Mario Six <mario.six@gdsys.cc>


Revision tags: v2018.03
# a6151916 12-Mar-2018 Patrick Delaunay <patrick.delaunay@st.com>

clk: add driver for stm32mp1

add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
of all SOC clock needed by U-Boot

Signed-off-by

clk: add driver for stm32mp1

add RCC clock driver for STMP32MP157
- base on driver model = UCLASS_CLK
- support ops to enable, disable and get rate
of all SOC clock needed by U-Boot

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

show more ...


Revision tags: v2018.01
# 6f1ee8a4 11-Dec-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-arc


# e80dac0a 10-Dec-2017 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

ARC: clk: introduce HSDK CGU clock driver

Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and

ARC: clk: introduce HSDK CGU clock driver

Synopsys HSDK clock controller generates and supplies clocks to various
controllers and peripherals within the SoC.

Each clock has assigned identifier and client device tree nodes can use
this identifier to specify the clock which they consume. All available
clocks are defined as preprocessor macros in the
dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device
tree sources.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

show more ...


# f264e235 15-Nov-2017 Patrice Chotard <patrice.chotard@st.com>

clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c

Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnin

clk: stm32f7: rename clk_stm32f7.c to clk_stm32f.c

Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs
rename it to a more generic clk_stm32f.c

Fix also some checkpatch errors/warnings.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

show more ...


Revision tags: v2017.11
# 0712b672 31-Jul-2017 Wenyou Yang <wenyou.yang@microchip.com>

clk: Kconfig: Add dependences of SPL_CLK

The SPL_CLK config should depend on SPL && SPL_DM.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>


# c1b62ba9 14-Aug-2017 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-rockchip


# 7c819e7f 28-Jun-2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

spl: dm: Kconfig: split CLK support for SPL and TPL

Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.

Signed-off-by: Philipp Tomsich <p

spl: dm: Kconfig: split CLK support for SPL and TPL

Introduce TPL_CLK to allow finer-grained selection of TPL features
for feature-rich (i.e. DM-based) TPL stages.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

show more ...


# f0776a55 28-Jun-2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

spl: dm: Kconfig: SPL_CLK depends on SPL_DM

SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-syst

spl: dm: Kconfig: SPL_CLK depends on SPL_DM

SPL_CLK should also depend on SPL_DM (and not just on CLK).
Add the additional dependency.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

show more ...


# a89302cc 02-Aug-2017 Tom Rini <trini@konsulko.com>

Merge branch 'rmobile' of git://git.denx.de/u-boot-sh


12