History log of /openbmc/u-boot/drivers/clk/Makefile (Results 1 – 25 of 67)
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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00
# 550e691b 17-May-2019 ryan_chen <ryan_chen@aspeedtech.com>

clk driver separte


# 8f65ebb4 15-May-2019 ryan_chen <ryan_chen@aspeedtech.com>

update clk


Revision tags: v2019.04
# 783e6681 27-Feb-2019 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-riscv

- SiFive FU540 Support


# b630d57d 25-Feb-2019 Anup Patel <Anup.Patel@wdc.com>

clk: Add fixed-factor clock driver

This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Atish

clk: Add fixed-factor clock driver

This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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# c40b6df8 25-Feb-2019 Anup Patel <Anup.Patel@wdc.com>

clk: Add SiFive FU540 PRCI clock driver

Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock

clk: Add SiFive FU540 PRCI clock driver

Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra <wesley@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>

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# d01806a8 24-Jan-2019 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-sunxi


# 0d47bc70 22-Dec-2018 Jagan Teki <jagan@amarulasolutions.com>

clk: Add Allwinner A64 CLK driver

Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk ga

clk: Add Allwinner A64 CLK driver

Add initial clock driver for Allwinner A64.

Implement USB clock enable and disable functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers
via ccu clk gate table.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>

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# 93e72ac4 29-Nov-2018 Tom Rini <trini@konsulko.com>

Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add mes

Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

Cleanup and update towards support for Amlogic Meson AXG SoCs :
- mmc: meson-gx: Add AXG compatible
- net: designware: add meson meson compatibles
- Amlogic Meson cleanup for AXG SoC support

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# e16c888f 28-Nov-2018 Tom Rini <trini@konsulko.com>

Merge branch '2018-11-28-master-imports'

- Add MediaTek support


# 0bd7dc74 14-Nov-2018 Ryder Lee <ryder.lee@mediatek.com>

clk: MediaTek: add clock driver for MT7629 SoC.

This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and ga

clk: MediaTek: add clock driver for MT7629 SoC.

This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.

- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.

We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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# f6eb68b9 07-Sep-2018 Neil Armstrong <narmstrong@baylibre.com>

clk: Add clock driver for AXG

This patch adds a minimal clock driver for the Amlogic AXG SoC to handle
the basic gates and PLLs.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>


# 22929e12 26-Oct-2018 Patrick Delaunay <patrick.delaunay@st.com>

drivers: cosmetic: Convert SPDX license tags to Linux Kernel style

Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux

drivers: cosmetic: Convert SPDX license tags to Linux Kernel style

Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

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# cf033e04 25-Oct-2018 Tom Rini <trini@konsulko.com>

Merge tag 'u-boot-imx-20181025' of git://git.denx.de/u-boot-imx

Merged imx8 architecture, fix build for imx8 + warnings


# f77d4410 18-Oct-2018 Peng Fan <peng.fan@nxp.com>

clk: imx: add clk driver for i.MX8QXP

Add clk driver for i.MX8QXP. This basic version supports clk
enable/disable/get_rate/set_rate operations for I2C, ENET,
SDHC0 and UART clocks.

Signed-off-by: P

clk: imx: add clk driver for i.MX8QXP

Add clk driver for i.MX8QXP. This basic version supports clk
enable/disable/get_rate/set_rate operations for I2C, ENET,
SDHC0 and UART clocks.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

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# a71e907c 17-Sep-2018 Liviu Dudau <Liviu.Dudau@foss.arm.com>

clk: Add support for Arm's Versatile Express OSC clock generators

The Arm Versatile Express and Juno development boards contain an
OSC clock generator that can be accessed through the Versatile
Expr

clk: Add support for Arm's Versatile Express OSC clock generators

The Arm Versatile Express and Juno development boards contain an
OSC clock generator that can be accessed through the Versatile
Express config bus. The generators are quite often being controlled
by some MCU and the config bus offers a uniform way of exposing them.

Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Heiko Schocher <hs@denx.de>

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# 4e710ebb 18-Sep-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-dm

- MPC83xx device tree additions (CPU and RAM)
- Fix sandbox build error
- Sync bitrev with Linux
- Various ofnode/DT improvements


# 07d538d2 06-Aug-2018 Mario Six <mario.six@gdsys.cc>

clk: Add MPC83xx clock driver

Add a clock driver for the MPC83xx architecture.

Signed-off-by: Mario Six <mario.six@gdsys.cc>


# e585bef1 27-Aug-2018 Andreas Dannenberg <dannenberg@ti.com>

clk: Introduce TI System Control Interface (TI SCI) clock driver

Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoC

clk: Introduce TI System Control Interface (TI SCI) clock driver

Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a clock driver that communicates to the system
controller over the TI SCI protocol for performing clock management of
various devices present on the SoC. Various clock functionality is
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.

This code is loosely based on the drivers/clk/keystone/sci-clk.c driver
of the Linux kernel.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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# 719afeb0 17-Aug-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga


# f9f016ad 31-Jul-2018 Marek Vasut <marex@denx.de>

clk: socfpga: Add initial Arria10 clock driver

Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and

clk: socfpga: Add initial Arria10 clock driver

Add clock driver for the Arria10, which allows reading the clock
frequency from all the clock described in the DT. The driver also
allows enabling and disabling the clock. Reconfiguring frequency
is not supported thus far.

Since the DT bindings for the SoCFPGA clock are massively misdesigned
and the handoff DT adds additional incorrectly described entries to
the DT, the driver contains workarounds which attempt to rectify all
of those problems.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

show more ...


Revision tags: v2018.07
# ae485b54 14-Jun-2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

clk: Add Actions Semi OWL clock support

This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for

clk: Add Actions Semi OWL clock support

This commit adds Actions Semi OWL family base clock and S900 SoC
specific clock support. For S900 peripheral clock support, only UART
clock has been added for now.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

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# c0fc1e21 14-Jun-2018 Beniamino Galvani <b.galvani@gmail.com>

clk: add Amlogic meson clock driver

Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.

Signed-off-by: Beniamino Galvani

clk: add Amlogic meson clock driver

Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

show more ...


# ca70cbab 14-May-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-marvell


# 82a248df 24-Apr-2018 Marek Behún <marek.behun@nic.cz>

driver: clk: Add support for clocks on Armada 37xx

The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
- since setting rate is not supporte

driver: clk: Add support for clocks on Armada 37xx

The drivers are based on Linux driver by Gregory Clement.

The TBG clocks support only the .get_rate method.
- since setting rate is not supported, the driver computes the rates
when probing and so subsequent calls to the .get_rate method do not
read the corresponding registers again

The peripheral clocks support methods .get_rate, .enable and .disable.

- the .set_parent method theoretically could be supported on some clocks
(the parent would have to be one of the TBG clocks)

- the .set_rate method would have to try all the divider values to find
the best approximation of a given rate, and it doesn't seem like
this should be needed in U-Boot, therefore not implemented

Signed-off-by: Marek Behun <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>

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# f0bcbe6c 27-Apr-2018 Mario Six <mario.six@gdsys.cc>

clk: Add ICS8N3QV01 driver

Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO.

Signed-off-by: Mario Six <mario.six@gdsys.cc>


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