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Searched refs:CCR (Results 1 – 25 of 30) sorted by relevance

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/openbmc/u-boot/arch/sh/cpu/sh4/
H A Dcache.c42 ccr = inl(CCR); in cache_control()
48 outl(CCR_CACHE_STOP, CCR); in cache_control()
50 outl(CCR_CACHE_INIT, CCR); in cache_control()
/openbmc/u-boot/doc/
H A DREADME.ne20003 that the CCR is correctly initialized.
26 - Address of the CCR (card configuration register). It could be found
32 - The value to be written in the CCR. It selects among different I/O
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7763.h11 #define CCR 0xFF00001C macro
H A Dcpu_sh7269.h6 #define CCR CCR1 macro
H A Dcpu_sh7264.h6 #define CCR CCR1 macro
H A Dcpu_sh7203.h6 #define CCR CCR1 macro
H A Dcpu_sh7706.h9 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7710.h9 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7734.h11 #define CCR 0xFF00001C macro
H A Dcpu_sh7750.h28 #define CCR 0xFF00001C macro
H A Dcpu_sh7785.h20 #define CCR 0xFF00001C macro
H A Dcpu_sh7723.h29 #define CCR 0xFF00001C macro
H A Dcpu_sh7724.h29 #define CCR 0xFF00001C macro
H A Dcpu_sh7757.h9 #define CCR 0xFF00001C macro
H A Dcpu_sh7752.h9 #define CCR 0xFF00001C macro
H A Dcpu_sh7753.h9 #define CCR 0xFF00001C macro
H A Dcpu_sh7720.h30 #define CCR 0xFFFFFFEC macro
H A Dcpu_sh7780.h28 #define CCR 0xFF00001C macro
/openbmc/u-boot/board/ms7750se/
H A Dlowlevel_init.S100 CCR_A: .long CCR
/openbmc/u-boot/board/renesas/r2dplus/
H A Dlowlevel_init.S73 CCR_A: .long CCR /* Cache Control Register */
/openbmc/u-boot/board/ms7722se/
H A Dlowlevel_init.S133 CCR_A: .long CCR
/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S119 CCR_A: .long CCR
/openbmc/u-boot/board/renesas/ecovec/
H A Dlowlevel_init.S194 CCR_A: .long CCR
/openbmc/u-boot/board/renesas/r7780mp/
H A Dlowlevel_init.S310 CCR_A: .long CCR
/openbmc/u-boot/board/renesas/sh7753evb/
H A Dlowlevel_init.S413 CCR_A: .long CCR

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