1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 21a2621baSYoshihiro Shimoda /* 31a2621baSYoshihiro Shimoda * Copyright (C) 2012 Renesas Solutions Corp. 41a2621baSYoshihiro Shimoda */ 51a2621baSYoshihiro Shimoda 61a2621baSYoshihiro Shimoda #ifndef _ASM_CPU_SH7752_H_ 71a2621baSYoshihiro Shimoda #define _ASM_CPU_SH7752_H_ 81a2621baSYoshihiro Shimoda 91a2621baSYoshihiro Shimoda #define CCR 0xFF00001C 101a2621baSYoshihiro Shimoda #define WTCNT 0xFFCC0000 111a2621baSYoshihiro Shimoda #define CCR_CACHE_INIT 0x0000090b 121a2621baSYoshihiro Shimoda #define CACHE_OC_NUM_WAYS 1 131a2621baSYoshihiro Shimoda 141a2621baSYoshihiro Shimoda #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 151a2621baSYoshihiro Shimoda /* MMU */ 161a2621baSYoshihiro Shimoda struct mmu_regs { 171a2621baSYoshihiro Shimoda unsigned int reserved[4]; 181a2621baSYoshihiro Shimoda unsigned int mmucr; 191a2621baSYoshihiro Shimoda }; 201a2621baSYoshihiro Shimoda #define MMU_BASE ((struct mmu_regs *)0xff000000) 211a2621baSYoshihiro Shimoda 221a2621baSYoshihiro Shimoda /* Watchdog */ 231a2621baSYoshihiro Shimoda #define WTCSR0 0xffcc0002 241a2621baSYoshihiro Shimoda #define WRSTCSR_R 0xffcc0003 251a2621baSYoshihiro Shimoda #define WRSTCSR_W 0xffcc0002 261a2621baSYoshihiro Shimoda #define WTCSR_PREFIX 0xa500 271a2621baSYoshihiro Shimoda #define WRSTCSR_PREFIX 0x6900 281a2621baSYoshihiro Shimoda #define WRSTCSR_WOVF_PREFIX 0x9600 291a2621baSYoshihiro Shimoda 301a2621baSYoshihiro Shimoda /* SCIF */ 311a2621baSYoshihiro Shimoda #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ 321a2621baSYoshihiro Shimoda #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ 331a2621baSYoshihiro Shimoda #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ 341a2621baSYoshihiro Shimoda 351a2621baSYoshihiro Shimoda /* TMU0 */ 361a2621baSYoshihiro Shimoda #define TMU_BASE 0xFE430000 371a2621baSYoshihiro Shimoda 381a2621baSYoshihiro Shimoda /* ETHER, GETHER MAC address */ 391a2621baSYoshihiro Shimoda struct ether_mac_regs { 401a2621baSYoshihiro Shimoda unsigned int reserved[114]; 411a2621baSYoshihiro Shimoda unsigned int mahr; 421a2621baSYoshihiro Shimoda unsigned int reserved2; 431a2621baSYoshihiro Shimoda unsigned int malr; 441a2621baSYoshihiro Shimoda }; 451a2621baSYoshihiro Shimoda #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) 461a2621baSYoshihiro Shimoda #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) 471a2621baSYoshihiro Shimoda #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) 481a2621baSYoshihiro Shimoda #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) 491a2621baSYoshihiro Shimoda 501a2621baSYoshihiro Shimoda /* GETHER */ 511a2621baSYoshihiro Shimoda struct gether_control_regs { 521a2621baSYoshihiro Shimoda unsigned int gbecont; 531a2621baSYoshihiro Shimoda }; 541a2621baSYoshihiro Shimoda #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) 551a2621baSYoshihiro Shimoda #define GBECONT_RMII1 0x00020000 561a2621baSYoshihiro Shimoda #define GBECONT_RMII0 0x00010000 571a2621baSYoshihiro Shimoda 581a2621baSYoshihiro Shimoda /* SerMux */ 591a2621baSYoshihiro Shimoda struct sermux_regs { 601a2621baSYoshihiro Shimoda unsigned char smr0; 611a2621baSYoshihiro Shimoda unsigned char smr1; 621a2621baSYoshihiro Shimoda unsigned char smr2; 631a2621baSYoshihiro Shimoda unsigned char smr3; 641a2621baSYoshihiro Shimoda unsigned char smr4; 651a2621baSYoshihiro Shimoda unsigned char smr5; 661a2621baSYoshihiro Shimoda }; 671a2621baSYoshihiro Shimoda #define SERMUX_BASE ((struct sermux_regs *)0xfe470000) 681a2621baSYoshihiro Shimoda 691a2621baSYoshihiro Shimoda 701a2621baSYoshihiro Shimoda /* USB0/1 */ 711a2621baSYoshihiro Shimoda struct usb_common_regs { 721a2621baSYoshihiro Shimoda unsigned short reserved[129]; 731a2621baSYoshihiro Shimoda unsigned short suspmode; 741a2621baSYoshihiro Shimoda }; 751a2621baSYoshihiro Shimoda #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) 761a2621baSYoshihiro Shimoda #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) 771a2621baSYoshihiro Shimoda 781a2621baSYoshihiro Shimoda struct usb0_phy_regs { 791a2621baSYoshihiro Shimoda unsigned short reset; 801a2621baSYoshihiro Shimoda unsigned short reserved[4]; 811a2621baSYoshihiro Shimoda unsigned short portsel; 821a2621baSYoshihiro Shimoda }; 831a2621baSYoshihiro Shimoda #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) 841a2621baSYoshihiro Shimoda 851a2621baSYoshihiro Shimoda struct usb1_port_regs { 861a2621baSYoshihiro Shimoda unsigned int port1sel; 871a2621baSYoshihiro Shimoda unsigned int reserved; 881a2621baSYoshihiro Shimoda unsigned int usb1intsts; 891a2621baSYoshihiro Shimoda }; 901a2621baSYoshihiro Shimoda #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) 911a2621baSYoshihiro Shimoda 921a2621baSYoshihiro Shimoda struct usb1_alignment_regs { 931a2621baSYoshihiro Shimoda unsigned int ehcidatac; /* 0xfe4fe018 */ 941a2621baSYoshihiro Shimoda unsigned int reserved[63]; 951a2621baSYoshihiro Shimoda unsigned int ohcidatac; 961a2621baSYoshihiro Shimoda }; 971a2621baSYoshihiro Shimoda #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) 981a2621baSYoshihiro Shimoda 991a2621baSYoshihiro Shimoda /* GPIO */ 1001a2621baSYoshihiro Shimoda struct gpio_regs { 1011a2621baSYoshihiro Shimoda unsigned short pacr; 1021a2621baSYoshihiro Shimoda unsigned short pbcr; 1031a2621baSYoshihiro Shimoda unsigned short pccr; 1041a2621baSYoshihiro Shimoda unsigned short pdcr; 1051a2621baSYoshihiro Shimoda unsigned short pecr; 1061a2621baSYoshihiro Shimoda unsigned short pfcr; 1071a2621baSYoshihiro Shimoda unsigned short pgcr; 1081a2621baSYoshihiro Shimoda unsigned short phcr; 1091a2621baSYoshihiro Shimoda unsigned short picr; 1101a2621baSYoshihiro Shimoda unsigned short pjcr; 1111a2621baSYoshihiro Shimoda unsigned short pkcr; 1121a2621baSYoshihiro Shimoda unsigned short plcr; 1131a2621baSYoshihiro Shimoda unsigned short pmcr; 1141a2621baSYoshihiro Shimoda unsigned short pncr; 1151a2621baSYoshihiro Shimoda unsigned short pocr; 1161a2621baSYoshihiro Shimoda unsigned short reserved; 1171a2621baSYoshihiro Shimoda unsigned short pqcr; 1181a2621baSYoshihiro Shimoda unsigned short prcr; 1191a2621baSYoshihiro Shimoda unsigned short pscr; 1201a2621baSYoshihiro Shimoda unsigned short ptcr; 1211a2621baSYoshihiro Shimoda unsigned short pucr; 1221a2621baSYoshihiro Shimoda unsigned short pvcr; 1231a2621baSYoshihiro Shimoda unsigned short pwcr; 1241a2621baSYoshihiro Shimoda unsigned short pxcr; 1251a2621baSYoshihiro Shimoda unsigned short pycr; 1261a2621baSYoshihiro Shimoda unsigned short pzcr; 1271a2621baSYoshihiro Shimoda unsigned char padr; 1281a2621baSYoshihiro Shimoda unsigned char reserved_a; 1291a2621baSYoshihiro Shimoda unsigned char pbdr; 1301a2621baSYoshihiro Shimoda unsigned char reserved_b; 1311a2621baSYoshihiro Shimoda unsigned char pcdr; 1321a2621baSYoshihiro Shimoda unsigned char reserved_c; 1331a2621baSYoshihiro Shimoda unsigned char pddr; 1341a2621baSYoshihiro Shimoda unsigned char reserved_d; 1351a2621baSYoshihiro Shimoda unsigned char pedr; 1361a2621baSYoshihiro Shimoda unsigned char reserved_e; 1371a2621baSYoshihiro Shimoda unsigned char pfdr; 1381a2621baSYoshihiro Shimoda unsigned char reserved_f; 1391a2621baSYoshihiro Shimoda unsigned char pgdr; 1401a2621baSYoshihiro Shimoda unsigned char reserved_g; 1411a2621baSYoshihiro Shimoda unsigned char phdr; 1421a2621baSYoshihiro Shimoda unsigned char reserved_h; 1431a2621baSYoshihiro Shimoda unsigned char pidr; 1441a2621baSYoshihiro Shimoda unsigned char reserved_i; 1451a2621baSYoshihiro Shimoda unsigned char pjdr; 1461a2621baSYoshihiro Shimoda unsigned char reserved_j; 1471a2621baSYoshihiro Shimoda unsigned char pkdr; 1481a2621baSYoshihiro Shimoda unsigned char reserved_k; 1491a2621baSYoshihiro Shimoda unsigned char pldr; 1501a2621baSYoshihiro Shimoda unsigned char reserved_l; 1511a2621baSYoshihiro Shimoda unsigned char pmdr; 1521a2621baSYoshihiro Shimoda unsigned char reserved_m; 1531a2621baSYoshihiro Shimoda unsigned char pndr; 1541a2621baSYoshihiro Shimoda unsigned char reserved_n; 1551a2621baSYoshihiro Shimoda unsigned char podr; 1561a2621baSYoshihiro Shimoda unsigned char reserved_o; 1571a2621baSYoshihiro Shimoda unsigned char ppdr; 1581a2621baSYoshihiro Shimoda unsigned char reserved_p; 1591a2621baSYoshihiro Shimoda unsigned char pqdr; 1601a2621baSYoshihiro Shimoda unsigned char reserved_q; 1611a2621baSYoshihiro Shimoda unsigned char prdr; 1621a2621baSYoshihiro Shimoda unsigned char reserved_r; 1631a2621baSYoshihiro Shimoda unsigned char psdr; 1641a2621baSYoshihiro Shimoda unsigned char reserved_s; 1651a2621baSYoshihiro Shimoda unsigned char ptdr; 1661a2621baSYoshihiro Shimoda unsigned char reserved_t; 1671a2621baSYoshihiro Shimoda unsigned char pudr; 1681a2621baSYoshihiro Shimoda unsigned char reserved_u; 1691a2621baSYoshihiro Shimoda unsigned char pvdr; 1701a2621baSYoshihiro Shimoda unsigned char reserved_v; 1711a2621baSYoshihiro Shimoda unsigned char pwdr; 1721a2621baSYoshihiro Shimoda unsigned char reserved_w; 1731a2621baSYoshihiro Shimoda unsigned char pxdr; 1741a2621baSYoshihiro Shimoda unsigned char reserved_x; 1751a2621baSYoshihiro Shimoda unsigned char pydr; 1761a2621baSYoshihiro Shimoda unsigned char reserved_y; 1771a2621baSYoshihiro Shimoda unsigned char pzdr; 1781a2621baSYoshihiro Shimoda unsigned char reserved_z; 1791a2621baSYoshihiro Shimoda unsigned short ncer; 1801a2621baSYoshihiro Shimoda unsigned short ncmcr; 1811a2621baSYoshihiro Shimoda unsigned short nccsr; 1821a2621baSYoshihiro Shimoda unsigned char reserved2[2]; 1831a2621baSYoshihiro Shimoda unsigned short psel0; /* +0x70 */ 1841a2621baSYoshihiro Shimoda unsigned short psel1; 1851a2621baSYoshihiro Shimoda unsigned short psel2; 1861a2621baSYoshihiro Shimoda unsigned short psel3; 1871a2621baSYoshihiro Shimoda unsigned short psel4; 1881a2621baSYoshihiro Shimoda unsigned short psel5; 1891a2621baSYoshihiro Shimoda unsigned short psel6; 1901a2621baSYoshihiro Shimoda unsigned short reserved3[2]; 1911a2621baSYoshihiro Shimoda unsigned short psel7; 1921a2621baSYoshihiro Shimoda }; 1931a2621baSYoshihiro Shimoda #define GPIO_BASE ((struct gpio_regs *)0xffec0000) 1941a2621baSYoshihiro Shimoda 1951a2621baSYoshihiro Shimoda #endif /* ifndef __ASSEMBLY__ */ 1961a2621baSYoshihiro Shimoda #endif /* _ASM_CPU_SH7752_H_ */ 197