xref: /openbmc/u-boot/arch/sh/include/asm/cpu_sh7724.h (revision 0eee446e)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2bead86a8SNobuhiro Iwamatsu /*
3bead86a8SNobuhiro Iwamatsu  * (C) Copyright 2008, 2011 Renesas Solutions Corp.
4bead86a8SNobuhiro Iwamatsu  *
5bead86a8SNobuhiro Iwamatsu  * SH7724 Internal I/O register
6bead86a8SNobuhiro Iwamatsu  */
7bead86a8SNobuhiro Iwamatsu 
8bead86a8SNobuhiro Iwamatsu #ifndef _ASM_CPU_SH7724_H_
9bead86a8SNobuhiro Iwamatsu #define _ASM_CPU_SH7724_H_
10bead86a8SNobuhiro Iwamatsu 
11bead86a8SNobuhiro Iwamatsu #define CACHE_OC_NUM_WAYS	4
12bead86a8SNobuhiro Iwamatsu #define CCR_CACHE_INIT	0x0000090d
13bead86a8SNobuhiro Iwamatsu 
14bead86a8SNobuhiro Iwamatsu /* EXP */
15bead86a8SNobuhiro Iwamatsu #define TRA		0xFF000020
16bead86a8SNobuhiro Iwamatsu #define EXPEVT	0xFF000024
17bead86a8SNobuhiro Iwamatsu #define INTEVT	0xFF000028
18bead86a8SNobuhiro Iwamatsu 
19bead86a8SNobuhiro Iwamatsu /* MMU */
20bead86a8SNobuhiro Iwamatsu #define PTEH	0xFF000000
21bead86a8SNobuhiro Iwamatsu #define PTEL	0xFF000004
22bead86a8SNobuhiro Iwamatsu #define TTB		0xFF000008
23bead86a8SNobuhiro Iwamatsu #define TEA		0xFF00000C
24bead86a8SNobuhiro Iwamatsu #define MMUCR	0xFF000010
25bead86a8SNobuhiro Iwamatsu #define PASCR	0xFF000070
26bead86a8SNobuhiro Iwamatsu #define IRMCR	0xFF000078
27bead86a8SNobuhiro Iwamatsu 
28bead86a8SNobuhiro Iwamatsu /* CACHE */
29bead86a8SNobuhiro Iwamatsu #define CCR		0xFF00001C
30bead86a8SNobuhiro Iwamatsu #define RAMCR	0xFF000074
31bead86a8SNobuhiro Iwamatsu 
32bead86a8SNobuhiro Iwamatsu /* INTC */
33bead86a8SNobuhiro Iwamatsu 
34bead86a8SNobuhiro Iwamatsu /* BSC */
35bead86a8SNobuhiro Iwamatsu #define MMSELR		0xFF800020
36bead86a8SNobuhiro Iwamatsu #define CMNCR		0xFEC10000
37bead86a8SNobuhiro Iwamatsu #define	CS0BCR		0xFEC10004
38bead86a8SNobuhiro Iwamatsu #define CS2BCR		0xFEC10008
39bead86a8SNobuhiro Iwamatsu #define CS4BCR		0xFEC10010
40bead86a8SNobuhiro Iwamatsu #define CS5ABCR		0xFEC10014
41bead86a8SNobuhiro Iwamatsu #define CS5BBCR		0xFEC10018
42bead86a8SNobuhiro Iwamatsu #define CS6ABCR		0xFEC1001C
43bead86a8SNobuhiro Iwamatsu #define CS6BBCR		0xFEC10020
44bead86a8SNobuhiro Iwamatsu #define CS0WCR		0xFEC10024
45bead86a8SNobuhiro Iwamatsu #define CS2WCR		0xFEC10028
46bead86a8SNobuhiro Iwamatsu #define CS4WCR		0xFEC10030
47bead86a8SNobuhiro Iwamatsu #define CS5AWCR		0xFEC10034
48bead86a8SNobuhiro Iwamatsu #define CS5BWCR		0xFEC10038
49bead86a8SNobuhiro Iwamatsu #define CS6AWCR		0xFEC1003C
50bead86a8SNobuhiro Iwamatsu #define CS6BWCR		0xFEC10040
51bead86a8SNobuhiro Iwamatsu #define RBWTCNT		0xFEC10054
52bead86a8SNobuhiro Iwamatsu 
53bead86a8SNobuhiro Iwamatsu /* SBSC */
54bead86a8SNobuhiro Iwamatsu #define SBSC_SDCR	0xFE400008
55bead86a8SNobuhiro Iwamatsu #define SBSC_SDWCR	0xFE40000C
56bead86a8SNobuhiro Iwamatsu #define SBSC_SDPCR	0xFE400010
57bead86a8SNobuhiro Iwamatsu #define SBSC_RTCSR	0xFE400014
58bead86a8SNobuhiro Iwamatsu #define SBSC_RTCNT	0xFE400018
59bead86a8SNobuhiro Iwamatsu #define SBSC_RTCOR	0xFE40001C
60bead86a8SNobuhiro Iwamatsu #define SBSC_RFCR	0xFE400020
61bead86a8SNobuhiro Iwamatsu 
62bead86a8SNobuhiro Iwamatsu /* DSBC */
63bead86a8SNobuhiro Iwamatsu #define DBKIND		0xFD000008
64bead86a8SNobuhiro Iwamatsu #define DBSTATE		0xFD00000C
65bead86a8SNobuhiro Iwamatsu #define DBEN		0xFD000010
66bead86a8SNobuhiro Iwamatsu #define DBCMDCNT	0xFD000014
67bead86a8SNobuhiro Iwamatsu #define DBCKECNT	0xFD000018
68bead86a8SNobuhiro Iwamatsu #define DBCONF		0xFD000020
69bead86a8SNobuhiro Iwamatsu #define DBTR0		0xFD000030
70bead86a8SNobuhiro Iwamatsu #define DBTR1		0xFD000034
71bead86a8SNobuhiro Iwamatsu #define DBTR2		0xFD000038
72bead86a8SNobuhiro Iwamatsu #define DBTR3		0xFD00003C
73bead86a8SNobuhiro Iwamatsu #define DBRFPDN0	0xFD000040
74bead86a8SNobuhiro Iwamatsu #define DBRFPDN1	0xFD000044
75bead86a8SNobuhiro Iwamatsu #define DBRFPDN2	0xFD000048
76bead86a8SNobuhiro Iwamatsu #define DBRFSTS		0xFD00004C
77bead86a8SNobuhiro Iwamatsu #define DBMRCNT		0xFD000060
78bead86a8SNobuhiro Iwamatsu #define DBPDCNT0	0xFD000108
79bead86a8SNobuhiro Iwamatsu 
80bead86a8SNobuhiro Iwamatsu /* DMAC */
81bead86a8SNobuhiro Iwamatsu 
82bead86a8SNobuhiro Iwamatsu /* CPG */
83bead86a8SNobuhiro Iwamatsu #define FRQCRA		0xA4150000
84bead86a8SNobuhiro Iwamatsu #define FRQCRB		0xA4150004
85bead86a8SNobuhiro Iwamatsu #define FRQCR		FRQCRA
86bead86a8SNobuhiro Iwamatsu #define VCLKCR      0xA4150004
87bead86a8SNobuhiro Iwamatsu #define SCLKACR     0xA4150008
88bead86a8SNobuhiro Iwamatsu #define SCLKBCR     0xA415000C
89bead86a8SNobuhiro Iwamatsu #define IRDACLKCR   0xA4150018
90bead86a8SNobuhiro Iwamatsu #define PLLCR       0xA4150024
91bead86a8SNobuhiro Iwamatsu #define DLLFRQ      0xA4150050
92bead86a8SNobuhiro Iwamatsu 
93bead86a8SNobuhiro Iwamatsu /* LOW POWER MODE */
94bead86a8SNobuhiro Iwamatsu #define STBCR       0xA4150020
95bead86a8SNobuhiro Iwamatsu #define MSTPCR0     0xA4150030
96bead86a8SNobuhiro Iwamatsu #define MSTPCR1     0xA4150034
97bead86a8SNobuhiro Iwamatsu #define MSTPCR2     0xA4150038
98bead86a8SNobuhiro Iwamatsu 
99bead86a8SNobuhiro Iwamatsu /* RWDT */
100bead86a8SNobuhiro Iwamatsu #define RWTCNT      0xA4520000
101bead86a8SNobuhiro Iwamatsu #define RWTCSR      0xA4520004
102bead86a8SNobuhiro Iwamatsu #define WTCNT		RWTCNT
103bead86a8SNobuhiro Iwamatsu 
104bead86a8SNobuhiro Iwamatsu /* TMU */
10573f35e0bSNobuhiro Iwamatsu #define TMU_BASE	0xFFD80000
106bead86a8SNobuhiro Iwamatsu 
107bead86a8SNobuhiro Iwamatsu /* TPU */
108bead86a8SNobuhiro Iwamatsu 
109bead86a8SNobuhiro Iwamatsu /* CMT */
110bead86a8SNobuhiro Iwamatsu #define CMSTR       0xA44A0000
111bead86a8SNobuhiro Iwamatsu #define CMCSR       0xA44A0060
112bead86a8SNobuhiro Iwamatsu #define CMCNT       0xA44A0064
113bead86a8SNobuhiro Iwamatsu #define CMCOR       0xA44A0068
114bead86a8SNobuhiro Iwamatsu 
115bead86a8SNobuhiro Iwamatsu /* MSIOF */
116bead86a8SNobuhiro Iwamatsu 
117bead86a8SNobuhiro Iwamatsu /* SCIF */
118bead86a8SNobuhiro Iwamatsu #define SCIF0_BASE  0xFFE00000
119bead86a8SNobuhiro Iwamatsu #define SCIF1_BASE  0xFFE10000
120bead86a8SNobuhiro Iwamatsu #define SCIF2_BASE  0xFFE20000
121bead86a8SNobuhiro Iwamatsu #define SCIF3_BASE  0xa4e30000
122bead86a8SNobuhiro Iwamatsu #define SCIF4_BASE  0xa4e40000
123bead86a8SNobuhiro Iwamatsu #define SCIF5_BASE  0xa4e50000
124bead86a8SNobuhiro Iwamatsu 
125bead86a8SNobuhiro Iwamatsu /* RTC */
126bead86a8SNobuhiro Iwamatsu /* IrDA */
127bead86a8SNobuhiro Iwamatsu /* KEYSC */
128bead86a8SNobuhiro Iwamatsu /* USB */
129bead86a8SNobuhiro Iwamatsu /* IIC */
130bead86a8SNobuhiro Iwamatsu /* FLCTL */
131bead86a8SNobuhiro Iwamatsu /* VPU */
132bead86a8SNobuhiro Iwamatsu /* VIO(CEU) */
133bead86a8SNobuhiro Iwamatsu /* VIO(VEU) */
134bead86a8SNobuhiro Iwamatsu /* VIO(BEU) */
135bead86a8SNobuhiro Iwamatsu /* 2DG */
136bead86a8SNobuhiro Iwamatsu /* LCDC */
137bead86a8SNobuhiro Iwamatsu /* VOU */
138bead86a8SNobuhiro Iwamatsu /* TSIF */
139bead86a8SNobuhiro Iwamatsu /* SIU */
140bead86a8SNobuhiro Iwamatsu /* ATAPI */
141bead86a8SNobuhiro Iwamatsu 
142bead86a8SNobuhiro Iwamatsu /* PFC */
143bead86a8SNobuhiro Iwamatsu #define PACR        0xA4050100
144bead86a8SNobuhiro Iwamatsu #define PBCR        0xA4050102
145bead86a8SNobuhiro Iwamatsu #define PCCR        0xA4050104
146bead86a8SNobuhiro Iwamatsu #define PDCR        0xA4050106
147bead86a8SNobuhiro Iwamatsu #define PECR        0xA4050108
148bead86a8SNobuhiro Iwamatsu #define PFCR        0xA405010A
149bead86a8SNobuhiro Iwamatsu #define PGCR        0xA405010C
150bead86a8SNobuhiro Iwamatsu #define PHCR        0xA405010E
151bead86a8SNobuhiro Iwamatsu #define PJCR        0xA4050110
152bead86a8SNobuhiro Iwamatsu #define PKCR        0xA4050112
153bead86a8SNobuhiro Iwamatsu #define PLCR        0xA4050114
154bead86a8SNobuhiro Iwamatsu #define PMCR        0xA4050116
155bead86a8SNobuhiro Iwamatsu #define PNCR        0xA4050118
156bead86a8SNobuhiro Iwamatsu #define PQCR        0xA405011A
157bead86a8SNobuhiro Iwamatsu #define PRCR        0xA405011C
158bead86a8SNobuhiro Iwamatsu #define PSCR        0xA405011E
159bead86a8SNobuhiro Iwamatsu #define PTCR        0xA4050140
160bead86a8SNobuhiro Iwamatsu #define PUCR        0xA4050142
161bead86a8SNobuhiro Iwamatsu #define PVCR        0xA4050144
162bead86a8SNobuhiro Iwamatsu #define PWCR        0xA4050146
163bead86a8SNobuhiro Iwamatsu #define PXCR        0xA4050148
164bead86a8SNobuhiro Iwamatsu #define PYCR        0xA405014A
165bead86a8SNobuhiro Iwamatsu #define PZCR        0xA405014C
166bead86a8SNobuhiro Iwamatsu #define PSELA       0xA405014E
167bead86a8SNobuhiro Iwamatsu #define PSELB       0xA4050150
168bead86a8SNobuhiro Iwamatsu #define PSELC       0xA4050152
169bead86a8SNobuhiro Iwamatsu #define PSELD       0xA4050154
170bead86a8SNobuhiro Iwamatsu #define PSELE       0xA4050156
171bead86a8SNobuhiro Iwamatsu #define HIZCRA      0xA4050158
172bead86a8SNobuhiro Iwamatsu #define HIZCRB      0xA405015A
173bead86a8SNobuhiro Iwamatsu #define HIZCRC      0xA405015C
174bead86a8SNobuhiro Iwamatsu #define HIZCRD      0xA405015E
175bead86a8SNobuhiro Iwamatsu #define MSELCRA     0xA4050180
176bead86a8SNobuhiro Iwamatsu #define MSELCRB     0xA4050182
177bead86a8SNobuhiro Iwamatsu #define PULCR       0xA4050184
178bead86a8SNobuhiro Iwamatsu #define DRVCRA      0xA405018A
179bead86a8SNobuhiro Iwamatsu #define DRVCRB      0xA405018C
180bead86a8SNobuhiro Iwamatsu 
181bead86a8SNobuhiro Iwamatsu /* I/O Port */
182bead86a8SNobuhiro Iwamatsu #define PADR        0xA4050120
183bead86a8SNobuhiro Iwamatsu #define PBDR        0xA4050122
184bead86a8SNobuhiro Iwamatsu #define PCDR        0xA4050124
185bead86a8SNobuhiro Iwamatsu #define PDDR        0xA4050126
186bead86a8SNobuhiro Iwamatsu #define PEDR        0xA4050128
187bead86a8SNobuhiro Iwamatsu #define PFDR        0xA405012A
188bead86a8SNobuhiro Iwamatsu #define PGDR        0xA405012C
189bead86a8SNobuhiro Iwamatsu #define PHDR        0xA405012E
190bead86a8SNobuhiro Iwamatsu #define PJDR        0xA4050130
191bead86a8SNobuhiro Iwamatsu #define PKDR        0xA4050132
192bead86a8SNobuhiro Iwamatsu #define PLDR        0xA4050134
193bead86a8SNobuhiro Iwamatsu #define PMDR        0xA4050136
194bead86a8SNobuhiro Iwamatsu #define PNDR        0xA4050138
195bead86a8SNobuhiro Iwamatsu #define PQDR        0xA405013A
196bead86a8SNobuhiro Iwamatsu #define PRDR        0xA405013C
197bead86a8SNobuhiro Iwamatsu #define PSDR        0xA405013E
198bead86a8SNobuhiro Iwamatsu #define PTDR        0xA4050160
199bead86a8SNobuhiro Iwamatsu #define PUDR        0xA4050162
200bead86a8SNobuhiro Iwamatsu #define PVDR        0xA4050164
201bead86a8SNobuhiro Iwamatsu #define PWDR        0xA4050166
20219bb5e4bSBaruch Siach #define PXDR        0xA4050168
20319bb5e4bSBaruch Siach #define PYDR        0xA405016A
20419bb5e4bSBaruch Siach #define PZDR        0xA405016C
205bead86a8SNobuhiro Iwamatsu 
206bead86a8SNobuhiro Iwamatsu /* UBC */
207bead86a8SNobuhiro Iwamatsu /* H-UDI */
208bead86a8SNobuhiro Iwamatsu 
209bead86a8SNobuhiro Iwamatsu #endif /* _ASM_CPU_SH7724_H_ */
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