1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2819833afSPeter Tyser #ifndef _ASM_CPU_SH7780_H_ 3819833afSPeter Tyser #define _ASM_CPU_SH7780_H_ 4819833afSPeter Tyser 5819833afSPeter Tyser /* 6819833afSPeter Tyser * Copyright (c) 2007,2008 Nobuhiro Iwamatsu 7819833afSPeter Tyser * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com> 8819833afSPeter Tyser */ 9819833afSPeter Tyser 10819833afSPeter Tyser #define CACHE_OC_NUM_WAYS 1 11819833afSPeter Tyser #define CCR_CACHE_INIT 0x0000090b 12819833afSPeter Tyser 13819833afSPeter Tyser /* Exceptions */ 14819833afSPeter Tyser #define TRA 0xFF000020 15819833afSPeter Tyser #define EXPEVT 0xFF000024 16819833afSPeter Tyser #define INTEVT 0xFF000028 17819833afSPeter Tyser 18819833afSPeter Tyser /* Memory Management Unit */ 19819833afSPeter Tyser #define PTEH 0xFF000000 20819833afSPeter Tyser #define PTEL 0xFF000004 21819833afSPeter Tyser #define TTB 0xFF000008 22819833afSPeter Tyser #define TEA 0xFF00000C 23819833afSPeter Tyser #define MMUCR 0xFF000010 24819833afSPeter Tyser #define PASCR 0xFF000070 25819833afSPeter Tyser #define IRMCR 0xFF000078 26819833afSPeter Tyser 27819833afSPeter Tyser /* Cache Controller */ 28819833afSPeter Tyser #define CCR 0xFF00001C 29819833afSPeter Tyser #define QACR0 0xFF000038 30819833afSPeter Tyser #define QACR1 0xFF00003C 31819833afSPeter Tyser #define RAMCR 0xFF000074 32819833afSPeter Tyser 33819833afSPeter Tyser /* L Memory */ 34819833afSPeter Tyser #define RAMCR 0xFF000074 35819833afSPeter Tyser #define LSA0 0xFF000050 36819833afSPeter Tyser #define LSA1 0xFF000054 37819833afSPeter Tyser #define LDA0 0xFF000058 38819833afSPeter Tyser #define LDA1 0xFF00005C 39819833afSPeter Tyser 40819833afSPeter Tyser /* Interrupt Controller */ 41819833afSPeter Tyser #define ICR0 0xFFD00000 42819833afSPeter Tyser #define ICR1 0xFFD0001C 43819833afSPeter Tyser #define INTPRI 0xFFD00010 44819833afSPeter Tyser #define INTREQ 0xFFD00024 45819833afSPeter Tyser #define INTMSK0 0xFFD00044 46819833afSPeter Tyser #define INTMSK1 0xFFD00048 47819833afSPeter Tyser #define INTMSK2 0xFFD40080 48819833afSPeter Tyser #define INTMSKCLR0 0xFFD00064 49819833afSPeter Tyser #define INTMSKCLR1 0xFFD00068 50819833afSPeter Tyser #define INTMSKCLR2 0xFFD40084 51819833afSPeter Tyser #define NMIFCR 0xFFD000C0 52819833afSPeter Tyser #define USERIMASK 0xFFD30000 53819833afSPeter Tyser #define INT2PRI0 0xFFD40000 54819833afSPeter Tyser #define INT2PRI1 0xFFD40004 55819833afSPeter Tyser #define INT2PRI2 0xFFD40008 56819833afSPeter Tyser #define INT2PRI3 0xFFD4000C 57819833afSPeter Tyser #define INT2PRI4 0xFFD40010 58819833afSPeter Tyser #define INT2PRI5 0xFFD40014 59819833afSPeter Tyser #define INT2PRI6 0xFFD40018 60819833afSPeter Tyser #define INT2PRI7 0xFFD4001C 61819833afSPeter Tyser #define INT2A0 0xFFD40030 62819833afSPeter Tyser #define INT2A1 0xFFD40034 63819833afSPeter Tyser #define INT2MSKR 0xFFD40038 64819833afSPeter Tyser #define INT2MSKCR 0xFFD4003C 65819833afSPeter Tyser #define INT2B0 0xFFD40040 66819833afSPeter Tyser #define INT2B1 0xFFD40044 67819833afSPeter Tyser #define INT2B2 0xFFD40048 68819833afSPeter Tyser #define INT2B3 0xFFD4004C 69819833afSPeter Tyser #define INT2B4 0xFFD40050 70819833afSPeter Tyser #define INT2B5 0xFFD40054 71819833afSPeter Tyser #define INT2B6 0xFFD40058 72819833afSPeter Tyser #define INT2B7 0xFFD4005C 73819833afSPeter Tyser #define INT2GPIC 0xFFD40090 74819833afSPeter Tyser 75819833afSPeter Tyser /* local Bus State Controller */ 76819833afSPeter Tyser #define MMSELR 0xFF400020 77819833afSPeter Tyser #define BCR 0xFF801000 78819833afSPeter Tyser #define CS0BCR 0xFF802000 79819833afSPeter Tyser #define CS1BCR 0xFF802010 80819833afSPeter Tyser #define CS2BCR 0xFF802020 81819833afSPeter Tyser #define CS4BCR 0xFF802040 82819833afSPeter Tyser #define CS5BCR 0xFF802050 83819833afSPeter Tyser #define CS6BCR 0xFF802060 84819833afSPeter Tyser #define CS0WCR 0xFF802008 85819833afSPeter Tyser #define CS1WCR 0xFF802018 86819833afSPeter Tyser #define CS2WCR 0xFF802028 87819833afSPeter Tyser #define CS4WCR 0xFF802048 88819833afSPeter Tyser #define CS5WCR 0xFF802058 89819833afSPeter Tyser #define CS6WCR 0xFF802068 90819833afSPeter Tyser #define CS5PCR 0xFF802070 91819833afSPeter Tyser #define CS6PCR 0xFF802080 92819833afSPeter Tyser 93819833afSPeter Tyser /* DDR-SDRAM I/F */ 94819833afSPeter Tyser #define MIM_1 0xFE800008 95819833afSPeter Tyser #define MIM_2 0xFE80000C 96819833afSPeter Tyser #define SCR_1 0xFE800010 97819833afSPeter Tyser #define SCR_2 0xFE800014 98819833afSPeter Tyser #define STR_1 0xFE800018 99819833afSPeter Tyser #define STR_2 0xFE80001C 100819833afSPeter Tyser #define SDR_1 0xFE800030 101819833afSPeter Tyser #define SDR_2 0xFE800034 102819833afSPeter Tyser #define DBK_1 0xFE800400 103819833afSPeter Tyser #define DBK_2 0xFE800404 104819833afSPeter Tyser 105819833afSPeter Tyser /* PCI Controller */ 106819833afSPeter Tyser #define SH7780_PCIECR 0xFE000008 107819833afSPeter Tyser #define SH7780_PCIVID 0xFE040000 108819833afSPeter Tyser #define SH7780_PCIDID 0xFE040002 109819833afSPeter Tyser #define SH7780_PCICMD 0xFE040004 110819833afSPeter Tyser #define SH7780_PCISTATUS 0xFE040006 111819833afSPeter Tyser #define SH7780_PCIRID 0xFE040008 112819833afSPeter Tyser #define SH7780_PCIPIF 0xFE040009 113819833afSPeter Tyser #define SH7780_PCISUB 0xFE04000A 114819833afSPeter Tyser #define SH7780_PCIBCC 0xFE04000B 115819833afSPeter Tyser #define SH7780_PCICLS 0xFE04000C 116819833afSPeter Tyser #define SH7780_PCILTM 0xFE04000D 117819833afSPeter Tyser #define SH7780_PCIHDR 0xFE04000E 118819833afSPeter Tyser #define SH7780_PCIBIST 0xFE04000F 119819833afSPeter Tyser #define SH7780_PCIIBAR 0xFE040010 120819833afSPeter Tyser #define SH7780_PCIMBAR0 0xFE040014 121819833afSPeter Tyser #define SH7780_PCIMBAR1 0xFE040018 122819833afSPeter Tyser #define SH7780_PCISVID 0xFE04002C 123819833afSPeter Tyser #define SH7780_PCISID 0xFE04002E 124819833afSPeter Tyser #define SH7780_PCICP 0xFE040034 125819833afSPeter Tyser #define SH7780_PCIINTLINE 0xFE04003C 126819833afSPeter Tyser #define SH7780_PCIINTPIN 0xFE04003D 127819833afSPeter Tyser #define SH7780_PCIMINGNT 0xFE04003E 128819833afSPeter Tyser #define SH7780_PCIMAXLAT 0xFE04003F 129819833afSPeter Tyser #define SH7780_PCICID 0xFE040040 130819833afSPeter Tyser #define SH7780_PCINIP 0xFE040041 131819833afSPeter Tyser #define SH7780_PCIPMC 0xFE040042 132819833afSPeter Tyser #define SH7780_PCIPMCSR 0xFE040044 133819833afSPeter Tyser #define SH7780_PCIPMCSRBSE 0xFE040046 134819833afSPeter Tyser #define SH7780_PCI_CDD 0xFE040047 135819833afSPeter Tyser #define SH7780_PCICR 0xFE040100 136819833afSPeter Tyser #define SH7780_PCILSR0 0xFE040104 137819833afSPeter Tyser #define SH7780_PCILSR1 0xFE040108 138819833afSPeter Tyser #define SH7780_PCILAR0 0xFE04010C 139819833afSPeter Tyser #define SH7780_PCILAR1 0xFE040110 140819833afSPeter Tyser #define SH7780_PCIIR 0xFE040114 141819833afSPeter Tyser #define SH7780_PCIIMR 0xFE040118 142819833afSPeter Tyser #define SH7780_PCIAIR 0xFE04011C 143819833afSPeter Tyser #define SH7780_PCICIR 0xFE040120 144819833afSPeter Tyser #define SH7780_PCIAINT 0xFE040130 145819833afSPeter Tyser #define SH7780_PCIAINTM 0xFE040134 146819833afSPeter Tyser #define SH7780_PCIBMIR 0xFE040138 147819833afSPeter Tyser #define SH7780_PCIPAR 0xFE0401C0 148819833afSPeter Tyser #define SH7780_PCIPINT 0xFE0401CC 149819833afSPeter Tyser #define SH7780_PCIPINTM 0xFE0401D0 150819833afSPeter Tyser #define SH7780_PCIMBR0 0xFE0401E0 151819833afSPeter Tyser #define SH7780_PCIMBMR0 0xFE0401E4 152819833afSPeter Tyser #define SH7780_PCIMBR1 0xFE0401E8 153819833afSPeter Tyser #define SH7780_PCIMBMR1 0xFE0401EC 154819833afSPeter Tyser #define SH7780_PCIMBR2 0xFE0401F0 155819833afSPeter Tyser #define SH7780_PCIMBMR2 0xFE0401F4 156819833afSPeter Tyser #define SH7780_PCIIOBR 0xFE0401F8 157819833afSPeter Tyser #define SH7780_PCIIOBMR 0xFE0401FC 158819833afSPeter Tyser #define SH7780_PCICSCR0 0xFE040210 159819833afSPeter Tyser #define SH7780_PCICSCR1 0xFE040214 160819833afSPeter Tyser #define SH7780_PCICSAR0 0xFE040218 161819833afSPeter Tyser #define SH7780_PCICSAR1 0xFE04021C 162819833afSPeter Tyser #define SH7780_PCIPDR 0xFE040220 163819833afSPeter Tyser 164819833afSPeter Tyser /* DMAC */ 165819833afSPeter Tyser #define DMAC_SAR0 0xFC808020 166819833afSPeter Tyser #define DMAC_DAR0 0xFC808024 167819833afSPeter Tyser #define DMAC_TCR0 0xFC808028 168819833afSPeter Tyser #define DMAC_CHCR0 0xFC80802C 169819833afSPeter Tyser #define DMAC_SAR1 0xFC808030 170819833afSPeter Tyser #define DMAC_DAR1 0xFC808034 171819833afSPeter Tyser #define DMAC_TCR1 0xFC808038 172819833afSPeter Tyser #define DMAC_CHCR1 0xFC80803C 173819833afSPeter Tyser #define DMAC_SAR2 0xFC808040 174819833afSPeter Tyser #define DMAC_DAR2 0xFC808044 175819833afSPeter Tyser #define DMAC_TCR2 0xFC808048 176819833afSPeter Tyser #define DMAC_CHCR2 0xFC80804C 177819833afSPeter Tyser #define DMAC_SAR3 0xFC808050 178819833afSPeter Tyser #define DMAC_DAR3 0xFC808054 179819833afSPeter Tyser #define DMAC_TCR3 0xFC808058 180819833afSPeter Tyser #define DMAC_CHCR3 0xFC80805C 181819833afSPeter Tyser #define DMAC_DMAOR0 0xFC808060 182819833afSPeter Tyser #define DMAC_SAR4 0xFC808070 183819833afSPeter Tyser #define DMAC_DAR4 0xFC808074 184819833afSPeter Tyser #define DMAC_TCR4 0xFC808078 185819833afSPeter Tyser #define DMAC_CHCR4 0xFC80807C 186819833afSPeter Tyser #define DMAC_SAR5 0xFC808080 187819833afSPeter Tyser #define DMAC_DAR5 0xFC808084 188819833afSPeter Tyser #define DMAC_TCR5 0xFC808088 189819833afSPeter Tyser #define DMAC_CHCR5 0xFC80808C 190819833afSPeter Tyser #define DMAC_SARB0 0xFC808120 191819833afSPeter Tyser #define DMAC_DARB0 0xFC808124 192819833afSPeter Tyser #define DMAC_TCRB0 0xFC808128 193819833afSPeter Tyser #define DMAC_SARB1 0xFC808130 194819833afSPeter Tyser #define DMAC_DARB1 0xFC808134 195819833afSPeter Tyser #define DMAC_TCRB1 0xFC808138 196819833afSPeter Tyser #define DMAC_SARB2 0xFC808140 197819833afSPeter Tyser #define DMAC_DARB2 0xFC808144 198819833afSPeter Tyser #define DMAC_TCRB2 0xFC808148 199819833afSPeter Tyser #define DMAC_SARB3 0xFC808150 200819833afSPeter Tyser #define DMAC_DARB3 0xFC808154 201819833afSPeter Tyser #define DMAC_TCRB3 0xFC808158 202819833afSPeter Tyser #define DMAC_DMARS0 0xFC809000 203819833afSPeter Tyser #define DMAC_DMARS1 0xFC809004 204819833afSPeter Tyser #define DMAC_DMARS2 0xFC809008 205819833afSPeter Tyser #define DMAC_SAR6 0xFC818020 206819833afSPeter Tyser #define DMAC_DAR6 0xFC818024 207819833afSPeter Tyser #define DMAC_TCR6 0xFC818028 208819833afSPeter Tyser #define DMAC_CHCR6 0xFC81802C 209819833afSPeter Tyser #define DMAC_SAR7 0xFC818030 210819833afSPeter Tyser #define DMAC_DAR7 0xFC818034 211819833afSPeter Tyser #define DMAC_TCR7 0xFC818038 212819833afSPeter Tyser #define DMAC_CHCR7 0xFC81803C 213819833afSPeter Tyser #define DMAC_SAR8 0xFC818040 214819833afSPeter Tyser #define DMAC_DAR8 0xFC818044 215819833afSPeter Tyser #define DMAC_TCR8 0xFC818048 216819833afSPeter Tyser #define DMAC_CHCR8 0xFC81804C 217819833afSPeter Tyser #define DMAC_SAR9 0xFC818050 218819833afSPeter Tyser #define DMAC_DAR9 0xFC818054 219819833afSPeter Tyser #define DMAC_TCR9 0xFC818058 220819833afSPeter Tyser #define DMAC_CHCR9 0xFC81805C 221819833afSPeter Tyser #define DMAC_DMAOR1 0xFC818060 222819833afSPeter Tyser #define DMAC_SAR10 0xFC818070 223819833afSPeter Tyser #define DMAC_DAR10 0xFC818074 224819833afSPeter Tyser #define DMAC_TCR10 0xFC818078 225819833afSPeter Tyser #define DMAC_CHCR10 0xFC81807C 226819833afSPeter Tyser #define DMAC_SAR11 0xFC818080 227819833afSPeter Tyser #define DMAC_DAR11 0xFC818084 228819833afSPeter Tyser #define DMAC_TCR11 0xFC818088 229819833afSPeter Tyser #define DMAC_CHCR11 0xFC81808C 230819833afSPeter Tyser #define DMAC_SARB6 0xFC818120 231819833afSPeter Tyser #define DMAC_DARB6 0xFC818124 232819833afSPeter Tyser #define DMAC_TCRB6 0xFC818128 233819833afSPeter Tyser #define DMAC_SARB7 0xFC818130 234819833afSPeter Tyser #define DMAC_DARB7 0xFC818134 235819833afSPeter Tyser #define DMAC_TCRB7 0xFC818138 236819833afSPeter Tyser #define DMAC_SARB8 0xFC818140 237819833afSPeter Tyser #define DMAC_DARB8 0xFC818144 238819833afSPeter Tyser #define DMAC_TCRB8 0xFC818148 239819833afSPeter Tyser #define DMAC_SARB9 0xFC818150 240819833afSPeter Tyser #define DMAC_DARB9 0xFC818154 241819833afSPeter Tyser #define DMAC_TCRB9 0xFC818158 242819833afSPeter Tyser 243819833afSPeter Tyser /* Clock Pulse Generator */ 244819833afSPeter Tyser #define FRQCR 0xFFC80000 245819833afSPeter Tyser #define PLLCR 0xFFC80024 246819833afSPeter Tyser #define MSTPCR 0xFFC80030 247819833afSPeter Tyser 248819833afSPeter Tyser /* Watchdog Timer and Reset */ 249819833afSPeter Tyser #define WTCNT WDTCNT 250819833afSPeter Tyser #define WDTST 0xFFCC0000 251819833afSPeter Tyser #define WDTCSR 0xFFCC0004 252819833afSPeter Tyser #define WDTBST 0xFFCC0008 253819833afSPeter Tyser #define WDTCNT 0xFFCC0010 254819833afSPeter Tyser #define WDTBCNT 0xFFCC0018 255819833afSPeter Tyser 256819833afSPeter Tyser /* System Control */ 257819833afSPeter Tyser #define MSTPCR 0xFFC80030 258819833afSPeter Tyser 259819833afSPeter Tyser /* Timer Unit */ 26073f35e0bSNobuhiro Iwamatsu #define TMU_BASE 0xFFD80000 261819833afSPeter Tyser 262819833afSPeter Tyser /* Timer/Counter */ 263819833afSPeter Tyser #define CMTCFG 0xFFE30000 264819833afSPeter Tyser #define CMTFRT 0xFFE30004 265819833afSPeter Tyser #define CMTCTL 0xFFE30008 266819833afSPeter Tyser #define CMTIRQS 0xFFE3000C 267819833afSPeter Tyser #define CMTCH0T 0xFFE30010 268819833afSPeter Tyser #define CMTCH0ST 0xFFE30020 269819833afSPeter Tyser #define CMTCH0C 0xFFE30030 270819833afSPeter Tyser #define CMTCH1T 0xFFE30014 271819833afSPeter Tyser #define CMTCH1ST 0xFFE30024 272819833afSPeter Tyser #define CMTCH1C 0xFFE30034 273819833afSPeter Tyser #define CMTCH2T 0xFFE30018 274819833afSPeter Tyser #define CMTCH2C 0xFFE30038 275819833afSPeter Tyser #define CMTCH3T 0xFFE3001C 276819833afSPeter Tyser #define CMTCH3C 0xFFE3003C 277819833afSPeter Tyser 278819833afSPeter Tyser /* Realtime Clock */ 279819833afSPeter Tyser #define R64CNT 0xFFE80000 280819833afSPeter Tyser #define RSECCNT 0xFFE80004 281819833afSPeter Tyser #define RMINCNT 0xFFE80008 282819833afSPeter Tyser #define RHRCNT 0xFFE8000C 283819833afSPeter Tyser #define RWKCNT 0xFFE80010 284819833afSPeter Tyser #define RDAYCNT 0xFFE80014 285819833afSPeter Tyser #define RMONCNT 0xFFE80018 286819833afSPeter Tyser #define RYRCNT 0xFFE8001C 287819833afSPeter Tyser #define RSECAR 0xFFE80020 288819833afSPeter Tyser #define RMINAR 0xFFE80024 289819833afSPeter Tyser #define RHRAR 0xFFE80028 290819833afSPeter Tyser #define RWKAR 0xFFE8002C 291819833afSPeter Tyser #define RDAYAR 0xFFE80030 292819833afSPeter Tyser #define RMONAR 0xFFE80034 293819833afSPeter Tyser #define RCR1 0xFFE80038 294819833afSPeter Tyser #define RCR2 0xFFE8003C 295819833afSPeter Tyser #define RCR3 0xFFE80050 296819833afSPeter Tyser #define RYRAR 0xFFE80054 297819833afSPeter Tyser 298819833afSPeter Tyser /* Serial Communication Interface with FIFO */ 299819833afSPeter Tyser #define SCSMR0 0xFFE00000 300efc0ba43SNobuhiro Iwamatsu #define SCIF0_BASE SCSMR0 301819833afSPeter Tyser 302819833afSPeter Tyser /* Serial I/O with FIFO */ 303819833afSPeter Tyser #define SIMDR 0xFFE20000 304819833afSPeter Tyser #define SISCR 0xFFE20002 305819833afSPeter Tyser #define SITDAR 0xFFE20004 306819833afSPeter Tyser #define SIRDAR 0xFFE20006 307819833afSPeter Tyser #define SICDAR 0xFFE20008 308819833afSPeter Tyser #define SICTR 0xFFE2000C 309819833afSPeter Tyser #define SIFCTR 0xFFE20010 310819833afSPeter Tyser #define SISTR 0xFFE20014 311819833afSPeter Tyser #define SIIER 0xFFE20016 312819833afSPeter Tyser #define SITCR 0xFFE20028 313819833afSPeter Tyser #define SIRCR 0xFFE2002C 314819833afSPeter Tyser #define SPICR 0xFFE20030 315819833afSPeter Tyser 316819833afSPeter Tyser /* Serial Protocol Interface */ 317819833afSPeter Tyser #define SPCR 0xFFE50000 318819833afSPeter Tyser #define SPSR 0xFFE50004 319819833afSPeter Tyser #define SPSCR 0xFFE50008 320819833afSPeter Tyser #define SPTBR 0xFFE5000C 321819833afSPeter Tyser #define SPRBR 0xFFE50010 322819833afSPeter Tyser 323819833afSPeter Tyser /* Multimedia Card Interface */ 324819833afSPeter Tyser #define CMDR0 0xFFE60000 325819833afSPeter Tyser #define CMDR1 0xFFE60001 326819833afSPeter Tyser #define CMDR2 0xFFE60002 327819833afSPeter Tyser #define CMDR3 0xFFE60003 328819833afSPeter Tyser #define CMDR4 0xFFE60004 329819833afSPeter Tyser #define CMDR5 0xFFE60005 330819833afSPeter Tyser #define CMDSTRT 0xFFE60006 331819833afSPeter Tyser #define OPCR 0xFFE6000A 332819833afSPeter Tyser #define CSTR 0xFFE6000B 333819833afSPeter Tyser #define INTCR0 0xFFE6000C 334819833afSPeter Tyser #define INTCR1 0xFFE6000D 335819833afSPeter Tyser #define INTSTR0 0xFFE6000E 336819833afSPeter Tyser #define INTSTR1 0xFFE6000F 337819833afSPeter Tyser #define CLKON 0xFFE60010 338819833afSPeter Tyser #define CTOCR 0xFFE60011 339819833afSPeter Tyser #define TBCR 0xFFE60014 340819833afSPeter Tyser #define MODER 0xFFE60016 341819833afSPeter Tyser #define CMDTYR 0xFFE60018 342819833afSPeter Tyser #define RSPTYR 0xFFE60019 343819833afSPeter Tyser #define TBNCR 0xFFE6001A 344819833afSPeter Tyser #define RSPR0 0xFFE60020 345819833afSPeter Tyser #define RSPR1 0xFFE60021 346819833afSPeter Tyser #define RSPR2 0xFFE60022 347819833afSPeter Tyser #define RSPR3 0xFFE60023 348819833afSPeter Tyser #define RSPR4 0xFFE60024 349819833afSPeter Tyser #define RSPR5 0xFFE60025 350819833afSPeter Tyser #define RSPR6 0xFFE60026 351819833afSPeter Tyser #define RSPR7 0xFFE60027 352819833afSPeter Tyser #define RSPR8 0xFFE60028 353819833afSPeter Tyser #define RSPR9 0xFFE60029 354819833afSPeter Tyser #define RSPR10 0xFFE6002A 355819833afSPeter Tyser #define RSPR11 0xFFE6002B 356819833afSPeter Tyser #define RSPR12 0xFFE6002C 357819833afSPeter Tyser #define RSPR13 0xFFE6002D 358819833afSPeter Tyser #define RSPR14 0xFFE6002E 359819833afSPeter Tyser #define RSPR15 0xFFE6002F 360819833afSPeter Tyser #define RSPR16 0xFFE60030 361819833afSPeter Tyser #define RSPRD 0xFFE60031 362819833afSPeter Tyser #define DTOUTR 0xFFE60032 363819833afSPeter Tyser #define DR 0xFFE60040 364819833afSPeter Tyser #define DMACR 0xFFE60044 365819833afSPeter Tyser #define INTCR2 0xFFE60046 366819833afSPeter Tyser #define INTSTR2 0xFFE60048 367819833afSPeter Tyser 368819833afSPeter Tyser /* Audio Codec Interface */ 369819833afSPeter Tyser #define HACCR 0xFFE40008 370819833afSPeter Tyser #define HACCSAR 0xFFE40020 371819833afSPeter Tyser #define HACCSDR 0xFFE40024 372819833afSPeter Tyser #define HACPCML 0xFFE40028 373819833afSPeter Tyser #define HACPCMR 0xFFE4002C 374819833afSPeter Tyser #define HACTIER 0xFFE40050 375819833afSPeter Tyser #define HACTSR 0xFFE40054 376819833afSPeter Tyser #define HACRIER 0xFFE40058 377819833afSPeter Tyser #define HACRSR 0xFFE4005C 378819833afSPeter Tyser #define HACACR 0xFFE40060 379819833afSPeter Tyser 380819833afSPeter Tyser /* Serial Sound Interface */ 381819833afSPeter Tyser #define SSICR 0xFFE70000 382819833afSPeter Tyser #define SSISR 0xFFE70004 383819833afSPeter Tyser #define SSITDR 0xFFE70008 384819833afSPeter Tyser #define SSIRDR 0xFFE7000C 385819833afSPeter Tyser 386819833afSPeter Tyser /* Flash memory Controller */ 387819833afSPeter Tyser #define FLCMNCR 0xFFE90000 388819833afSPeter Tyser #define FLCMDCR 0xFFE90004 389819833afSPeter Tyser #define FLCMCDR 0xFFE90008 390819833afSPeter Tyser #define FLADR 0xFFE9000C 391819833afSPeter Tyser #define FLDATAR 0xFFE90010 392819833afSPeter Tyser #define FLDTCNTR 0xFFE90014 393819833afSPeter Tyser #define FLINTDMACR 0xFFE90018 394819833afSPeter Tyser #define FLBSYTMR 0xFFE9001C 395819833afSPeter Tyser #define FLBSYCNT 0xFFE90020 396819833afSPeter Tyser #define FLTRCR 0xFFE9002C 397819833afSPeter Tyser 398819833afSPeter Tyser /* General Purpose I/O */ 399819833afSPeter Tyser #define PACR 0xFFEA0000 400819833afSPeter Tyser #define PBCR 0xFFEA0002 401819833afSPeter Tyser #define PCCR 0xFFEA0004 402819833afSPeter Tyser #define PDCR 0xFFEA0006 403819833afSPeter Tyser #define PECR 0xFFEA0008 404819833afSPeter Tyser #define PFCR 0xFFEA000A 405819833afSPeter Tyser #define PGCR 0xFFEA000C 406819833afSPeter Tyser #define PHCR 0xFFEA000E 407819833afSPeter Tyser #define PJCR 0xFFEA0010 408819833afSPeter Tyser #define PKCR 0xFFEA0012 409819833afSPeter Tyser #define PLCR 0xFFEA0014 410819833afSPeter Tyser #define PMCR 0xFFEA0016 411819833afSPeter Tyser #define PADR 0xFFEA0020 412819833afSPeter Tyser #define PBDR 0xFFEA0022 413819833afSPeter Tyser #define PCDR 0xFFEA0024 414819833afSPeter Tyser #define PDDR 0xFFEA0026 415819833afSPeter Tyser #define PEDR 0xFFEA0028 416819833afSPeter Tyser #define PFDR 0xFFEA002A 417819833afSPeter Tyser #define PGDR 0xFFEA002C 418819833afSPeter Tyser #define PHDR 0xFFEA002E 419819833afSPeter Tyser #define PJDR 0xFFEA0030 420819833afSPeter Tyser #define PKDR 0xFFEA0032 421819833afSPeter Tyser #define PLDR 0xFFEA0034 422819833afSPeter Tyser #define PMDR 0xFFEA0036 423819833afSPeter Tyser #define PEPUPR 0xFFEA0048 424819833afSPeter Tyser #define PHPUPR 0xFFEA004E 425819833afSPeter Tyser #define PJPUPR 0xFFEA0050 426819833afSPeter Tyser #define PKPUPR 0xFFEA0052 427819833afSPeter Tyser #define PMPUPR 0xFFEA0056 428819833afSPeter Tyser #define PPUPR1 0xFFEA0060 429819833afSPeter Tyser #define PPUPR2 0xFFEA0062 430819833afSPeter Tyser #define PMSELR 0xFFEA0080 431819833afSPeter Tyser 432819833afSPeter Tyser /* User Break Controller */ 433819833afSPeter Tyser #define CBR0 0xFF200000 434819833afSPeter Tyser #define CRR0 0xFF200004 435819833afSPeter Tyser #define CAR0 0xFF200008 436819833afSPeter Tyser #define CAMR0 0xFF20000C 437819833afSPeter Tyser #define CBR1 0xFF200020 438819833afSPeter Tyser #define CRR1 0xFF200024 439819833afSPeter Tyser #define CAR1 0xFF200028 440819833afSPeter Tyser #define CAMR1 0xFF20002C 441819833afSPeter Tyser #define CDR1 0xFF200030 442819833afSPeter Tyser #define CDMR1 0xFF200034 443819833afSPeter Tyser #define CETR1 0xFF200038 444819833afSPeter Tyser #define CCMFR 0xFF200600 445819833afSPeter Tyser #define CBCR 0xFF200620 446819833afSPeter Tyser 447819833afSPeter Tyser #endif /* _ASM_CPU_SH7780_H_ */ 448