xref: /openbmc/u-boot/arch/sh/include/asm/cpu_sh7264.h (revision bd061a52)
1 #ifndef _ASM_CPU_SH7264_H_
2 #define _ASM_CPU_SH7264_H_
3 
4 /* Cache */
5 #define CCR1		0xFFFC1000
6 #define CCR		CCR1
7 
8 /* PFC */
9 #define PACR		0xA4050100
10 #define PBCR		0xA4050102
11 #define PCCR		0xA4050104
12 #define PETCR		0xA4050106
13 
14 /* Port Data Registers */
15 #define PADR		0xA4050120
16 #define PBDR		0xA4050122
17 #define PCDR		0xA4050124
18 
19 /* BSC */
20 
21 /* SDRAM controller */
22 
23 /* SCIF */
24 #define SCSMR_3		0xFFFE9800
25 #define SCIF3_BASE	SCSMR_3
26 
27 /* Timer(CMT) */
28 #define CMSTR		0xFFFEC000
29 #define CMCSR_0 	0xFFFEC002
30 #define CMCNT_0 	0xFFFEC004
31 #define CMCOR_0 	0xFFFEC006
32 #define CMCSR_1 	0xFFFEC008
33 #define CMCNT_1 	0xFFFEC00A
34 #define CMCOR_1		0xFFFEC00C
35 
36 /* On chip oscillator circuits */
37 #define FRQCR		0xA415FF80
38 #define WTCNT		0xA415FF84
39 #define WTCSR		0xA415FF86
40 
41 #endif	/* _ASM_CPU_SH7264_H_ */
42