1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2320cf350SYoshihiro Shimoda /* 3320cf350SYoshihiro Shimoda * Copyright (C) 2012 Renesas Solutions Corp. 4320cf350SYoshihiro Shimoda */ 5320cf350SYoshihiro Shimoda 6320cf350SYoshihiro Shimoda #ifndef _ASM_CPU_SH7753_H_ 7320cf350SYoshihiro Shimoda #define _ASM_CPU_SH7753_H_ 8320cf350SYoshihiro Shimoda 9320cf350SYoshihiro Shimoda #define CCR 0xFF00001C 10320cf350SYoshihiro Shimoda #define WTCNT 0xFFCC0000 11320cf350SYoshihiro Shimoda #define CCR_CACHE_INIT 0x0000090b 12320cf350SYoshihiro Shimoda #define CACHE_OC_NUM_WAYS 1 13320cf350SYoshihiro Shimoda 14320cf350SYoshihiro Shimoda #ifndef __ASSEMBLY__ /* put C only stuff in this section */ 15320cf350SYoshihiro Shimoda /* MMU */ 16320cf350SYoshihiro Shimoda struct mmu_regs { 17320cf350SYoshihiro Shimoda unsigned int reserved[4]; 18320cf350SYoshihiro Shimoda unsigned int mmucr; 19320cf350SYoshihiro Shimoda }; 20320cf350SYoshihiro Shimoda #define MMU_BASE ((struct mmu_regs *)0xff000000) 21320cf350SYoshihiro Shimoda 22320cf350SYoshihiro Shimoda /* Watchdog */ 23320cf350SYoshihiro Shimoda #define WTCSR0 0xffcc0002 24320cf350SYoshihiro Shimoda #define WRSTCSR_R 0xffcc0003 25320cf350SYoshihiro Shimoda #define WRSTCSR_W 0xffcc0002 26320cf350SYoshihiro Shimoda #define WTCSR_PREFIX 0xa500 27320cf350SYoshihiro Shimoda #define WRSTCSR_PREFIX 0x6900 28320cf350SYoshihiro Shimoda #define WRSTCSR_WOVF_PREFIX 0x9600 29320cf350SYoshihiro Shimoda 30320cf350SYoshihiro Shimoda /* SCIF */ 31320cf350SYoshihiro Shimoda #define SCIF0_BASE 0xfe4b0000 /* The real name is SCIF2 */ 32320cf350SYoshihiro Shimoda #define SCIF1_BASE 0xfe4c0000 /* The real name is SCIF3 */ 33320cf350SYoshihiro Shimoda #define SCIF2_BASE 0xfe4d0000 /* The real name is SCIF4 */ 34320cf350SYoshihiro Shimoda 35320cf350SYoshihiro Shimoda /* TMU0 */ 36320cf350SYoshihiro Shimoda #define TMU_BASE 0xFE430000 37320cf350SYoshihiro Shimoda 38320cf350SYoshihiro Shimoda /* ETHER, GETHER MAC address */ 39320cf350SYoshihiro Shimoda struct ether_mac_regs { 40320cf350SYoshihiro Shimoda unsigned int reserved[114]; 41320cf350SYoshihiro Shimoda unsigned int mahr; 42320cf350SYoshihiro Shimoda unsigned int reserved2; 43320cf350SYoshihiro Shimoda unsigned int malr; 44320cf350SYoshihiro Shimoda }; 45320cf350SYoshihiro Shimoda #define GETHER0_MAC_BASE ((struct ether_mac_regs *)0xfee0400) 46320cf350SYoshihiro Shimoda #define GETHER1_MAC_BASE ((struct ether_mac_regs *)0xfee0c00) 47320cf350SYoshihiro Shimoda #define ETHER0_MAC_BASE ((struct ether_mac_regs *)0xfef0000) 48320cf350SYoshihiro Shimoda #define ETHER1_MAC_BASE ((struct ether_mac_regs *)0xfef0800) 49320cf350SYoshihiro Shimoda 50320cf350SYoshihiro Shimoda /* GETHER */ 51320cf350SYoshihiro Shimoda struct gether_control_regs { 52320cf350SYoshihiro Shimoda unsigned int gbecont; 53320cf350SYoshihiro Shimoda }; 54320cf350SYoshihiro Shimoda #define GETHER_CONTROL_BASE ((struct gether_control_regs *)0xffc10100) 55320cf350SYoshihiro Shimoda #define GBECONT_RMII1 0x00020000 56320cf350SYoshihiro Shimoda #define GBECONT_RMII0 0x00010000 57320cf350SYoshihiro Shimoda 58320cf350SYoshihiro Shimoda /* SerMux */ 59320cf350SYoshihiro Shimoda struct sermux_regs { 60320cf350SYoshihiro Shimoda unsigned char smr0; 61320cf350SYoshihiro Shimoda unsigned char smr1; 62320cf350SYoshihiro Shimoda unsigned char smr2; 63320cf350SYoshihiro Shimoda unsigned char smr3; 64320cf350SYoshihiro Shimoda unsigned char smr4; 65320cf350SYoshihiro Shimoda unsigned char smr5; 66320cf350SYoshihiro Shimoda }; 67320cf350SYoshihiro Shimoda #define SERMUX_BASE ((struct sermux_regs *)0xfe470000) 68320cf350SYoshihiro Shimoda 69320cf350SYoshihiro Shimoda 70320cf350SYoshihiro Shimoda /* USB0/1 */ 71320cf350SYoshihiro Shimoda struct usb_common_regs { 72320cf350SYoshihiro Shimoda unsigned short reserved[129]; 73320cf350SYoshihiro Shimoda unsigned short suspmode; 74320cf350SYoshihiro Shimoda }; 75320cf350SYoshihiro Shimoda #define USB0_COMMON_BASE ((struct usb_common_regs *)0xfe450000) 76320cf350SYoshihiro Shimoda #define USB1_COMMON_BASE ((struct usb_common_regs *)0xfe4f0000) 77320cf350SYoshihiro Shimoda 78320cf350SYoshihiro Shimoda struct usb0_phy_regs { 79320cf350SYoshihiro Shimoda unsigned short reset; 80320cf350SYoshihiro Shimoda unsigned short reserved[4]; 81320cf350SYoshihiro Shimoda unsigned short portsel; 82320cf350SYoshihiro Shimoda }; 83320cf350SYoshihiro Shimoda #define USB0_PHY_BASE ((struct usb0_phy_regs *)0xfe5f0000) 84320cf350SYoshihiro Shimoda 85320cf350SYoshihiro Shimoda struct usb1_port_regs { 86320cf350SYoshihiro Shimoda unsigned int port1sel; 87320cf350SYoshihiro Shimoda unsigned int reserved; 88320cf350SYoshihiro Shimoda unsigned int usb1intsts; 89320cf350SYoshihiro Shimoda }; 90320cf350SYoshihiro Shimoda #define USB1_PORT_BASE ((struct usb1_port_regs *)0xfe4f2000) 91320cf350SYoshihiro Shimoda 92320cf350SYoshihiro Shimoda struct usb1_alignment_regs { 93320cf350SYoshihiro Shimoda unsigned int ehcidatac; /* 0xfe4fe018 */ 94320cf350SYoshihiro Shimoda unsigned int reserved[63]; 95320cf350SYoshihiro Shimoda unsigned int ohcidatac; 96320cf350SYoshihiro Shimoda }; 97320cf350SYoshihiro Shimoda #define USB1_ALIGNMENT_BASE ((struct usb1_alignment_regs *)0xfe4fe018) 98320cf350SYoshihiro Shimoda 99320cf350SYoshihiro Shimoda /* GPIO */ 100320cf350SYoshihiro Shimoda struct gpio_regs { 101320cf350SYoshihiro Shimoda unsigned short pacr; 102320cf350SYoshihiro Shimoda unsigned short pbcr; 103320cf350SYoshihiro Shimoda unsigned short pccr; 104320cf350SYoshihiro Shimoda unsigned short pdcr; 105320cf350SYoshihiro Shimoda unsigned short pecr; 106320cf350SYoshihiro Shimoda unsigned short pfcr; 107320cf350SYoshihiro Shimoda unsigned short pgcr; 108320cf350SYoshihiro Shimoda unsigned short phcr; 109320cf350SYoshihiro Shimoda unsigned short picr; 110320cf350SYoshihiro Shimoda unsigned short pjcr; 111320cf350SYoshihiro Shimoda unsigned short pkcr; 112320cf350SYoshihiro Shimoda unsigned short plcr; 113320cf350SYoshihiro Shimoda unsigned short pmcr; 114320cf350SYoshihiro Shimoda unsigned short pncr; 115320cf350SYoshihiro Shimoda unsigned short pocr; 116320cf350SYoshihiro Shimoda unsigned short reserved; 117320cf350SYoshihiro Shimoda unsigned short pqcr; 118320cf350SYoshihiro Shimoda unsigned short prcr; 119320cf350SYoshihiro Shimoda unsigned short pscr; 120320cf350SYoshihiro Shimoda unsigned short ptcr; 121320cf350SYoshihiro Shimoda unsigned short pucr; 122320cf350SYoshihiro Shimoda unsigned short pvcr; 123320cf350SYoshihiro Shimoda unsigned short pwcr; 124320cf350SYoshihiro Shimoda unsigned short pxcr; 125320cf350SYoshihiro Shimoda unsigned short pycr; 126320cf350SYoshihiro Shimoda unsigned short pzcr; 127320cf350SYoshihiro Shimoda unsigned char padr; 128320cf350SYoshihiro Shimoda unsigned char reserved_a; 129320cf350SYoshihiro Shimoda unsigned char pbdr; 130320cf350SYoshihiro Shimoda unsigned char reserved_b; 131320cf350SYoshihiro Shimoda unsigned char pcdr; 132320cf350SYoshihiro Shimoda unsigned char reserved_c; 133320cf350SYoshihiro Shimoda unsigned char pddr; 134320cf350SYoshihiro Shimoda unsigned char reserved_d; 135320cf350SYoshihiro Shimoda unsigned char pedr; 136320cf350SYoshihiro Shimoda unsigned char reserved_e; 137320cf350SYoshihiro Shimoda unsigned char pfdr; 138320cf350SYoshihiro Shimoda unsigned char reserved_f; 139320cf350SYoshihiro Shimoda unsigned char pgdr; 140320cf350SYoshihiro Shimoda unsigned char reserved_g; 141320cf350SYoshihiro Shimoda unsigned char phdr; 142320cf350SYoshihiro Shimoda unsigned char reserved_h; 143320cf350SYoshihiro Shimoda unsigned char pidr; 144320cf350SYoshihiro Shimoda unsigned char reserved_i; 145320cf350SYoshihiro Shimoda unsigned char pjdr; 146320cf350SYoshihiro Shimoda unsigned char reserved_j; 147320cf350SYoshihiro Shimoda unsigned char pkdr; 148320cf350SYoshihiro Shimoda unsigned char reserved_k; 149320cf350SYoshihiro Shimoda unsigned char pldr; 150320cf350SYoshihiro Shimoda unsigned char reserved_l; 151320cf350SYoshihiro Shimoda unsigned char pmdr; 152320cf350SYoshihiro Shimoda unsigned char reserved_m; 153320cf350SYoshihiro Shimoda unsigned char pndr; 154320cf350SYoshihiro Shimoda unsigned char reserved_n; 155320cf350SYoshihiro Shimoda unsigned char podr; 156320cf350SYoshihiro Shimoda unsigned char reserved_o; 157320cf350SYoshihiro Shimoda unsigned char ppdr; 158320cf350SYoshihiro Shimoda unsigned char reserved_p; 159320cf350SYoshihiro Shimoda unsigned char pqdr; 160320cf350SYoshihiro Shimoda unsigned char reserved_q; 161320cf350SYoshihiro Shimoda unsigned char prdr; 162320cf350SYoshihiro Shimoda unsigned char reserved_r; 163320cf350SYoshihiro Shimoda unsigned char psdr; 164320cf350SYoshihiro Shimoda unsigned char reserved_s; 165320cf350SYoshihiro Shimoda unsigned char ptdr; 166320cf350SYoshihiro Shimoda unsigned char reserved_t; 167320cf350SYoshihiro Shimoda unsigned char pudr; 168320cf350SYoshihiro Shimoda unsigned char reserved_u; 169320cf350SYoshihiro Shimoda unsigned char pvdr; 170320cf350SYoshihiro Shimoda unsigned char reserved_v; 171320cf350SYoshihiro Shimoda unsigned char pwdr; 172320cf350SYoshihiro Shimoda unsigned char reserved_w; 173320cf350SYoshihiro Shimoda unsigned char pxdr; 174320cf350SYoshihiro Shimoda unsigned char reserved_x; 175320cf350SYoshihiro Shimoda unsigned char pydr; 176320cf350SYoshihiro Shimoda unsigned char reserved_y; 177320cf350SYoshihiro Shimoda unsigned char pzdr; 178320cf350SYoshihiro Shimoda unsigned char reserved_z; 179320cf350SYoshihiro Shimoda unsigned short ncer; 180320cf350SYoshihiro Shimoda unsigned short ncmcr; 181320cf350SYoshihiro Shimoda unsigned short nccsr; 182320cf350SYoshihiro Shimoda unsigned char reserved2[2]; 183320cf350SYoshihiro Shimoda unsigned short psel0; /* +0x70 */ 184320cf350SYoshihiro Shimoda unsigned short psel1; 185320cf350SYoshihiro Shimoda unsigned short psel2; 186320cf350SYoshihiro Shimoda unsigned short psel3; 187320cf350SYoshihiro Shimoda unsigned short psel4; 188320cf350SYoshihiro Shimoda unsigned short psel5; 189320cf350SYoshihiro Shimoda unsigned short psel6; 190320cf350SYoshihiro Shimoda unsigned short reserved3[2]; 191320cf350SYoshihiro Shimoda unsigned short psel7; 192320cf350SYoshihiro Shimoda }; 193320cf350SYoshihiro Shimoda #define GPIO_BASE ((struct gpio_regs *)0xffec0000) 194320cf350SYoshihiro Shimoda 195320cf350SYoshihiro Shimoda #endif /* ifndef __ASSEMBLY__ */ 196320cf350SYoshihiro Shimoda #endif /* _ASM_CPU_SH7753_H_ */ 197