/openbmc/linux/Documentation/driver-api/media/drivers/ccs/ |
H A D | ccs.rst | 104 CCS PLL calculator 107 The CCS PLL calculator is used to compute the PLL configuration, given sensor's 110 PLL calculator isn't entirely trivial. Yet it is relatively simple to use for a 113 The PLL model implemented by the PLL calculator corresponds to MIPI CCS 1.1.
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/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | nvidia,tegra186-xusb.yaml | 43 - description: USB PLL 45 - description: I/O PLL 114 description: UTMI PLL power supply. Must supply 1.8 V. 117 description: PLLE reference PLL power supply. Must supply 1.05 V. 120 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
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H A D | nvidia,tegra194-xusb.yaml | 43 - description: USB PLL 45 - description: I/O PLL 115 description: UTMI PLL power supply. Must supply 1.8 V. 118 description: PLLE reference PLL power supply. Must supply 1.05 V. 121 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
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H A D | nvidia,tegra124-xusb.yaml | 55 - description: USB PLL 57 - description: I/O PLL 118 description: UTMI PLL power supply. Must supply 1.8 V. 121 description: PLLE reference PLL power supply. Must supply 1.05 V. 124 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
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H A D | nvidia,tegra210-xusb.yaml | 47 - description: USB PLL 49 - description: I/O PLL 121 description: UTMI PLL power supply. Must supply 1.8 V. 124 description: PLLE reference PLL power supply. Must supply 1.05 V. 127 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | keystone-pll.txt | 3 Binding for keystone PLLs. The main PLL IP typically has a multiplier, 4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL 6 PLL is controlled by a PLL controller registers along with memory mapped
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H A D | samsung,s5pv210-audss-clock.yaml | 29 Optional fixed rate PLL reference clock, parent of mout_audss. If not 30 specified (i.e. xusbxti is used for PLL reference), it is fixed to a 33 Input PLL to the AudioSS block, parent of mout_audss.
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H A D | brcm,bcm2835-cprman.txt | 8 oscillator, a level of PLL dividers that produce channels off of the 10 the PLL channels. Most other hardware components source from the 12 the PLL dividers directly.
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H A D | snps,hsdk-pll-clock.txt | 1 Binding for the HSDK Generic PLL clock 13 - clocks: shall be the input parent clock phandle for the PLL.
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H A D | mstar,msc313-cpupll.yaml | 7 title: MStar/Sigmastar MSC313 CPU PLL 14 PLL that can be used as the clock source for the CPU(s).
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H A D | fsl,imx8m-anatop.yaml | 13 NXP i.MX8M Family anatop PLL module which generates PLL to CCM root.
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H A D | toshiba,tmpv770x-pipllct.yaml | 7 title: Toshiba Visconti5 TMPV770X PLL Controller 13 Toshia Visconti5 PLL controller which supports the PLLs on TMPV770X.
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H A D | silabs,si5341.txt | 13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which 21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not 52 - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL 53 feedback divider. Must be such that the PLL output is in the valid range. For 56 If these are not specified, and the PLL is not yet programmed when the driver 57 probes, the PLL will be set to 14GHz. 117 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
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H A D | qcom,a7pll.yaml | 7 title: Qualcomm A7 PLL clock 13 The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
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H A D | starfive,jh7110-pll.yaml | 7 title: StarFive JH7110 PLL Clock Generator 11 Each PLL works in integer mode or fraction mode, with configuration
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H A D | moxa,moxart-clock.txt | 7 MOXA ART SoCs allow to determine PLL output and APB frequencies 11 PLL:
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H A D | mediatek,mt8186-fhctl.yaml | 30 description: Phandles of the PLL with FHCTL hardware capability. 35 description: The percentage of spread spectrum clocking for one PLL.
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/openbmc/linux/Documentation/devicetree/bindings/display/ |
H A D | allwinner,sun4i-a10-hdmi.yaml | 38 - description: The first video PLL 39 - description: The second video PLL 45 - description: The first video PLL 46 - description: The second video PLL
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/openbmc/u-boot/doc/imx/common/ |
H A D | imx5.txt | 9 1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata. 12 The PLL's in the i.MX51 processor can go out of lock due to a metastable 14 This workaround implements an undocumented feature in the PLL (dither
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/openbmc/linux/drivers/clk/samsung/ |
H A D | clk-s5pv210.c | 716 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll", 718 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 720 [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll", 722 [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc", 728 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll", 730 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll", 732 [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll", 734 [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
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/openbmc/u-boot/doc/ |
H A D | README.Heterogeneous-SoCs | 63 Following are the defines for PLL's index that provide the Clocking to 66 CONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock 67 CONFIG_SYS_ULB_CLK - Define PLL index for ULB clock 68 CONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock
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/openbmc/u-boot/drivers/clk/mediatek/ |
H A D | clk-mt7629.c | 31 #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \ macro 48 PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0, 50 PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR, 52 PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR, 54 PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0, 56 PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0, 58 PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
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/openbmc/linux/Documentation/admin-guide/media/ |
H A D | frontend-cardlist.rst | 13 tuner/PLL chips, and not all combinations are supported. Often 14 the demodulator and tuner/PLL chip are inside a metal box for 87 tua6100 Infineon TUA6100 PLL 131 Digital terrestrial only tuners/PLL 137 dvb-pll Generic I2C PLL based tuners
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/openbmc/linux/arch/arm/boot/dts/arm/ |
H A D | vexpress-v2p-ca15-tc1.dts | 146 /* CPU PLL reference clock */ 164 /* HDLCD PLL reference clock */ 182 /* SYS PLL reference clock */ 191 /* DDR2 PLL reference clock */
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/openbmc/linux/drivers/media/common/b2c2/ |
H A D | flexcop-fe-tuner.c | 41 #if (FE_SUPPORTED(MT312) || FE_SUPPORTED(STV0299)) && FE_SUPPORTED(PLL) 81 #if FE_SUPPORTED(MT312) && FE_SUPPORTED(PLL) 197 #if FE_SUPPORTED(STV0299) && FE_SUPPORTED(PLL) 421 #if FE_SUPPORTED(MT352) && FE_SUPPORTED(PLL) 476 #if FE_SUPPORTED(NXT200X) && FE_SUPPORTED(PLL) 519 #if FE_SUPPORTED(STV0297) && FE_SUPPORTED(PLL)
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