1daeeb438SEugeniy PaltsevBinding for the HSDK Generic PLL clock
2daeeb438SEugeniy Paltsev
3daeeb438SEugeniy PaltsevThis binding uses the common clock binding[1].
4daeeb438SEugeniy Paltsev
5daeeb438SEugeniy Paltsev[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6daeeb438SEugeniy Paltsev
7daeeb438SEugeniy PaltsevRequired properties:
8daeeb438SEugeniy Paltsev- compatible: should be "snps,hsdk-<name>-pll-clock"
9daeeb438SEugeniy Paltsev  "snps,hsdk-core-pll-clock"
10daeeb438SEugeniy Paltsev  "snps,hsdk-gp-pll-clock"
11daeeb438SEugeniy Paltsev  "snps,hsdk-hdmi-pll-clock"
12daeeb438SEugeniy Paltsev- reg : should contain base register location and length.
13daeeb438SEugeniy Paltsev- clocks: shall be the input parent clock phandle for the PLL.
14daeeb438SEugeniy Paltsev- #clock-cells: from common clock binding; Should always be set to 0.
15daeeb438SEugeniy Paltsev
16daeeb438SEugeniy PaltsevExample:
17daeeb438SEugeniy Paltsev	input_clk: input-clk {
18daeeb438SEugeniy Paltsev		clock-frequency = <33333333>;
19daeeb438SEugeniy Paltsev		compatible = "fixed-clock";
20daeeb438SEugeniy Paltsev		#clock-cells = <0>;
21daeeb438SEugeniy Paltsev	};
22daeeb438SEugeniy Paltsev
23daeeb438SEugeniy Paltsev	cpu_clk: cpu-clk@0 {
24daeeb438SEugeniy Paltsev		compatible = "snps,hsdk-core-pll-clock";
25daeeb438SEugeniy Paltsev		reg = <0x00 0x10>;
26daeeb438SEugeniy Paltsev		#clock-cells = <0>;
27daeeb438SEugeniy Paltsev		clocks = <&input_clk>;
28daeeb438SEugeniy Paltsev	};
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