1*b8bf0adcSShaveta LeekhaDSP side awareness for Freescale heterogeneous multicore chips based on 2*b8bf0adcSShaveta LeekhaStarCore and Power Architecture 3*b8bf0adcSShaveta Leekha=============================================================== 4*b8bf0adcSShaveta Leekhapowerpc/mpc85xx code ve APIs and function to get the number, 5*b8bf0adcSShaveta Leekhaconfiguration and frequencies of all PowerPC cores and devices 6*b8bf0adcSShaveta Leekhaconnected to them, but it didnt have the similar code ofr HEterogeneous 7*b8bf0adcSShaveta LeekhaSC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc. 8*b8bf0adcSShaveta Leekha 9*b8bf0adcSShaveta LeekhaCode for DSP side awareness provides such functionality for Freescale 10*b8bf0adcSShaveta LeekhaHeterogeneous SoCs which are chasis-2 compliant like B4860 and B4420 11*b8bf0adcSShaveta Leekha 12*b8bf0adcSShaveta LeekhaAs part of this feature, following changes have been made: 13*b8bf0adcSShaveta Leekha========================================================== 14*b8bf0adcSShaveta Leekha 15*b8bf0adcSShaveta Leekha1. Changed files: 16*b8bf0adcSShaveta Leekha================= 17*b8bf0adcSShaveta Leekha- arch/powerpc/cpu/mpc85xx/cpu.c 18*b8bf0adcSShaveta Leekha 19*b8bf0adcSShaveta LeekhaCode added in this file to print the DSP cores and other device's(CPRI, 20*b8bf0adcSShaveta LeekhaMAPLE etc) frequencies 21*b8bf0adcSShaveta Leekha 22*b8bf0adcSShaveta Leekha- arch/powerpc/cpu/mpc85xx/speed.c 23*b8bf0adcSShaveta Leekha 24*b8bf0adcSShaveta LeekhaAdded Defines and code to extract the frequncy information for all 25*b8bf0adcSShaveta Leekharequired cores and devices from RCW and System frequency 26*b8bf0adcSShaveta Leekha 27*b8bf0adcSShaveta Leekha- arch/powerpc/cpu/mpc8xxx/cpu.c 28*b8bf0adcSShaveta Leekha 29*b8bf0adcSShaveta LeekhaAdded API to get the number of SC cores in running system and Their BIT 30*b8bf0adcSShaveta LeekhaMASK, similar to the code written for PowerPC 31*b8bf0adcSShaveta Leekha 32*b8bf0adcSShaveta Leekha- arch/powerpc/include/asm/config_mpc85xx.h 33*b8bf0adcSShaveta Leekha 34*b8bf0adcSShaveta LeekhaAdded top level CONFIG to identify presence of HETEROGENUOUS clusters 35*b8bf0adcSShaveta Leekhain the system and CONFIGS for SC3900/DSP components 36*b8bf0adcSShaveta Leekha 37*b8bf0adcSShaveta Leekha- arch/powerpc/include/asm/processor.h 38*b8bf0adcSShaveta Leekha- include/common.h 39*b8bf0adcSShaveta Leekha 40*b8bf0adcSShaveta LeekhaAdded newly added Functions Declaration 41*b8bf0adcSShaveta Leekha 42*b8bf0adcSShaveta Leekha- include/e500.h 43*b8bf0adcSShaveta Leekha 44*b8bf0adcSShaveta LeekhaGlobal structure updated for dsp cores and other components 45*b8bf0adcSShaveta Leekha 46*b8bf0adcSShaveta Leekha2. CONFIGs ADDED 47*b8bf0adcSShaveta Leekha================ 48*b8bf0adcSShaveta Leekha 49*b8bf0adcSShaveta LeekhaCONFIG_HETROGENOUS_CLUSTERS - Define for checking the presence of 50*b8bf0adcSShaveta Leekha DSP/SC3900 core clusters 51*b8bf0adcSShaveta Leekha 52*b8bf0adcSShaveta LeekhaCONFIG_SYS_FSL_NUM_CC_PLLS - Define for number of PLLs 53*b8bf0adcSShaveta Leekha 54*b8bf0adcSShaveta LeekhaThough there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 - 55*b8bf0adcSShaveta LeekhaPLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the 56*b8bf0adcSShaveta Leekhavalue as 5 not 4, to iterate over all PLLs while coding 57*b8bf0adcSShaveta Leekha 58*b8bf0adcSShaveta LeekhaCONFIG_SYS_MAPLE - Define for MAPLE Baseband Accelerator 59*b8bf0adcSShaveta LeekhaCONFIG_SYS_CPRI - Define for CPRI Interface 60*b8bf0adcSShaveta LeekhaCONFIG_PPC_CLUSTER_START - Start index of ppc clusters 61*b8bf0adcSShaveta LeekhaCONFIG_DSP_CLUSTER_START - Start index of dsp clusters 62*b8bf0adcSShaveta Leekha 63*b8bf0adcSShaveta LeekhaFollowing are the defines for PLL's index that provide the Clocking to 64*b8bf0adcSShaveta LeekhaCPRI, ULB and ETVE components 65*b8bf0adcSShaveta Leekha 66*b8bf0adcSShaveta LeekhaCONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock 67*b8bf0adcSShaveta LeekhaCONFIG_SYS_ULB_CLK - Define PLL index for ULB clock 68*b8bf0adcSShaveta LeekhaCONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock 69*b8bf0adcSShaveta Leekha 70*b8bf0adcSShaveta Leekha3. Changes in MPC85xx_SYS_INFO Global structure 71*b8bf0adcSShaveta Leekha=============================================== 72*b8bf0adcSShaveta Leekha 73*b8bf0adcSShaveta LeekhaDSP cores and other device's components have been added in this structure. 74*b8bf0adcSShaveta Leekha 75*b8bf0adcSShaveta Leekhafreq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies 76*b8bf0adcSShaveta Leekhafreq_cpri - To store CPRI frequency 77*b8bf0adcSShaveta Leekhafreq_maple - To store MAPLE frequency 78*b8bf0adcSShaveta Leekhafreq_maple_ulb - To store MAPLE-ULB frequency 79*b8bf0adcSShaveta Leekhafreq_maple_etvpe - To store MAPLE-eTVPE frequency 80*b8bf0adcSShaveta Leekha 81*b8bf0adcSShaveta Leekha4. U-BOOT LOGS 82*b8bf0adcSShaveta Leekha============== 83*b8bf0adcSShaveta Leekha4.1 B4860QDS board 84*b8bf0adcSShaveta Leekha Boot from NOR flash 85*b8bf0adcSShaveta Leekha 86*b8bf0adcSShaveta LeekhaU-Boot 2014.07-00222-g70587a8-dirty (Aug 07 2014 - 13:15:47) 87*b8bf0adcSShaveta Leekha 88*b8bf0adcSShaveta LeekhaCPU0: B4860E, Version: 2.0, (0x86880020) 89*b8bf0adcSShaveta LeekhaCore: e6500, Version: 2.0, (0x80400020) Clock Configuration: 90*b8bf0adcSShaveta Leekha CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz, 91*b8bf0adcSShaveta Leekha DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz, 92*b8bf0adcSShaveta Leekha DSP CPU4:1200 MHz, DSP CPU5:1200 MHz, 93*b8bf0adcSShaveta Leekha CCB:666.667 MHz, 94*b8bf0adcSShaveta Leekha DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz 95*b8bf0adcSShaveta Leekha CPRI:600 MHz 96*b8bf0adcSShaveta Leekha MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz 97*b8bf0adcSShaveta Leekha FMAN1: 666.667 MHz 98*b8bf0adcSShaveta Leekha QMAN: 333.333 MHz 99*b8bf0adcSShaveta Leekha 100*b8bf0adcSShaveta LeekhaCPUn - PowerPC core 101*b8bf0adcSShaveta LeekhaDSP CPUn - SC3900 core 102*b8bf0adcSShaveta Leekha 103*b8bf0adcSShaveta LeekhaShaveta Leekha(shaveta@freescale.com) 104*b8bf0adcSShaveta LeekhaCreated August 7, 2014 105*b8bf0adcSShaveta Leekha=========================================== 106