1b9e0d40cSSantosh ShilimkarStatus: Unstable - ABI compatibility may be broken in the future
2b9e0d40cSSantosh Shilimkar
3b9e0d40cSSantosh ShilimkarBinding for keystone PLLs. The main PLL IP typically has a multiplier,
4b9e0d40cSSantosh Shilimkara divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
5b9e0d40cSSantosh Shilimkarand PAPLL are controlled by the memory mapped register where as the Main
6b9e0d40cSSantosh ShilimkarPLL is controlled by a PLL controller registers along with memory mapped
7b9e0d40cSSantosh Shilimkarregisters.
8b9e0d40cSSantosh Shilimkar
9b9e0d40cSSantosh ShilimkarThis binding uses the common clock binding[1].
10b9e0d40cSSantosh Shilimkar
11b9e0d40cSSantosh Shilimkar[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12b9e0d40cSSantosh Shilimkar
13b9e0d40cSSantosh ShilimkarRequired properties:
14b9e0d40cSSantosh Shilimkar- #clock-cells : from common clock binding; shall be set to 0.
15b9e0d40cSSantosh Shilimkar- compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16b9e0d40cSSantosh Shilimkar- clocks : parent clock phandle
17*47aab533SBjorn Helgaas- reg - pll control0 and pll multiplier registers
1802fdfd70SMurali Karicheri- reg-names : control, multiplier and post-divider. The multiplier and
1902fdfd70SMurali Karicheri		post-divider registers are applicable only for main pll clock
20dbb4e67fSMurali Karicheri- fixed-postdiv : fixed post divider value. If absent, use clkod register bits
21dbb4e67fSMurali Karicheri		for postdiv
22b9e0d40cSSantosh Shilimkar
23b9e0d40cSSantosh ShilimkarExample:
24b9e0d40cSSantosh Shilimkar	mainpllclk: mainpllclk@2310110 {
25b9e0d40cSSantosh Shilimkar		#clock-cells = <0>;
26b9e0d40cSSantosh Shilimkar		compatible = "ti,keystone,main-pll-clock";
27dbb4e67fSMurali Karicheri		clocks = <&refclksys>;
2802fdfd70SMurali Karicheri		reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
2902fdfd70SMurali Karicheri		reg-names = "control", "multiplier", "post-divider";
30b9e0d40cSSantosh Shilimkar		fixed-postdiv = <2>;
31b9e0d40cSSantosh Shilimkar	};
32b9e0d40cSSantosh Shilimkar
33b9e0d40cSSantosh Shilimkar	papllclk: papllclk@2620358 {
34b9e0d40cSSantosh Shilimkar		#clock-cells = <0>;
35b9e0d40cSSantosh Shilimkar		compatible = "ti,keystone,pll-clock";
36dbb4e67fSMurali Karicheri		clocks = <&refclkpass>;
37b9e0d40cSSantosh Shilimkar		clock-output-names = "pa-pll-clk";
38b9e0d40cSSantosh Shilimkar		reg = <0x02620358 4>;
39b9e0d40cSSantosh Shilimkar		reg-names = "control";
40b9e0d40cSSantosh Shilimkar	};
41b9e0d40cSSantosh Shilimkar
42b9e0d40cSSantosh ShilimkarRequired properties:
43b9e0d40cSSantosh Shilimkar- #clock-cells : from common clock binding; shall be set to 0.
44b9e0d40cSSantosh Shilimkar- compatible : shall be "ti,keystone,pll-mux-clock"
45b9e0d40cSSantosh Shilimkar- clocks : link phandles of parent clocks
46b9e0d40cSSantosh Shilimkar- reg - pll mux register
47b9e0d40cSSantosh Shilimkar- bit-shift : number of bits to shift the bit-mask
48b9e0d40cSSantosh Shilimkar- bit-mask : arbitrary bitmask for programming the mux
49b9e0d40cSSantosh Shilimkar
50b9e0d40cSSantosh ShilimkarOptional properties:
51b9e0d40cSSantosh Shilimkar- clock-output-names : From common clock binding.
52b9e0d40cSSantosh Shilimkar
53b9e0d40cSSantosh ShilimkarExample:
54b9e0d40cSSantosh Shilimkar	mainmuxclk: mainmuxclk@2310108 {
55b9e0d40cSSantosh Shilimkar		#clock-cells = <0>;
56b9e0d40cSSantosh Shilimkar		compatible = "ti,keystone,pll-mux-clock";
57b9e0d40cSSantosh Shilimkar		clocks = <&mainpllclk>, <&refclkmain>;
58b9e0d40cSSantosh Shilimkar		reg = <0x02310108 4>;
59b9e0d40cSSantosh Shilimkar		bit-shift = <23>;
60b9e0d40cSSantosh Shilimkar		bit-mask = <1>;
61b9e0d40cSSantosh Shilimkar		clock-output-names = "mainmuxclk";
62b9e0d40cSSantosh Shilimkar	};
63b9e0d40cSSantosh Shilimkar
64b9e0d40cSSantosh ShilimkarRequired properties:
65b9e0d40cSSantosh Shilimkar- #clock-cells : from common clock binding; shall be set to 0.
66b9e0d40cSSantosh Shilimkar- compatible : shall be "ti,keystone,pll-divider-clock"
67b9e0d40cSSantosh Shilimkar- clocks : parent clock phandle
68b9e0d40cSSantosh Shilimkar- reg - pll mux register
69b9e0d40cSSantosh Shilimkar- bit-shift : number of bits to shift the bit-mask
70b9e0d40cSSantosh Shilimkar- bit-mask : arbitrary bitmask for programming the divider
71b9e0d40cSSantosh Shilimkar
72b9e0d40cSSantosh ShilimkarOptional properties:
73b9e0d40cSSantosh Shilimkar- clock-output-names : From common clock binding.
74b9e0d40cSSantosh Shilimkar
75b9e0d40cSSantosh ShilimkarExample:
76b9e0d40cSSantosh Shilimkar	gemtraceclk: gemtraceclk@2310120 {
77b9e0d40cSSantosh Shilimkar		#clock-cells = <0>;
78b9e0d40cSSantosh Shilimkar		compatible = "ti,keystone,pll-divider-clock";
79b9e0d40cSSantosh Shilimkar		clocks = <&mainmuxclk>;
80b9e0d40cSSantosh Shilimkar		reg = <0x02310120 4>;
81b9e0d40cSSantosh Shilimkar		bit-shift = <0>;
82b9e0d40cSSantosh Shilimkar		bit-mask = <8>;
83b9e0d40cSSantosh Shilimkar		clock-output-names = "gemtraceclk";
84b9e0d40cSSantosh Shilimkar	};
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